@@ -16,7 +16,7 @@
# define ERR_PTR(val) NULL
#endif
-#define evex_encoded() (s->evex.mbs)
+#define evex_encoded() (s->evex.opcx)
struct x86_emulate_state *
x86_decode_insn(
@@ -1179,8 +1179,15 @@ int x86emul_decode(struct x86_emulate_st
s->evex.raw[1] = s->vex.raw[1];
s->evex.raw[2] = insn_fetch_type(uint8_t);
- generate_exception_if(!s->evex.mbs || s->evex.mbz, X86_EXC_UD);
- generate_exception_if(!s->evex.opmsk && s->evex.z, X86_EXC_UD);
+ /*
+ * .opcx is being checked here just to be on the safe
+ * side, especially as long as evex_encoded() uses
+ * this field.
+ */
+ generate_exception_if(s->evex.mbz || !s->evex.opcx,
+ X86_EXC_UD);
+ generate_exception_if(!s->evex.opmsk && s->evex.z,
+ X86_EXC_UD);
if ( !mode_64bit() )
s->evex.R = 1;
@@ -1758,6 +1765,12 @@ int x86emul_decode(struct x86_emulate_st
if ( override_seg != x86_seg_none )
s->ea.mem.seg = override_seg;
+ generate_exception_if((evex_encoded() &&
+ !s->evex.u &&
+ (s->modrm_mod != 3 ||
+ !vcpu_has_avx10(2) || !s->evex.brs)),
+ X86_EXC_UD);
+
/* Fetch the immediate operand, if present. */
switch ( d & SrcMask )
{
@@ -221,7 +221,7 @@ union evex {
uint8_t x:1; /* X */
uint8_t r:1; /* R */
uint8_t pfx:2; /* pp */
- uint8_t mbs:1;
+ uint8_t u:1; /* U */
uint8_t reg:4; /* vvvv */
uint8_t w:1; /* W */
uint8_t opmsk:3; /* aaa */
@@ -582,6 +582,8 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert)
#define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16)
+#define vcpu_has_avx10(minor) (ctxt->cpuid->avx10.version >= (minor))
+
#define vcpu_must_have(feat) \
generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD)
@@ -1240,7 +1240,7 @@ int cf_check x86emul_unhandleable_rw(
#define lock_prefix (state->lock_prefix)
#define vex (state->vex)
#define evex (state->evex)
-#define evex_encoded() (evex.mbs)
+#define evex_encoded() (evex.opcx)
#define ea (state->ea)
/* Undo DEBUG wrapper. */
AVX10.2 (along with APX) assigns new meaning to the bit that previsouly distinguished EVEX from the Phi co-processor's MVEX. Therefore evex_encoded() now needs to key off of something else: Use the opcode mapping field for this, leveraging that map 0 has no assigned opcodes (and appears unlikely to gain any). Place the check of EVEX.U such that it'll cover all insns. EVEX.b is being checked for individual insns as applicable - whenever that's valid for (register-only) 512-bit forms, it becomes valid for 256-bit forms as well when AVX10.2 is permitted for a guest. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- To raise the question early: It is entirely unclear to me how we want to allow control over the AVX10 minor version number from guest configs, as that's not a boolean field and hence not suitable for simple bit-wise masking of feature sets. --- v2: New.