From patchwork Fri Aug 16 11:19:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13766017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D283CC3DA4A for ; Fri, 16 Aug 2024 11:19:21 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778584.1188631 (Exim 4.92) (envelope-from ) id 1seuzC-0001nv-FW; Fri, 16 Aug 2024 11:19:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778584.1188631; Fri, 16 Aug 2024 11:19:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuzC-0001no-Cn; Fri, 16 Aug 2024 11:19:14 +0000 Received: by outflank-mailman (input) for mailman id 778584; Fri, 16 Aug 2024 11:19:13 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuzB-0001mN-3h for xen-devel@lists.xenproject.org; Fri, 16 Aug 2024 11:19:13 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 5c64582a-5bc1-11ef-a505-bb4a2ccca743; Fri, 16 Aug 2024 13:19:11 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 8C5B82B8AD; Fri, 16 Aug 2024 07:19:10 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 830592B8AC; Fri, 16 Aug 2024 07:19:10 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id 912E72B8AB; Fri, 16 Aug 2024 07:19:09 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5c64582a-5bc1-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=PjnMO2z53AIZ819k6PFRrFgWX 6KC8ZTHVSlS1GFYRHg=; b=RJz3lELjHQkcdAJIiw2+DyP48jnGSsN1JYu3eQHWc jtU59lDyc4nd30jCzlyT8o6C/gaDivwYg3gGIPjKH7Jl4EXigYR9aB8MVrLNZeru 9RC6cNsNRIRQWU38oFmQM09dQ9eyiLCF63HfhlnHNs0AfX+PRu+oOyt32eXLluIA aM= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Jan Beulich Subject: [XEN PATCH v2 5/5] x86/amd: optional build of amd.c Date: Fri, 16 Aug 2024 14:19:07 +0300 Message-Id: <3c641433fa7cfe1f7fdc918ab32086835a2e13eb.1723806405.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 5BA4DA1C-5BC1-11EF-AEDC-9B0F950A682E-90055647!pb-smtp2.pobox.com Similar to making Intel CPU support optional -- as we've got CONFIG_AMD option now, we can put arch/x86/cpu/amd.c under it and make it possible to build Xen without AMD CPU support. One possible use case is to dispose of dead code in Intel-only systems. Signed-off-by: Sergiy Kibrik CC: Jan Beulich --- changes in v2: - drop routines-stubs in amd.h, handle call sites instead - cpu_has_amd_erratum() return int instead of bool --- xen/arch/x86/cpu/Makefile | 2 +- xen/arch/x86/cpu/common.c | 4 +++- xen/arch/x86/hvm/svm/svm.c | 6 ++++-- xen/arch/x86/include/asm/amd.h | 20 ++++++++++++++++++-- xen/arch/x86/spec_ctrl.c | 2 ++ 5 files changed, 28 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index eeb9ebe562..2c34597136 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -2,7 +2,7 @@ obj-y += mcheck/ obj-y += microcode/ obj-y += mtrr/ -obj-y += amd.o +obj-$(CONFIG_AMD) += amd.o obj-$(CONFIG_CENTAUR) += centaur.o obj-y += common.o obj-$(CONFIG_HYGON) += hygon.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 580b01d6d5..5930b712bf 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -194,7 +194,7 @@ void ctxt_switch_levelling(const struct vcpu *next) if (cpu_has_cpuid_faulting) set_cpuid_faulting(enable_cpuid_faulting); - else + else if ( IS_ENABLED(CONFIG_AMD) ) amd_set_cpuid_user_dis(enable_cpuid_faulting); return; @@ -340,7 +340,9 @@ void __init early_cpu_init(bool verbose) case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu = intel_cpu_dev; break; #endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: actual_cpu = amd_cpu_dev; break; +#endif #ifdef CONFIG_CENTAUR case X86_VENDOR_CENTAUR: actual_cpu = centaur_cpu_dev; break; #endif diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 92bb10c504..88902e2d3a 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -919,7 +919,8 @@ static void cf_check svm_ctxt_switch_from(struct vcpu *v) * Possibly clear previous guest selection of SSBD if set. Note that * SPEC_CTRL.SSBD is already handled by svm_vmexit_spec_ctrl. */ - if ( v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) + if ( IS_ENABLED(CONFIG_AMD) && + v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) { ASSERT(v->domain->arch.cpuid->extd.virt_ssbd); amd_set_legacy_ssbd(false); @@ -953,7 +954,8 @@ static void cf_check svm_ctxt_switch_to(struct vcpu *v) wrmsr_tsc_aux(v->arch.msrs->tsc_aux); /* Load SSBD if set by the guest. */ - if ( v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) + if ( IS_ENABLED(CONFIG_AMD) && + v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) { ASSERT(v->domain->arch.cpuid->extd.virt_ssbd); amd_set_legacy_ssbd(true); diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index fa4e0fc766..da35b82d5a 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -158,20 +158,36 @@ #define is_zen4_uarch() boot_cpu_has(X86_FEATURE_AUTO_IBRS) struct cpuinfo_x86; +#ifdef CONFIG_AMD int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...); +#else +static inline int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, + int osvw_id, ...) +{ + return 0; +} +#endif extern s8 opt_allow_unsafe; void fam10h_check_enable_mmcfg(void); void check_enable_amd_mmconf_dmi(void); -extern bool amd_acpi_c1e_quirk; void amd_check_disable_c1e(unsigned int port, u8 value); extern bool amd_legacy_ssbd; -extern bool amd_virt_spec_ctrl; bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); void amd_set_cpuid_user_dis(bool enable); +#ifdef CONFIG_AMD +extern bool amd_acpi_c1e_quirk; +extern bool amd_virt_spec_ctrl; +#else + +#define amd_acpi_c1e_quirk (false) +#define amd_virt_spec_ctrl (false) + +#endif + #endif /* __AMD_H__ */ diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index ba6c3e80d2..1964a417de 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -1893,10 +1893,12 @@ void __init init_speculation_mitigations(void) setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM); } +#ifdef CONFIG_AMD /* Support VIRT_SPEC_CTRL.SSBD if AMD_SSBD is not available. */ if ( opt_msr_sc_hvm && !cpu_has_amd_ssbd && (cpu_has_virt_ssbd || (amd_legacy_ssbd && amd_setup_legacy_ssbd())) ) amd_virt_spec_ctrl = true; +#endif /* Figure out default_xen_spec_ctrl. */ if ( has_spec_ctrl && ibrs )