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[v3,12/14] x86/traps: Add Hygon Dhyana support

Message ID 48dc73b7ece7e33785b118eb1b0853eda0ff5b31.1553520193.git.puwen@hygon.cn (mailing list archive)
State Superseded
Headers show
Series Add support for Hygon Dhyana Family 18h processor | expand

Commit Message

Pu Wen March 25, 2019, 1:31 p.m. UTC
The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR0000_01DD. So add support for it if the boot param
ler is true.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
 xen/arch/x86/traps.c | 3 +++
 1 file changed, 3 insertions(+)
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diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 05ddc39..97bf9e2 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,9 @@  static unsigned int calc_ler_msr(void)
             return MSR_IA32_LASTINTFROMIP;
+    case X86_VENDOR_HYGON:
+        return MSR_IA32_LASTINTFROMIP;
     return 0;