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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-535408410f5sm1677618e87.211.2024.09.02.10.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 10:01:26 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fedaced3-694c-11ef-a0b2-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725296488; x=1725901288; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zsZPmdsnUQ0g8GNjVOugZDCtnwfYe0WoeUsADZLx6iU=; b=OEr7tjSrD3lJFEzyhX3FdUMxsmJR1YyMxpAPETreJmVWCXExOoJT668qHkwtN6wsk4 zHMfxQavvy0ZJW/NhgAMf4HEaQu26v5fDZIYofS76jNOZrb5G2t0EB+ZY0Wj6SkoFjxQ Ogjmq/SEjOXPuZBnzicFxZ98ljhv6qCrDElmH2f/TJn0cLXS6/2qNI5UZLaKdhBLjmLl 3fTXP6B6KlrUGyVH9SpCg/GMdrBWh2lYjBr98MngnT77CppWleIn2XqLpMZiER+acqHD ojKN8ddCdVSYpVuBC9+DHZsswZxa6hSJnKZC86FQzzcXLwwjAl0LNQuAKssC+QK8KnLI QpvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725296488; x=1725901288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zsZPmdsnUQ0g8GNjVOugZDCtnwfYe0WoeUsADZLx6iU=; b=Wb+cfr4CGTQ1YY8ddkaTOu5yDZ8DCSIt6lmiM9x8ralO9uCgGbF1P/b1FdGCKec8nJ +BK/8D2wqHzg/lbl66jwuao9vICq77FniBeByTLdL3DCwbKrcJWzxhOM+R/pjb2xJjd/ 12+6GyyC+GUWgjYTkUhRq5zY2mEpcxGG5rWTizvOydoBCEdf4uv4qAHOROcPMtCYghsZ bA27LqjyMYnyY/tSngzpJcQupPf92+o7DH6d/taL4xrydq2s7CsWB5Jfp3M6/LKse7pm gbnXtyhpd59hdqXjVIqgDnNmLKu4KANahORHI7ijSo5JedbHXii+GeaDcc3Y4rEuPZBW hPzA== X-Gm-Message-State: AOJu0YzchBB0TWr4BCRKjfqTD/zO/sd4vQkDnfYp5LC2wRNVuN6OKdQ8 c2SRKfLqHOxaiLKQFZsXVqBZHJXtcEQ7Ui23Q1UNkOgzCbXvcS0h3EdTyw== X-Google-Smtp-Source: AGHT+IEWGK9oB56pwCiBkBH6KNLMot3k+AocE1a8BqzB1tmMKLmsUFkhDRO1K+eGIN2tjn4oFkGwAw== X-Received: by 2002:a05:6512:3b8c:b0:52f:159:2dc5 with SMTP id 2adb3069b0e04-53546ba9fd4mr7564023e87.42.1725296487042; Mon, 02 Sep 2024 10:01:27 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v6 2/9] xen/riscv: use {read,write}{b,w,l,q}_cpu() to define {read,write}_atomic() Date: Mon, 2 Sep 2024 19:01:15 +0200 Message-ID: <4b62d7e3faa24f6070430607262a3aed1bbf1861.1725295716.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 The functions {read,write}{b,w,l,q}_cpu() do not need to be memory-ordered atomic operations in Xen, based on their definitions for other architectures. Therefore, {read,write}{b,w,l,q}_cpu() can be used instead of {read,write}{b,w,l,q}(), allowing the caller to decide if additional fences should be applied before or after {read,write}_atomic(). Signed-off-by: Oleksii Kurochko --- Changes in V6: - revert changes connected to _write_atomic() prototype and in definition of write_atomic(). - update the commit message. --- Changes in v5: - new patch. --- xen/arch/riscv/include/asm/atomic.h | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h index 31b91a79c8..3c6bd86406 100644 --- a/xen/arch/riscv/include/asm/atomic.h +++ b/xen/arch/riscv/include/asm/atomic.h @@ -31,21 +31,17 @@ void __bad_atomic_size(void); -/* - * Legacy from Linux kernel. For some reason they wanted to have ordered - * read/write access. Thereby read* is used instead of read*_cpu() - */ static always_inline void read_atomic_size(const volatile void *p, void *res, unsigned int size) { switch ( size ) { - case 1: *(uint8_t *)res = readb(p); break; - case 2: *(uint16_t *)res = readw(p); break; - case 4: *(uint32_t *)res = readl(p); break; + case 1: *(uint8_t *)res = readb_cpu(p); break; + case 2: *(uint16_t *)res = readw_cpu(p); break; + case 4: *(uint32_t *)res = readl_cpu(p); break; #ifndef CONFIG_RISCV_32 - case 8: *(uint32_t *)res = readq(p); break; + case 8: *(uint32_t *)res = readq_cpu(p); break; #endif default: __bad_atomic_size(); break; } @@ -58,15 +54,16 @@ static always_inline void read_atomic_size(const volatile void *p, }) static always_inline void _write_atomic(volatile void *p, - unsigned long x, unsigned int size) + unsigned long x, + unsigned int size) { switch ( size ) { - case 1: writeb(x, p); break; - case 2: writew(x, p); break; - case 4: writel(x, p); break; + case 1: writeb_cpu(x, p); break; + case 2: writew_cpu(x, p); break; + case 4: writel_cpu(x, p); break; #ifndef CONFIG_RISCV_32 - case 8: writeq(x, p); break; + case 8: writeq_cpu(x, p); break; #endif default: __bad_atomic_size(); break; }