From patchwork Wed Dec 20 11:03:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Federico Serafini X-Patchwork-Id: 13499980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5ABA7C3DA6E for ; Wed, 20 Dec 2023 11:03:37 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.657636.1026662 (Exim 4.92) (envelope-from ) id 1rFuMI-0006DE-63; Wed, 20 Dec 2023 11:03:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 657636.1026662; Wed, 20 Dec 2023 11:03:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rFuMI-0006D3-1a; Wed, 20 Dec 2023 11:03:26 +0000 Received: by outflank-mailman (input) for mailman id 657636; Wed, 20 Dec 2023 11:03:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rFuMG-0004rG-2S for xen-devel@lists.xenproject.org; Wed, 20 Dec 2023 11:03:24 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 647b579b-9f27-11ee-98eb-6d05b1d4d9a1; Wed, 20 Dec 2023 12:03:23 +0100 (CET) Received: from Dell.bugseng.com (unknown [37.161.218.228]) by support.bugseng.com (Postfix) with ESMTPSA id 75AB84EE0C92; Wed, 20 Dec 2023 12:03:22 +0100 (CET) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 647b579b-9f27-11ee-98eb-6d05b1d4d9a1 From: Federico Serafini To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Federico Serafini , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [XEN PATCH 5/7] xen/arm: v{cp,sys}reg: address violations of MISRA C:2012 Rule 16.3 Date: Wed, 20 Dec 2023 12:03:05 +0100 Message-Id: <541bc4fd47d26b12ea131590bf0c49f7c92d9368.1703066935.git.federico.serafini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Refactor of the switch-clauses to have a return statement at the end. This satisfies the requirements to deviate Rule 16.3 ("An unconditional `break' statement shall terminate every switch-clause). No functional change. Signed-off-by: Federico Serafini Acked-by: Julien Grall --- xen/arch/arm/arm64/vsysreg.c | 4 ++-- xen/arch/arm/vcpreg.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index b5d54c569b..247f08ad8d 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -210,8 +210,8 @@ void do_sysreg(struct cpu_user_regs *regs, /* RO at EL0. RAZ/WI at EL1 */ if ( regs_mode_is_user(regs) ) return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); case HSR_SYSREG_PMCR_EL0: case HSR_SYSREG_PMCNTENSET_EL0: case HSR_SYSREG_PMCNTENCLR_EL0: diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index a2d0500704..685609f825 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -289,8 +289,8 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) /* RO at EL0. RAZ/WI at EL1 */ if ( regs_mode_is_user(regs) ) return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); case HSR_CPREG32(PMINTENSET): case HSR_CPREG32(PMINTENCLR): /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */