From patchwork Fri Dec 20 13:39:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 11305449 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8AF3109A for ; Fri, 20 Dec 2019 13:39:44 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEF71206A5 for ; Fri, 20 Dec 2019 13:39:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CEF71206A5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iiIUR-00076O-B4; Fri, 20 Dec 2019 13:38:47 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iiIUQ-00076G-38 for xen-devel@lists.xenproject.org; Fri, 20 Dec 2019 13:38:46 +0000 X-Inumbo-ID: 0acf162a-232e-11ea-935a-12813bfff9fa Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 0acf162a-232e-11ea-935a-12813bfff9fa; Fri, 20 Dec 2019 13:38:45 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 7E090AFA8; Fri, 20 Dec 2019 13:38:44 +0000 (UTC) From: Jan Beulich To: "xen-devel@lists.xenproject.org" References: <7f7a6ba3-7308-b079-2df1-f5b8501b3cc6@suse.com> Message-ID: <5493d679-3183-25e9-6f3e-6320779420bb@suse.com> Date: Fri, 20 Dec 2019 14:39:13 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <7f7a6ba3-7308-b079-2df1-f5b8501b3cc6@suse.com> Content-Language: en-US Subject: [Xen-devel] [PATCH 1/5] x86emul: use CASE_SIMD_PACKED_INT() where possible X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This (imo) improves readability (simply by the shrunk number of lines) and helps prepare for optionally disabling MMX and SIMD support in the emulator. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -8528,36 +8528,21 @@ x86_emulate( sfence = true; break; - case X86EMUL_OPC(0x0f38, 0x00): /* pshufb mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x00): /* pshufb xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x01): /* phaddw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x01): /* phaddw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x02): /* phaddd mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x02): /* phaddd xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x03): /* phaddsw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x03): /* phaddsw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x04): /* pmaddubsw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x04): /* pmaddubsw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x05): /* phsubw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x05): /* phsubw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x06): /* phsubd mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x06): /* phsubd xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x07): /* phsubsw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x07): /* phsubsw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x08): /* psignb mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x08): /* psignb xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x09): /* psignw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x09): /* psignw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x0a): /* psignd mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x0a): /* psignd xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x0b): /* pmulhrsw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x0b): /* pmulhrsw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x1c): /* pabsb mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x1c): /* pabsb xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x1d): /* pabsw mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x1d): /* pabsw xmm/m128,xmm */ - case X86EMUL_OPC(0x0f38, 0x1e): /* pabsd mm/m64,mm */ - case X86EMUL_OPC_66(0x0f38, 0x1e): /* pabsd xmm/m128,xmm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x00): /* pshufb {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x01): /* phaddw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x02): /* phaddd {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x03): /* phaddsw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x04): /* pmaddubsw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x05): /* phsubw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x06): /* phsubd {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x07): /* phsubsw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x08): /* psignb {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x09): /* psignw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x0a): /* psignd {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x0b): /* pmulhrsw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x1c): /* pabsb {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x1d): /* pabsw {,x}mm/mem,{,x}mm */ + CASE_SIMD_PACKED_INT(0x0f38, 0x1e): /* pabsd {,x}mm/mem,{,x}mm */ host_and_vcpu_must_have(ssse3); if ( vex.pfx ) { @@ -9982,8 +9967,7 @@ x86_emulate( avx512_vlen_check(b & 2); goto simd_imm8_zmm; - case X86EMUL_OPC(0x0f3a, 0x0f): /* palignr $imm8,mm/m64,mm */ - case X86EMUL_OPC_66(0x0f3a, 0x0f): /* palignr $imm8,xmm/m128,xmm */ + CASE_SIMD_PACKED_INT(0x0f3a, 0x0f): /* palignr $imm8,{,x}mm/mem,{,x}mm */ host_and_vcpu_must_have(ssse3); if ( vex.pfx ) {