From patchwork Wed Jan 27 13:12:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8133441 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A32F49F440 for ; Wed, 27 Jan 2016 13:15:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D56920270 for ; Wed, 27 Jan 2016 13:15:52 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 59B4F20251 for ; Wed, 27 Jan 2016 13:15:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aOPtk-0001bx-4Y; Wed, 27 Jan 2016 13:12:36 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aOPti-0001bs-LW for xen-devel@lists.xen.org; Wed, 27 Jan 2016 13:12:34 +0000 Received: from [85.158.143.35] by server-2.bemta-4.messagelabs.com id 95/CF-08977-142C8A65; Wed, 27 Jan 2016 13:12:33 +0000 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1453900336!8032498!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 29338 invoked from network); 27 Jan 2016 13:12:27 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-16.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 27 Jan 2016 13:12:27 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 27 Jan 2016 06:12:15 -0700 Message-Id: <56A8D03E02000078000CB8B8@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Wed, 27 Jan 2016 06:12:14 -0700 From: "Jan Beulich" To: "Harmandeep Kaur" References: <569D2A49.1090409@citrix.com> <1453141749.11427.92.camel@citrix.com> <569E4A0102000078000C8917@prv-mh.provo.novell.com> <1453215095.11427.144.camel@citrix.com> <569E5118.4030704@citrix.com> <569E76B102000078000C8C14@prv-mh.provo.novell.com> <569E6C36.3070402@citrix.com> <1453223282.11427.149.camel@citrix.com> <569F6A2102000078000C8F20@prv-mh.provo.novell.com> <1453389242.3116.106.camel@citrix.com> <56A6344C02000078000CAA56@prv-mh.provo.novell.com> <56A7815502000078000CB147@prv-mh.provo.novell.com> <56A7B98C02000078000CB3B8@prv-mh.provo.novell.com> In-Reply-To: Mime-Version: 1.0 Cc: Andrew Cooper , Dario Faggioli , xen-devel@lists.xen.org, Shuai Ruan Subject: Re: [Xen-devel] Error booting Xen X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP >>> On 26.01.16 at 19:02, wrote: > Last time, I did absolutely nothing. System was idle > and it crashed just after the login. Now, I booted the > system again and this time, there is no reset. But, > performance of the system is very slow. Browser > (Mozilla Firefox) freezes a lot. Also, before applying > patches, when I used to disabe xsave it resulted in > same kind of performance issues. And the following > is still present in the log. > > (XEN) traps.c:3290: GPF (0000): ffff82d0801c1cea -> ffff82d080252e5c > (XEN) d1v1 fault#1: mxcsr=00001f80 > (XEN) d1v1 xs=0000000000000003 xc=8000000000000000 > (XEN) d1v1 r0=0000000000000000 r1=0000000000000000 > (XEN) d1v1 r2=0000000000000000 r3=0000000000000000 > (XEN) d1v1 r4=0000000000000000 r5=0000000000000000 > (XEN) traps.c:3290: GPF (0000): ffff82d0801c1cea -> ffff82d080252e5c > (XEN) d1v1 fault#2: mxcsr=00001f80 > (XEN) d1v1 xs=0000000000000000 xc=0000000000000000 > (XEN) d1v1 r0=0000000000000000 r1=0000000000000000 > (XEN) d1v1 r2=0000000000000000 r3=0000000000000000 > (XEN) d1v1 r4=0000000000000000 r5=0000000000000000 > > Full log here: http://paste2.org/C8WpyKOg This together with ... > On Tue, Jan 26, 2016 at 10:53 PM, Jan Beulich wrote: >>>>> On 26.01.16 at 18:01, wrote: >>> I tried 3rd patch together with earlier two. I'm >>> afraid the problem is not solved completely. >>> Full log goes here, http://paste2.org/KEAetMHb ... this, and both being apparently the same build makes me suspect uninitialized data to get passed in from the tool stack. But that's a secondary issue for now. For the immediate problem here are four patches replacing the three earlier ones (I think only one of them is unchanged, so be sure to remove the old ones first). Their intended ordering is: x86-xsaves-init.patch x86-xstate-align.patch x86-xrstors-fault.patch x86-xstate-validate.patch Jan x86/xstate: fix fault behavior on XRSTORS XRSTORS unconditionally faults when xcomp_bv has bit 63 clear. Instead of just fixing this issue, overhaul the fault recovery code, which - one of the many mistakes made when xstate support got introduced - was blindly mirroring that accompanying FXRSTOR, neglecting the fact that XRSTOR{,S} aren't all-or-nothing instructions. The new code, first of all, does all the recovery actions in C, simplifying the inline assembly used. And it does its work in a multi-stage fashion: Upon first seeing a fault, state fixups get applied strictly based on what architecturally may cause #GP. When seeing another fault despite the fixups done, state gets fully reset. A third fault would then lead to crashing the domain (instead of hanging the hypervisor in an infinite loop of recurring faults). Reported-by: Harmandeep Kaur Signed-off-by: Jan Beulich x86/xstate: fix xcomp_bv initialization We must not clear the compaction bit when using XSAVES/XRSTORS. And we need to guarantee that xcomp_bv never has any bits clear which are set in xstate_bv (which requires partly undoing commit 83ae0bb226 ["x86/xsave: simplify xcomp_bv initialization"]). Split initialization of xcomp_bv from the other FPU/SSE/AVX related state setup in arch_set_info_guest() and hvm_load_cpu_ctxt(). Reported-by: Harmandeep Kaur Signed-off-by: Jan Beulich --- unstable.orig/xen/arch/x86/domain.c 2016-01-27 09:29:50.000000000 +0100 +++ unstable/xen/arch/x86/domain.c 2016-01-27 09:52:37.000000000 +0100 @@ -922,15 +922,10 @@ int arch_set_info_guest( { memcpy(v->arch.fpu_ctxt, &c.nat->fpu_ctxt, sizeof(c.nat->fpu_ctxt)); if ( v->arch.xsave_area ) - { v->arch.xsave_area->xsave_hdr.xstate_bv = XSTATE_FP_SSE; - v->arch.xsave_area->xsave_hdr.xcomp_bv = - cpu_has_xsaves ? XSTATE_COMPACTION_ENABLED : 0; - } } else if ( v->arch.xsave_area ) - memset(&v->arch.xsave_area->xsave_hdr, 0, - sizeof(v->arch.xsave_area->xsave_hdr)); + v->arch.xsave_area->xsave_hdr.xstate_bv = 0; else { typeof(v->arch.xsave_area->fpu_sse) *fpu_sse = v->arch.fpu_ctxt; @@ -939,6 +934,14 @@ int arch_set_info_guest( fpu_sse->fcw = FCW_DEFAULT; fpu_sse->mxcsr = MXCSR_DEFAULT; } + if ( cpu_has_xsaves ) + { + ASSERT(v->arch.xsave_area); + v->arch.xsave_area->xsave_hdr.xcomp_bv = XSTATE_COMPACTION_ENABLED | + v->arch.xsave_area->xsave_hdr.xstate_bv; + } + else if ( v->arch.xsave_area ) + v->arch.xsave_area->xsave_hdr.xcomp_bv = 0; if ( !compat ) { --- unstable.orig/xen/arch/x86/hvm/hvm.c 2015-12-18 12:22:20.000000000 +0100 +++ unstable/xen/arch/x86/hvm/hvm.c 2016-01-27 09:52:26.000000000 +0100 @@ -2094,11 +2094,17 @@ static int hvm_load_cpu_ctxt(struct doma memcpy(v->arch.xsave_area, ctxt.fpu_regs, sizeof(ctxt.fpu_regs)); xsave_area->xsave_hdr.xstate_bv = XSTATE_FP_SSE; - xsave_area->xsave_hdr.xcomp_bv = - cpu_has_xsaves ? XSTATE_COMPACTION_ENABLED : 0; } else memcpy(v->arch.fpu_ctxt, ctxt.fpu_regs, sizeof(ctxt.fpu_regs)); + if ( cpu_has_xsaves ) + { + ASSERT(v->arch.xsave_area); + v->arch.xsave_area->xsave_hdr.xcomp_bv = XSTATE_COMPACTION_ENABLED | + v->arch.xsave_area->xsave_hdr.xstate_bv; + } + else if ( v->arch.xsave_area ) + v->arch.xsave_area->xsave_hdr.xcomp_bv = 0; v->arch.user_regs.eax = ctxt.rax; v->arch.user_regs.ebx = ctxt.rbx; @@ -5488,8 +5494,8 @@ void hvm_vcpu_reset_state(struct vcpu *v if ( v->arch.xsave_area ) { v->arch.xsave_area->xsave_hdr.xstate_bv = XSTATE_FP; - v->arch.xsave_area->xsave_hdr.xcomp_bv = - cpu_has_xsaves ? XSTATE_COMPACTION_ENABLED : 0; + v->arch.xsave_area->xsave_hdr.xcomp_bv = cpu_has_xsaves + ? XSTATE_COMPACTION_ENABLED | XSTATE_FP : 0; } v->arch.vgc_flags = VGCF_online; x86: adjust xsave structure attributes The packed attribute was pointlessly used here - there are no misaligned fields, and hence even if the attribute took effect, it would at best lead to the compiler generating worse code. At the same time specify the required alignment of the fpu_sse sub- structure, such that the various typeof() uses on that field obtain pointers to properly aligned memory (knowledge which a compiler may want to make use of). Also add suitable build-time checks. Signed-off-by: Jan Beulich --- unstable.orig/xen/arch/x86/i387.c 2016-01-25 11:30:11.000000000 +0100 +++ unstable/xen/arch/x86/i387.c 2016-01-25 09:35:36.000000000 +0100 @@ -277,7 +277,9 @@ int vcpu_init_fpu(struct vcpu *v) } else { - v->arch.fpu_ctxt = _xzalloc(sizeof(v->arch.xsave_area->fpu_sse), 16); + BUILD_BUG_ON(__alignof(v->arch.xsave_area->fpu_sse) < 16); + v->arch.fpu_ctxt = _xzalloc(sizeof(v->arch.xsave_area->fpu_sse), + __alignof(v->arch.xsave_area->fpu_sse)); if ( v->arch.fpu_ctxt ) { typeof(v->arch.xsave_area->fpu_sse) *fpu_sse = v->arch.fpu_ctxt; --- unstable.orig/xen/arch/x86/xstate.c 2016-01-25 11:30:11.000000000 +0100 +++ unstable/xen/arch/x86/xstate.c 2016-01-25 09:35:12.000000000 +0100 @@ -414,7 +414,8 @@ int xstate_alloc_save_area(struct vcpu * BUG_ON(xsave_cntxt_size < XSTATE_AREA_MIN_SIZE); /* XSAVE/XRSTOR requires the save area be 64-byte-boundary aligned. */ - save_area = _xzalloc(xsave_cntxt_size, 64); + BUILD_BUG_ON(__alignof(*save_area) < 64); + save_area = _xzalloc(xsave_cntxt_size, __alignof(*save_area)); if ( save_area == NULL ) return -ENOMEM; --- unstable.orig/xen/include/asm-x86/xstate.h 2016-01-25 11:30:11.000000000 +0100 +++ unstable/xen/include/asm-x86/xstate.h 2016-01-25 11:33:20.000000000 +0100 @@ -48,9 +48,9 @@ extern u64 xfeature_mask; extern unsigned int *xstate_sizes; /* extended state save area */ -struct __packed __attribute__((aligned (64))) xsave_struct +struct __attribute__((aligned (64))) xsave_struct { - union { /* FPU/MMX, SSE */ + union __attribute__((aligned(16))) { /* FPU/MMX, SSE */ char x[512]; struct { uint16_t fcw; x86/xstate: extend validation to cover full header Since we never hand out compacted state, at least for now we're also not going to accept such. Reported-by: Harmandeep Kaur Signed-off-by: Jan Beulich --- unstable.orig/xen/arch/x86/domctl.c 2016-01-27 10:54:16.000000000 +0100 +++ unstable/xen/arch/x86/domctl.c 2016-01-27 10:44:52.000000000 +0100 @@ -958,7 +958,7 @@ long arch_do_domctl( { if ( evc->size >= 2 * sizeof(uint64_t) + XSTATE_AREA_MIN_SIZE ) ret = validate_xstate(_xcr0, _xcr0_accum, - _xsave_area->xsave_hdr.xstate_bv); + &_xsave_area->xsave_hdr); } else if ( !_xcr0 ) ret = 0; --- unstable.orig/xen/arch/x86/hvm/hvm.c 2016-01-27 09:52:26.000000000 +0100 +++ unstable/xen/arch/x86/hvm/hvm.c 2016-01-27 11:09:44.000000000 +0100 @@ -2178,6 +2178,19 @@ static int hvm_save_cpu_xsave_states(str return 0; } +/* + * Structure layout conformity checks, documenting correctness of the cast in + * the invocation of validate_xstate() below. + * Leverage CONFIG_COMPAT machinery to perform this. + */ +#define xen_xsave_hdr xsave_hdr +#define compat_xsave_hdr hvm_hw_cpu_xsave_hdr +CHECK_FIELD_(struct, xsave_hdr, xstate_bv); +CHECK_FIELD_(struct, xsave_hdr, xcomp_bv); +CHECK_FIELD_(struct, xsave_hdr, reserved); +#undef compat_xsave_hdr +#undef xen_xsave_hdr + static int hvm_load_cpu_xsave_states(struct domain *d, hvm_domain_context_t *h) { unsigned int vcpuid, size; @@ -2233,7 +2246,7 @@ static int hvm_load_cpu_xsave_states(str h->cur += desc->length; err = validate_xstate(ctxt->xcr0, ctxt->xcr0_accum, - ctxt->save_area.xsave_hdr.xstate_bv); + (const void *)&ctxt->save_area.xsave_hdr); if ( err ) { printk(XENLOG_G_WARNING --- unstable.orig/xen/arch/x86/xstate.c 2016-01-27 10:23:06.000000000 +0100 +++ unstable/xen/arch/x86/xstate.c 2016-01-27 10:48:22.000000000 +0100 @@ -614,17 +614,24 @@ static bool_t valid_xcr0(u64 xcr0) return !(xcr0 & XSTATE_BNDREGS) == !(xcr0 & XSTATE_BNDCSR); } -int validate_xstate(u64 xcr0, u64 xcr0_accum, u64 xstate_bv) +int validate_xstate(u64 xcr0, u64 xcr0_accum, const struct xsave_hdr *hdr) { - if ( (xstate_bv & ~xcr0_accum) || + unsigned int i; + + if ( (hdr->xstate_bv & ~xcr0_accum) || (xcr0 & ~xcr0_accum) || !valid_xcr0(xcr0) || !valid_xcr0(xcr0_accum) ) return -EINVAL; - if ( xcr0_accum & ~xfeature_mask ) + if ( (xcr0_accum & ~xfeature_mask) || + hdr->xcomp_bv ) return -EOPNOTSUPP; + for ( i = 0; i < ARRAY_SIZE(hdr->reserved); ++i ) + if ( hdr->reserved[i] ) + return -EIO; + return 0; } --- unstable.orig/xen/include/asm-x86/xstate.h 2016-01-25 11:33:20.000000000 +0100 +++ unstable/xen/include/asm-x86/xstate.h 2016-01-27 10:57:54.000000000 +0100 @@ -72,14 +72,13 @@ struct __attribute__((aligned (64))) xsa }; } fpu_sse; - struct { + struct xsave_hdr { u64 xstate_bv; u64 xcomp_bv; u64 reserved[6]; } xsave_hdr; /* The 64-byte header */ - struct { char x[XSTATE_YMM_SIZE]; } ymm; /* YMM */ - char data[]; /* Future new states */ + char data[]; /* Variable layout states */ }; /* extended state operations */ @@ -90,7 +89,8 @@ uint64_t get_msr_xss(void); void xsave(struct vcpu *v, uint64_t mask); void xrstor(struct vcpu *v, uint64_t mask); bool_t xsave_enabled(const struct vcpu *v); -int __must_check validate_xstate(u64 xcr0, u64 xcr0_accum, u64 xstate_bv); +int __must_check validate_xstate(u64 xcr0, u64 xcr0_accum, + const struct xsave_hdr *); int __must_check handle_xsetbv(u32 index, u64 new_bv); void expand_xsave_states(struct vcpu *v, void *dest, unsigned int size); void compress_xsave_states(struct vcpu *v, const void *src, unsigned int size); --- unstable.orig/xen/include/public/arch-x86/hvm/save.h 2016-01-13 07:56:27.000000000 +0100 +++ unstable/xen/include/public/arch-x86/hvm/save.h 2016-01-27 11:09:20.000000000 +0100 @@ -550,12 +550,11 @@ struct hvm_hw_cpu_xsave { struct { struct { char x[512]; } fpu_sse; - struct { + struct hvm_hw_cpu_xsave_hdr { uint64_t xstate_bv; /* Updated by XRSTOR */ - uint64_t reserved[7]; + uint64_t xcomp_bv; /* Updated by XRSTOR{C,S} */ + uint64_t reserved[6]; } xsave_hdr; /* The 64-byte header */ - - struct { char x[0]; } ymm; /* YMM */ } save_area; }; --- unstable.orig/xen/arch/x86/xstate.c 2016-01-25 09:35:12.000000000 +0100 +++ unstable/xen/arch/x86/xstate.c 2016-01-27 10:23:06.000000000 +0100 @@ -29,6 +29,8 @@ unsigned int *__read_mostly xstate_sizes static unsigned int __read_mostly xstate_features; static unsigned int __read_mostly xstate_comp_offsets[sizeof(xfeature_mask)*8]; +static uint32_t __read_mostly mxcsr_mask = MXCSR_DEFAULT; + /* Cached xcr0 for fast read */ static DEFINE_PER_CPU(uint64_t, xcr0); @@ -342,6 +344,7 @@ void xrstor(struct vcpu *v, uint64_t mas uint32_t hmask = mask >> 32; uint32_t lmask = mask; struct xsave_struct *ptr = v->arch.xsave_area; + unsigned int faults, prev_faults; /* * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception @@ -361,35 +364,85 @@ void xrstor(struct vcpu *v, uint64_t mas /* * XRSTOR can fault if passed a corrupted data block. We handle this * possibility, which may occur if the block was passed to us by control - * tools or through VCPUOP_initialise, by silently clearing the block. + * tools or through VCPUOP_initialise, by silently adjusting state. */ - switch ( __builtin_expect(ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET], 8) ) + for ( prev_faults = faults = 0; ; prev_faults = faults ) { + switch ( __builtin_expect(ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET], 8) ) + { #define XRSTOR(pfx) \ alternative_io("1: .byte " pfx "0x0f,0xae,0x2f\n" \ + "3:\n" \ " .section .fixup,\"ax\"\n" \ - "2: mov %[size],%%ecx\n" \ - " xor %[lmask_out],%[lmask_out]\n" \ - " rep stosb\n" \ - " lea %[mem],%[ptr]\n" \ - " mov %[lmask_in],%[lmask_out]\n" \ - " jmp 1b\n" \ + "2: inc%z[faults] %[faults]\n" \ + " jmp 3b\n" \ " .previous\n" \ _ASM_EXTABLE(1b, 2b), \ ".byte " pfx "0x0f,0xc7,0x1f\n", \ X86_FEATURE_XSAVES, \ - ASM_OUTPUT2([ptr] "+&D" (ptr), [lmask_out] "+&a" (lmask)), \ - [mem] "m" (*ptr), [lmask_in] "g" (lmask), \ - [hmask] "d" (hmask), [size] "m" (xsave_cntxt_size) \ - : "ecx") - - default: - XRSTOR("0x48,"); - break; - case 4: case 2: - XRSTOR(""); - break; + ASM_OUTPUT2([mem] "+m" (*ptr), [faults] "+g" (faults)), \ + [lmask] "a" (lmask), [hmask] "d" (hmask), \ + [ptr] "D" (ptr)) + + default: + XRSTOR("0x48,"); + break; + case 4: case 2: + XRSTOR(""); + break; #undef XRSTOR + } + if ( likely(faults == prev_faults) ) + break; +#ifndef NDEBUG + gprintk(XENLOG_WARNING, "fault#%u: mxcsr=%08x\n", + faults, ptr->fpu_sse.mxcsr); + gprintk(XENLOG_WARNING, "xs=%016lx xc=%016lx\n", + ptr->xsave_hdr.xstate_bv, ptr->xsave_hdr.xcomp_bv); + gprintk(XENLOG_WARNING, "r0=%016lx r1=%016lx\n", + ptr->xsave_hdr.reserved[0], ptr->xsave_hdr.reserved[1]); + gprintk(XENLOG_WARNING, "r2=%016lx r3=%016lx\n", + ptr->xsave_hdr.reserved[2], ptr->xsave_hdr.reserved[3]); + gprintk(XENLOG_WARNING, "r4=%016lx r5=%016lx\n", + ptr->xsave_hdr.reserved[4], ptr->xsave_hdr.reserved[5]); +#endif + switch ( faults ) + { + case 1: + /* Stage 1: Reset state to be loaded. */ + ptr->xsave_hdr.xstate_bv &= ~mask; + /* + * Also try to eliminate fault reasons, even if this shouldn't be + * needed here (other code should ensure the sanity of the data). + */ + if ( ((mask & XSTATE_SSE) || + ((mask & XSTATE_YMM) && + !(ptr->xsave_hdr.xcomp_bv & XSTATE_COMPACTION_ENABLED))) ) + ptr->fpu_sse.mxcsr &= mxcsr_mask; + if ( cpu_has_xsaves || cpu_has_xsavec ) + { + ptr->xsave_hdr.xcomp_bv &= this_cpu(xcr0) | this_cpu(xss); + ptr->xsave_hdr.xstate_bv &= ptr->xsave_hdr.xcomp_bv; + ptr->xsave_hdr.xcomp_bv |= XSTATE_COMPACTION_ENABLED; + } + else + { + ptr->xsave_hdr.xstate_bv &= this_cpu(xcr0); + ptr->xsave_hdr.xcomp_bv = 0; + } + memset(ptr->xsave_hdr.reserved, 0, sizeof(ptr->xsave_hdr.reserved)); + continue; + case 2: + /* Stage 2: Reset all state. */ + ptr->fpu_sse.mxcsr = MXCSR_DEFAULT; + ptr->xsave_hdr.xstate_bv = 0; + ptr->xsave_hdr.xcomp_bv = cpu_has_xsaves + ? XSTATE_COMPACTION_ENABLED : 0; + continue; + default: + domain_crash(current->domain); + break; + } } } @@ -496,6 +549,8 @@ void xstate_init(struct cpuinfo_x86 *c) if ( bsp ) { + static typeof(current->arch.xsave_area->fpu_sse) __initdata ctxt; + xfeature_mask = feature_mask; /* * xsave_cntxt_size is the max size required by enabled features. @@ -504,6 +559,10 @@ void xstate_init(struct cpuinfo_x86 *c) xsave_cntxt_size = _xstate_ctxt_size(feature_mask); printk("%s: using cntxt_size: %#x and states: %#"PRIx64"\n", __func__, xsave_cntxt_size, xfeature_mask); + + asm ( "fxsave %0" : "=m" (ctxt) ); + if ( ctxt.mxcsr_mask ) + mxcsr_mask = ctxt.mxcsr_mask; } else {