From patchwork Thu Apr 21 15:45:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 8902291 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 980D79F457 for ; Thu, 21 Apr 2016 15:47:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AFD78202DD for ; Thu, 21 Apr 2016 15:47:39 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D1DDB20225 for ; Thu, 21 Apr 2016 15:47:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1atGnK-0004aN-Uz; Thu, 21 Apr 2016 15:45:30 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1atGnJ-0004aG-5g for xen-devel@lists.xenproject.org; Thu, 21 Apr 2016 15:45:29 +0000 Received: from [193.109.254.147] by server-12.bemta-14.messagelabs.com id D2/AB-13115-895F8175; Thu, 21 Apr 2016 15:45:28 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRWlGSWpSXmKPExsXS6fjDS3f6V4l wg/bnihbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8aJNxoFu6UrDjV/YGlgvC7SxcjJISSQJzHh RDsbiM0rYCdxuOM+K4gtIWAosW/+KrA4i4CqROe1tYwgNpuAukTbs+1ANRwcIgIGEueOJoGEm YHG/N88gx3EFhYIlOj7/YERpIRXQFDi7w5hiBI7iX3TnjNNYOSahZCZhSQDYWtJPPx1iwXC1p ZYtvA1M0g5s4C0xPJ/HBBhW4nbH/4wYSrxkJg2LXMBI8cqRvXi1KKy1CJdE72kosz0jJLcxMw cXUNDE73c1OLixPTUnMSkYr3k/NxNjMCwYwCCHYwrFjofYpTkYFIS5V3yTiJciC8pP6UyI7E4 I76oNCe1+BCjDAeHkgRv7RegnGBRanpqRVpmDjACYNISHDxKIryzQdK8xQWJucWZ6RCpU4yKU uK8xSAJAZBERmkeXBss6i4xykoJ8zICHSLEU5BalJtZgir/ilGcg1FJmHcSyBSezLwSuOmvgB YzAS3mvysKsrgkESEl1cAoG83j/W+m/Z0phQ9Fz1zuu//s6W45dps7vEJbDr+xPuL+XNnus7K y023VA7WcK2OZT79S1n98eN1Z1ivRVel/lK68m6ag+vMPp1x08BoPO5ngmccFLbPdclsfiGgf Z5uRYjWzIZD9tapZcfcZ7T/tBarbW/a+Fyg0khLnmL9y5qHA4/tNp3sqsRRnJBpqMRcVJwIAp kpEZLUCAAA= X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-10.tower-27.messagelabs.com!1461253524!37031222!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.28; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48901 invoked from network); 21 Apr 2016 15:45:27 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-10.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 21 Apr 2016 15:45:27 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Thu, 21 Apr 2016 09:45:20 -0600 Message-Id: <571911AD02000078000E46C9@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Thu, 21 Apr 2016 09:45:17 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper , Keir Fraser , Wei Liu Subject: [Xen-devel] [PATCH] x86/MSI: handle both MSI-X and MSI in cfg space write intercept X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests") I neglected to consider devices allowing for both MSI and MSI-X to be used (not at the same time of course): The MSI-X part of the intercept logic needs to fall through to the MSI one when the access is outside the MSI-X capability bounds. Signed-off-by: Jan Beulich x86/MSI: handle both MSI-X and MSI in cfg space write intercept In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests") I neglected to consider devices allowing for both MSI and MSI-X to be used (not at the same time of course): The MSI-X part of the intercept logic needs to fall through to the MSI one when the access is outside the MSI-X capability bounds. Signed-off-by: Jan Beulich --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct PCI_CAP_ID_MSIX); ASSERT(pos); - if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 ) - return 0; + if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 ) + { + if ( reg != msix_control_reg(pos) || size != 2 ) + return -EACCES; - if ( reg != msix_control_reg(pos) || size != 2 ) - return -EACCES; + pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL); + if ( pdev->msix->host_maskall ) + *data |= PCI_MSIX_FLAGS_MASKALL; - pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL); - if ( pdev->msix->host_maskall ) - *data |= PCI_MSIX_FLAGS_MASKALL; - - return 1; + return 1; + } } entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI); Reviewed-by: Andrew Cooper --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct PCI_CAP_ID_MSIX); ASSERT(pos); - if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 ) - return 0; + if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 ) + { + if ( reg != msix_control_reg(pos) || size != 2 ) + return -EACCES; - if ( reg != msix_control_reg(pos) || size != 2 ) - return -EACCES; + pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL); + if ( pdev->msix->host_maskall ) + *data |= PCI_MSIX_FLAGS_MASKALL; - pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL); - if ( pdev->msix->host_maskall ) - *data |= PCI_MSIX_FLAGS_MASKALL; - - return 1; + return 1; + } } entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI);