From patchwork Wed Jun 8 13:12:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9164597 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4EE4360572 for ; Wed, 8 Jun 2016 13:14:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4024B26B4A for ; Wed, 8 Jun 2016 13:14:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34FB42823D; Wed, 8 Jun 2016 13:14:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 64DCA26B4A for ; Wed, 8 Jun 2016 13:14:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAdHW-0002Gz-A7; Wed, 08 Jun 2016 13:12:26 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAdHU-0002Gl-Q8 for xen-devel@lists.xenproject.org; Wed, 08 Jun 2016 13:12:24 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id A8/FE-17117-7B918575; Wed, 08 Jun 2016 13:12:23 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMIsWRWlGSWpSXmKPExsXS6fjDS3e7ZES 4wZxT/Bbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8afabvYCyY6V5xqv87cwLjarIuRk0NIIE/i 2OKdzF2MHBy8AnYS2ybHgYQlBAwl9s1fxQZiswioSlz9/oMRxGYTUJdoe7adFaRcRMBA4tzRJ BCTWUBfYts6FpAKYQE1ibM3vrFCDBSU+LtDGCTMDDR7y9k9rBMYuWYhZGYhyUDYWhIPf91igb C1JZYtfM08C2y+tMTyfxwQYWuJCx++sqEqAbHdJJ4+XMG4gJFjFaNGcWpRWWqRrqG5XlJRZnp GSW5iZo6uoYGxXm5qcXFiempOYlKxXnJ+7iZGYOAxAMEOxpenPQ8xSnIwKYnyKrqHhwvxJeWn VGYkFmfEF5XmpBYfYpTh4FCS4N0jEREuJFiUmp5akZaZA4wBmLQEB4+SCG8sSJq3uCAxtzgzH SJ1ilFRSpzXASQhAJLIKM2Da4PF3SVGWSlhXkagQ4R4ClKLcjNLUOVfMYpzMCoJ85aBTOHJzC uBm/4KaDET0OLlR8JBFpckIqSkGhg7HjW+mCT76euVCV0cqoI6s1v2PFi5uuj3tCsf7tTz3Ng s5Pqi83Xd7ls92nMVn36adJth5+KD2+2mJxzfwlV9m+nvt1lSU/MmP+h/vibx/M+AD/df8m2O 6ZzLreGz6MoN7SeWdrNubiy/qKV48rMNx+Uda113uP7rbO1bf10kXmOu65v10ixrc5VYijMSD bWYi4oTAV5wDa22AgAA X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1465391541!44368343!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 44950 invoked from network); 8 Jun 2016 13:12:22 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-3.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 8 Jun 2016 13:12:22 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 08 Jun 2016 07:12:20 -0600 Message-Id: <575835D202000078000F310A@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Wed, 08 Jun 2016 07:12:18 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH] x86: drop hvm/iommu.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP As a follow-up to commit af07377007 ("IOMMU/x86: per-domain control structure is not HVM-specific"), fold hvm/iommu.h into iommu.h. Signed-off-by: Jan Beulich x86: drop hvm/iommu.h As a follow-up to commit af07377007 ("IOMMU/x86: per-domain control structure is not HVM-specific"), fold hvm/iommu.h into iommu.h. Signed-off-by: Jan Beulich --- a/xen/include/asm-x86/hvm/iommu.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __ASM_X86_HVM_IOMMU_H__ -#define __ASM_X86_HVM_IOMMU_H__ - -#include - -struct iommu_ops; -extern const struct iommu_ops intel_iommu_ops; -extern const struct iommu_ops amd_iommu_ops; -extern int intel_vtd_setup(void); -extern int amd_iov_detect(void); - -static inline const struct iommu_ops *iommu_get_ops(void) -{ - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_INTEL: - return &intel_iommu_ops; - case X86_VENDOR_AMD: - return &amd_iommu_ops; - default: - BUG(); - } - - return NULL; -} - -static inline int iommu_hardware_setup(void) -{ - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_INTEL: - return intel_vtd_setup(); - case X86_VENDOR_AMD: - return amd_iov_detect(); - default: - return -ENODEV; - } - - return 0; -} - -struct g2m_ioport { - struct list_head list; - unsigned int gport; - unsigned int mport; - unsigned int np; -}; - -#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 - -struct arch_iommu -{ - u64 pgd_maddr; /* io page directory machine address */ - spinlock_t mapping_lock; /* io page table lock */ - int agaw; /* adjusted guest address width, 0 is level 2 30-bit */ - struct list_head g2m_ioport_list; /* guest to machine ioport mapping */ - u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */ - struct list_head mapped_rmrrs; - - /* amd iommu support */ - int paging_mode; - struct page_info *root_table; - struct guest_iommu *g_iommu; -}; - -#endif /* __ASM_X86_HVM_IOMMU_H__ */ --- a/xen/include/asm-x86/iommu.h +++ b/xen/include/asm-x86/iommu.h @@ -14,10 +14,69 @@ #ifndef __ARCH_X86_IOMMU_H__ #define __ARCH_X86_IOMMU_H__ -#include /* For now - should really be merged here. */ +#include +#include +#include +#include +#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 #define MAX_IOMMUS 32 +struct g2m_ioport { + struct list_head list; + unsigned int gport; + unsigned int mport; + unsigned int np; +}; + +struct arch_iommu +{ + u64 pgd_maddr; /* io page directory machine address */ + spinlock_t mapping_lock; /* io page table lock */ + int agaw; /* adjusted guest address width, 0 is level 2 30-bit */ + struct list_head g2m_ioport_list; /* guest to machine ioport mapping */ + u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */ + struct list_head mapped_rmrrs; + + /* amd iommu support */ + int paging_mode; + struct page_info *root_table; + struct guest_iommu *g_iommu; +}; + +extern const struct iommu_ops intel_iommu_ops; +extern const struct iommu_ops amd_iommu_ops; +int intel_vtd_setup(void); +int amd_iov_detect(void); + +static inline const struct iommu_ops *iommu_get_ops(void) +{ + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + return &intel_iommu_ops; + case X86_VENDOR_AMD: + return &amd_iommu_ops; + } + + BUG(); + + return NULL; +} + +static inline int iommu_hardware_setup(void) +{ + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + return intel_vtd_setup(); + case X86_VENDOR_AMD: + return amd_iov_detect(); + } + + return -ENODEV; +} + /* Does this domain have a P2M table we can use as its IOMMU pagetable? */ #define iommu_use_hap_pt(d) (hap_enabled(d) && iommu_hap_pt_share) Reviewed-by: Andrew Cooper --- a/xen/include/asm-x86/hvm/iommu.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __ASM_X86_HVM_IOMMU_H__ -#define __ASM_X86_HVM_IOMMU_H__ - -#include - -struct iommu_ops; -extern const struct iommu_ops intel_iommu_ops; -extern const struct iommu_ops amd_iommu_ops; -extern int intel_vtd_setup(void); -extern int amd_iov_detect(void); - -static inline const struct iommu_ops *iommu_get_ops(void) -{ - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_INTEL: - return &intel_iommu_ops; - case X86_VENDOR_AMD: - return &amd_iommu_ops; - default: - BUG(); - } - - return NULL; -} - -static inline int iommu_hardware_setup(void) -{ - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_INTEL: - return intel_vtd_setup(); - case X86_VENDOR_AMD: - return amd_iov_detect(); - default: - return -ENODEV; - } - - return 0; -} - -struct g2m_ioport { - struct list_head list; - unsigned int gport; - unsigned int mport; - unsigned int np; -}; - -#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 - -struct arch_iommu -{ - u64 pgd_maddr; /* io page directory machine address */ - spinlock_t mapping_lock; /* io page table lock */ - int agaw; /* adjusted guest address width, 0 is level 2 30-bit */ - struct list_head g2m_ioport_list; /* guest to machine ioport mapping */ - u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */ - struct list_head mapped_rmrrs; - - /* amd iommu support */ - int paging_mode; - struct page_info *root_table; - struct guest_iommu *g_iommu; -}; - -#endif /* __ASM_X86_HVM_IOMMU_H__ */ --- a/xen/include/asm-x86/iommu.h +++ b/xen/include/asm-x86/iommu.h @@ -14,10 +14,69 @@ #ifndef __ARCH_X86_IOMMU_H__ #define __ARCH_X86_IOMMU_H__ -#include /* For now - should really be merged here. */ +#include +#include +#include +#include +#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 #define MAX_IOMMUS 32 +struct g2m_ioport { + struct list_head list; + unsigned int gport; + unsigned int mport; + unsigned int np; +}; + +struct arch_iommu +{ + u64 pgd_maddr; /* io page directory machine address */ + spinlock_t mapping_lock; /* io page table lock */ + int agaw; /* adjusted guest address width, 0 is level 2 30-bit */ + struct list_head g2m_ioport_list; /* guest to machine ioport mapping */ + u64 iommu_bitmap; /* bitmap of iommu(s) that the domain uses */ + struct list_head mapped_rmrrs; + + /* amd iommu support */ + int paging_mode; + struct page_info *root_table; + struct guest_iommu *g_iommu; +}; + +extern const struct iommu_ops intel_iommu_ops; +extern const struct iommu_ops amd_iommu_ops; +int intel_vtd_setup(void); +int amd_iov_detect(void); + +static inline const struct iommu_ops *iommu_get_ops(void) +{ + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + return &intel_iommu_ops; + case X86_VENDOR_AMD: + return &amd_iommu_ops; + } + + BUG(); + + return NULL; +} + +static inline int iommu_hardware_setup(void) +{ + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + return intel_vtd_setup(); + case X86_VENDOR_AMD: + return amd_iov_detect(); + } + + return -ENODEV; +} + /* Does this domain have a P2M table we can use as its IOMMU pagetable? */ #define iommu_use_hap_pt(d) (hap_enabled(d) && iommu_hap_pt_share)