From patchwork Thu Jun 16 09:40:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9180285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5328260573 for ; Thu, 16 Jun 2016 09:42:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 44F6A269E2 for ; Thu, 16 Jun 2016 09:42:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39B7B28308; Thu, 16 Jun 2016 09:42:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 96732269E2 for ; Thu, 16 Jun 2016 09:42:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bDTn7-0006r6-95; Thu, 16 Jun 2016 09:40:49 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bDTn6-0006qw-O1 for xen-devel@lists.xenproject.org; Thu, 16 Jun 2016 09:40:48 +0000 Received: from [85.158.139.211] by server-4.bemta-5.messagelabs.com id AA/A9-11823-F1472675; Thu, 16 Jun 2016 09:40:47 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRWlGSWpSXmKPExsXS6fjDS1e+JCn c4NF7cYvvWyYzOTB6HP5whSWAMYo1My8pvyKBNePW7wbGgvsWFT97XjI1MF4y6GLk5BASyJNY t/oNG4jNK2AnMXPBQVYQW0LAUGLf/FVgcRYBVYmX/RvZQWw2AXWJtmfbgWo4OEQEDCTOHU0CM ZkF9CW2rWMBqRAWcJK4d+IsG8R0O4kVPcfYQEo4Bewlrq5gATF5BQQl/u4QBqlgBqro3jqDaQ IjzyyEzCwkGQhbS+Lhr1ssELa2xLKFr5lnga2Vllj+jwMi7CBx4/IaRlQlILa3xJGX05gXMHK sYlQvTi0qSy3SNdRLKspMzyjJTczM0TU0MNXLTS0uTkxPzUlMKtZLzs/dxAgM03oGBsYdjE29 zocYJTmYlER5HTWSwoX4kvJTKjMSizPii0pzUosPMcpwcChJ8K4rAsoJFqWmp1akZeYAIwYmL cHBoyTCGwyS5i0uSMwtzkyHSJ1iVJQS590OkhAASWSU5sG1waL0EqOslDAvIwMDgxBPQWpRbm YJqvwrRnEORiVhXoZioCk8mXklcNNfAS1mAlpsMz0eZHFJIkJKqoExPcQv1v0O47NPLE8M30s 8qQiQOfT4aOSdU/a3/G04X3687LMozWrbMdaD7N4m/Gxhsg/Utl5Ln7j4rdWlq7PcHsjO3u/Q OVXNJOzFyiNz39969vuSp1xSbfBWoWWTp4Td8H7wu++typlH5/+0frG5tsLNtNAyUmlHS/Q5j SKW4+FX3HKPN9kqKrEUZyQaajEXFScCAGWNIYzNAgAA X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-11.tower-206.messagelabs.com!1466070044!32964496!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 49524 invoked from network); 16 Jun 2016 09:40:46 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-11.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 16 Jun 2016 09:40:46 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Thu, 16 Jun 2016 03:40:44 -0600 Message-Id: <5762903B02000078000F597E@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.0 Date: Thu, 16 Jun 2016 03:40:43 -0600 From: "Jan Beulich" To: "xen-devel" References: <57628EA302000078000F596B@prv-mh.provo.novell.com> In-Reply-To: <57628EA302000078000F596B@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH 2/2] hvmloader: don't hard-code IO-APIC parameters X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The IO-APIC address has variable bits determined by the PCI-to-ISA bridge, and the IO-APIC version should be read from the IO-APIC. (Note that there's still implicit rather than explicit agreement on the IO-APIC base address between qemu and the hypervisor.) Signed-off-by: Jan Beulich hvmloader: don't hard-code IO-APIC parameters The IO-APIC address has variable bits determined by the PCI-to-ISA bridge, and the IO-APIC version should be read from the IO-APIC. (Note that there's still implicit rather than explicit agreement on the IO-APIC base address between qemu and the hypervisor.) Signed-off-by: Jan Beulich --- a/tools/firmware/hvmloader/acpi/build.c +++ b/tools/firmware/hvmloader/acpi/build.c @@ -138,7 +138,7 @@ static struct acpi_20_madt *construct_ma io_apic->type = ACPI_IO_APIC; io_apic->length = sizeof(*io_apic); io_apic->ioapic_id = IOAPIC_ID; - io_apic->ioapic_addr = IOAPIC_BASE_ADDRESS; + io_apic->ioapic_addr = ioapic_base_address; lapic = (struct acpi_20_madt_lapic *)(io_apic + 1); info->nr_cpus = hvm_info->nr_vcpus; --- a/tools/firmware/hvmloader/config.h +++ b/tools/firmware/hvmloader/config.h @@ -42,9 +42,10 @@ extern struct bios_config ovmf_config; #define PAGE_SHIFT 12 #define PAGE_SIZE (1ul << PAGE_SHIFT) -#define IOAPIC_BASE_ADDRESS 0xfec00000 +extern uint32_t ioapic_base_address; +extern uint8_t ioapic_version; + #define IOAPIC_ID 0x01 -#define IOAPIC_VERSION 0x11 #define LAPIC_BASE_ADDRESS 0xfee00000 #define LAPIC_ID(vcpu_id) ((vcpu_id) * 2) --- a/tools/firmware/hvmloader/hvmloader.c +++ b/tools/firmware/hvmloader/hvmloader.c @@ -108,6 +108,9 @@ asm ( unsigned long scratch_start = SCRATCH_PHYSICAL_ADDRESS; +uint32_t ioapic_base_address = 0xfec00000; +uint8_t ioapic_version; + static void init_hypercalls(void) { uint32_t eax, ebx, ecx, edx; @@ -185,6 +188,9 @@ static void init_vm86_tss(void) static void apic_setup(void) { + ioapic_base_address |= (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << 10; + ioapic_version = ioapic_read(0x01) & 0xff; + /* Set the IOAPIC ID to the static value used in the MP/ACPI tables. */ ioapic_write(0x00, IOAPIC_ID); --- a/tools/firmware/hvmloader/mp_tables.c +++ b/tools/firmware/hvmloader/mp_tables.c @@ -227,9 +227,9 @@ static void fill_mp_ioapic_entry(struct { mpie->type = ENTRY_TYPE_IOAPIC; mpie->ioapic_id = IOAPIC_ID; - mpie->ioapic_version = IOAPIC_VERSION; + mpie->ioapic_version = ioapic_version; mpie->ioapic_flags = 1; /* enabled */ - mpie->ioapic_addr = IOAPIC_BASE_ADDRESS; + mpie->ioapic_addr = ioapic_base_address; } --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -490,14 +490,14 @@ void *scratch_alloc(uint32_t size, uint3 uint32_t ioapic_read(uint32_t reg) { - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg; - return *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10); + *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg; + return *(volatile uint32_t *)(ioapic_base_address + 0x10); } void ioapic_write(uint32_t reg, uint32_t val) { - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg; - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) = val; + *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg; + *(volatile uint32_t *)(ioapic_base_address + 0x10) = val; } uint32_t lapic_read(uint32_t reg) --- a/tools/firmware/hvmloader/acpi/build.c +++ b/tools/firmware/hvmloader/acpi/build.c @@ -138,7 +138,7 @@ static struct acpi_20_madt *construct_ma io_apic->type = ACPI_IO_APIC; io_apic->length = sizeof(*io_apic); io_apic->ioapic_id = IOAPIC_ID; - io_apic->ioapic_addr = IOAPIC_BASE_ADDRESS; + io_apic->ioapic_addr = ioapic_base_address; lapic = (struct acpi_20_madt_lapic *)(io_apic + 1); info->nr_cpus = hvm_info->nr_vcpus; --- a/tools/firmware/hvmloader/config.h +++ b/tools/firmware/hvmloader/config.h @@ -42,9 +42,10 @@ extern struct bios_config ovmf_config; #define PAGE_SHIFT 12 #define PAGE_SIZE (1ul << PAGE_SHIFT) -#define IOAPIC_BASE_ADDRESS 0xfec00000 +extern uint32_t ioapic_base_address; +extern uint8_t ioapic_version; + #define IOAPIC_ID 0x01 -#define IOAPIC_VERSION 0x11 #define LAPIC_BASE_ADDRESS 0xfee00000 #define LAPIC_ID(vcpu_id) ((vcpu_id) * 2) --- a/tools/firmware/hvmloader/hvmloader.c +++ b/tools/firmware/hvmloader/hvmloader.c @@ -108,6 +108,9 @@ asm ( unsigned long scratch_start = SCRATCH_PHYSICAL_ADDRESS; +uint32_t ioapic_base_address = 0xfec00000; +uint8_t ioapic_version; + static void init_hypercalls(void) { uint32_t eax, ebx, ecx, edx; @@ -185,6 +188,9 @@ static void init_vm86_tss(void) static void apic_setup(void) { + ioapic_base_address |= (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << 10; + ioapic_version = ioapic_read(0x01) & 0xff; + /* Set the IOAPIC ID to the static value used in the MP/ACPI tables. */ ioapic_write(0x00, IOAPIC_ID); --- a/tools/firmware/hvmloader/mp_tables.c +++ b/tools/firmware/hvmloader/mp_tables.c @@ -227,9 +227,9 @@ static void fill_mp_ioapic_entry(struct { mpie->type = ENTRY_TYPE_IOAPIC; mpie->ioapic_id = IOAPIC_ID; - mpie->ioapic_version = IOAPIC_VERSION; + mpie->ioapic_version = ioapic_version; mpie->ioapic_flags = 1; /* enabled */ - mpie->ioapic_addr = IOAPIC_BASE_ADDRESS; + mpie->ioapic_addr = ioapic_base_address; } --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -490,14 +490,14 @@ void *scratch_alloc(uint32_t size, uint3 uint32_t ioapic_read(uint32_t reg) { - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg; - return *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10); + *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg; + return *(volatile uint32_t *)(ioapic_base_address + 0x10); } void ioapic_write(uint32_t reg, uint32_t val) { - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg; - *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) = val; + *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg; + *(volatile uint32_t *)(ioapic_base_address + 0x10) = val; } uint32_t lapic_read(uint32_t reg)