From patchwork Wed Aug 3 13:04:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9261225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 08BC56048B for ; Wed, 3 Aug 2016 13:07:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEB24284A6 for ; Wed, 3 Aug 2016 13:07:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E361E28580; Wed, 3 Aug 2016 13:07:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 47E03284A6 for ; Wed, 3 Aug 2016 13:07:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bUvqk-0005GH-5l; Wed, 03 Aug 2016 13:04:42 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bUvqi-0005G3-MX for xen-devel@lists.xenproject.org; Wed, 03 Aug 2016 13:04:40 +0000 Received: from [85.158.139.211] by server-14.bemta-5.messagelabs.com id 65/34-10347-8EBE1A75; Wed, 03 Aug 2016 13:04:40 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRWlGSWpSXmKPExsXS6fjDS/f564X hBn2fJCy+b5nM5MDocfjDFZYAxijWzLyk/IoE1ox7My+wFWzUrfj9qYm1gXGhYhcjJ4eQQJ7E h013GbsYOTh4Bewkln+OBwlLCBhKPH1/nQ3EZhFQlVg0q5kVxGYTUJdoe7adFaRcRMBA4tzRJ BCTWUBfYts6FpAKYaDoiklXmCCG20k8eLiAEcTmFLCX+DR3DgvEIkGJvzuEITrtJFbNcZrAyD MLITELITELqJVZQEvi4a9bLBC2tsSyha+ZIUqkJZb/44AI20lcednBhKoExPaUmDKzk20BI8c qRo3i1KKy1CJdIxO9pKLM9IyS3MTMHF1DA1O93NTi4sT01JzEpGK95PzcTYzAIK1nYGDcwXhz st8hRkkOJiVR3okHF4YL8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuC98xIoJ1iUmp5akZaZA4wXm LQEB4+SCO+t50Bp3uKCxNzizHSI1ClGRSlx3vcgfQIgiYzSPLg2WIxeYpSVEuZlZGBgEOIpSC 3KzSxBlX/FKM7BqCTMG/MKaApPZl4J3PRXQIuZgBafMFgAsrgkESEl1cBYkJb///u3vVt+f+P aGOHDGuUr5zlr/iW2mria4hk9z1LmBxhonzXg1SlIXV+cpjbh+IulD96sUfyUNPWKuFGR6ivj DQqWeYVGAlb9VQz+aQabFEuELSTFds5f3vPpd5VRiOjid+ZzNq4MfLDUy+7H3BWn+Zn2FSiUi z/5pHR5mcvOWR3O3zqVWIozEg21mIuKEwFzLnd3zAIAAA== X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-14.tower-206.messagelabs.com!1470229477!16342867!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 40058 invoked from network); 3 Aug 2016 13:04:39 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-14.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 3 Aug 2016 13:04:39 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 03 Aug 2016 07:04:36 -0600 Message-Id: <57A2080202000078001023AA@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Wed, 03 Aug 2016 07:04:34 -0600 From: "Jan Beulich" To: "xen-devel" References: <57A205C50200007800102378@prv-mh.provo.novell.com> In-Reply-To: <57A205C50200007800102378@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH v2 6/6] x86/time: relax barriers X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP On x86 there's no need for full barriers in loops waiting for some memory location to change. Nor do we need full barriers between two reads and two writes - SMP ones fully suffice (and I actually think they could in fact be dropped, since atomic_*() operations should already provide enough ordering). x86/time: relax barriers On x86 there's no need for full barriers in loops waiting for some memory location to change. Nor do we need full barriers between two reads and two writes - SMP ones fully suffice (and I actually think they could in fact be dropped, since atomic_*() operations should already provide enough ordering). --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1206,7 +1206,7 @@ static void tsc_check_slave(void *unused unsigned int cpu = smp_processor_id(); local_irq_disable(); while ( !cpumask_test_cpu(cpu, &tsc_check_cpumask) ) - mb(); + cpu_relax(); check_tsc_warp(cpu_khz, &tsc_max_warp); cpumask_clear_cpu(cpu, &tsc_check_cpumask); local_irq_enable(); @@ -1271,7 +1271,7 @@ static void time_calibration_tsc_rendezv if ( smp_processor_id() == 0 ) { while ( atomic_read(&r->semaphore) != (total_cpus - 1) ) - mb(); + cpu_relax(); if ( r->master_stime == 0 ) { @@ -1284,21 +1284,21 @@ static void time_calibration_tsc_rendezv write_tsc(r->master_tsc_stamp); while ( atomic_read(&r->semaphore) != (2*total_cpus - 1) ) - mb(); + cpu_relax(); atomic_set(&r->semaphore, 0); } else { atomic_inc(&r->semaphore); while ( atomic_read(&r->semaphore) < total_cpus ) - mb(); + cpu_relax(); if ( i == 0 ) write_tsc(r->master_tsc_stamp); atomic_inc(&r->semaphore); while ( atomic_read(&r->semaphore) > total_cpus ) - mb(); + cpu_relax(); } } @@ -1316,7 +1316,7 @@ static void time_calibration_std_rendezv while ( atomic_read(&r->semaphore) != (total_cpus - 1) ) cpu_relax(); r->master_stime = read_platform_stime(); - mb(); /* write r->master_stime /then/ signal */ + smp_wmb(); /* write r->master_stime /then/ signal */ atomic_inc(&r->semaphore); } else @@ -1324,7 +1324,7 @@ static void time_calibration_std_rendezv atomic_inc(&r->semaphore); while ( atomic_read(&r->semaphore) != total_cpus ) cpu_relax(); - mb(); /* receive signal /then/ read r->master_stime */ + smp_rmb(); /* receive signal /then/ read r->master_stime */ } time_calibration_rendezvous_tail(r); --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1206,7 +1206,7 @@ static void tsc_check_slave(void *unused unsigned int cpu = smp_processor_id(); local_irq_disable(); while ( !cpumask_test_cpu(cpu, &tsc_check_cpumask) ) - mb(); + cpu_relax(); check_tsc_warp(cpu_khz, &tsc_max_warp); cpumask_clear_cpu(cpu, &tsc_check_cpumask); local_irq_enable(); @@ -1271,7 +1271,7 @@ static void time_calibration_tsc_rendezv if ( smp_processor_id() == 0 ) { while ( atomic_read(&r->semaphore) != (total_cpus - 1) ) - mb(); + cpu_relax(); if ( r->master_stime == 0 ) { @@ -1284,21 +1284,21 @@ static void time_calibration_tsc_rendezv write_tsc(r->master_tsc_stamp); while ( atomic_read(&r->semaphore) != (2*total_cpus - 1) ) - mb(); + cpu_relax(); atomic_set(&r->semaphore, 0); } else { atomic_inc(&r->semaphore); while ( atomic_read(&r->semaphore) < total_cpus ) - mb(); + cpu_relax(); if ( i == 0 ) write_tsc(r->master_tsc_stamp); atomic_inc(&r->semaphore); while ( atomic_read(&r->semaphore) > total_cpus ) - mb(); + cpu_relax(); } } @@ -1316,7 +1316,7 @@ static void time_calibration_std_rendezv while ( atomic_read(&r->semaphore) != (total_cpus - 1) ) cpu_relax(); r->master_stime = read_platform_stime(); - mb(); /* write r->master_stime /then/ signal */ + smp_wmb(); /* write r->master_stime /then/ signal */ atomic_inc(&r->semaphore); } else @@ -1324,7 +1324,7 @@ static void time_calibration_std_rendezv atomic_inc(&r->semaphore); while ( atomic_read(&r->semaphore) != total_cpus ) cpu_relax(); - mb(); /* receive signal /then/ read r->master_stime */ + smp_rmb(); /* receive signal /then/ read r->master_stime */ } time_calibration_rendezvous_tail(r);