diff mbox

x86/AMD: apply erratum 665 workaround

Message ID 57E9306C02000078001126D8@prv-mh.provo.novell.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jan Beulich Sept. 26, 2016, 12:27 p.m. UTC 
From: Emanuel Czirai <icanrealizeum@gmail.com>

AMD F12h machines have an erratum which can cause DIV/IDIV to behave
unpredictably. The workaround is to set MSRC001_1029[31] but sometimes
there is no BIOS update containing that workaround so let's do it
ourselves unconditionally. It is simple enough.

[ Borislav: Wrote commit message. ]

Signed-off-by: Emanuel Czirai <icanrealizeum@gmail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
[Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4]

Make applicable to Xen.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
x86/AMD: apply erratum 665 workaround

From: Emanuel Czirai <icanrealizeum@gmail.com>

AMD F12h machines have an erratum which can cause DIV/IDIV to behave
unpredictably. The workaround is to set MSRC001_1029[31] but sometimes
there is no BIOS update containing that workaround so let's do it
ourselves unconditionally. It is simple enough.

[ Borislav: Wrote commit message. ]

Signed-off-by: Emanuel Czirai <icanrealizeum@gmail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
[Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4]

Make applicable to Xen.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -661,6 +661,18 @@ static void init_amd(struct cpuinfo_x86
 				       smp_processor_id());
 			wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
 		}
+	} else if (c->x86 == 0x12) {
+		rdmsrl(MSR_AMD64_DE_CFG, value);
+		if (!(value & (1U << 31))) {
+			static bool warned;
+
+			if (c == &boot_cpu_data || opt_cpu_info ||
+			    !test_and_set_bool(warned))
+				printk(KERN_WARNING
+				       "CPU%u: Applying workaround for erratum 665\n",
+				       smp_processor_id());
+			wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
+		}
 	}
 
 	/* AMD CPUs do not support SYSENTER outside of legacy mode. */
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -199,10 +199,11 @@
 
 /* AMD64 MSRs */
 #define MSR_AMD64_NB_CFG		0xc001001f
+#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_IC_CFG		0xc0011021
 #define MSR_AMD64_DC_CFG		0xc0011022
-#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
+#define MSR_AMD64_DE_CFG		0xc0011029
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK	0xc0011019

Comments

Andrew Cooper Sept. 26, 2016, 12:49 p.m. UTC | #1 
On 26/09/16 13:27, Jan Beulich wrote:
> From: Emanuel Czirai <icanrealizeum@gmail.com>
>
> AMD F12h machines have an erratum which can cause DIV/IDIV to behave
> unpredictably. The workaround is to set MSRC001_1029[31] but sometimes
> there is no BIOS update containing that workaround so let's do it
> ourselves unconditionally. It is simple enough.
>
> [ Borislav: Wrote commit message. ]
>
> Signed-off-by: Emanuel Czirai <icanrealizeum@gmail.com>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> [Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4]
>
> Make applicable to Xen.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

It would be nice to have a name for this bit, but the Fam 12h BKDG
identified it as reserved, making the erratum description the only
reference I can find to it.  Oh well.

~Andrew
diff mbox

Patch

--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -661,6 +661,18 @@  static void init_amd(struct cpuinfo_x86
 				       smp_processor_id());
 			wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
 		}
+	} else if (c->x86 == 0x12) {
+		rdmsrl(MSR_AMD64_DE_CFG, value);
+		if (!(value & (1U << 31))) {
+			static bool warned;
+
+			if (c == &boot_cpu_data || opt_cpu_info ||
+			    !test_and_set_bool(warned))
+				printk(KERN_WARNING
+				       "CPU%u: Applying workaround for erratum 665\n",
+				       smp_processor_id());
+			wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
+		}
 	}
 
 	/* AMD CPUs do not support SYSENTER outside of legacy mode. */
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -199,10 +199,11 @@ 
 
 /* AMD64 MSRs */
 #define MSR_AMD64_NB_CFG		0xc001001f
+#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_IC_CFG		0xc0011021
 #define MSR_AMD64_DC_CFG		0xc0011022
-#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
+#define MSR_AMD64_DE_CFG		0xc0011029
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK	0xc0011019