From patchwork Mon Sep 26 12:27:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9350625 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6957E6077B for ; Mon, 26 Sep 2016 12:31:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56D8628C1C for ; Mon, 26 Sep 2016 12:31:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46D7F28D19; Mon, 26 Sep 2016 12:31:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4249028C1C for ; Mon, 26 Sep 2016 12:31:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1boV0w-0001FN-NC; Mon, 26 Sep 2016 12:28:06 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1boV0v-0001FH-BE for xen-devel@lists.xenproject.org; Mon, 26 Sep 2016 12:28:05 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id 09/31-23620-45419E75; Mon, 26 Sep 2016 12:28:04 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCIsWRWlGSWpSXmKPExsXS6fjDSzdY5GW 4wYN38hbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8brldfYC/4rVHT+3cTewLhapouRk0NIIE/i 5ZnVrCA2r4CdRMeUDcwgtoSAocTT99fZQGwWAVWJi1+72EFsNgF1ibZn24HqOThEBAwkzh1NA jGZBfQltq1jAakQFjCT+PP0PzNImFdAUOLvDmGQMDPQ8NNzetgmMHLNQsjMQpKBsLUkHv66xQ Jha0ssW/iaeRbYfGmJ5f84IMJWEr/O9rGjKgGxXSW+7//OvICRYxWjRnFqUVlqka6hpV5SUWZ 6RkluYmaOrqGBsV5uanFxYnpqTmJSsV5yfu4mRmDo1TMwMO5g/H3c7xCjJAeTkijvp9svwoX4 kvJTKjMSizPii0pzUosPMcpwcChJ8H4SehkuJFiUmp5akZaZA4wCmLQEB4+SCC+LMFCat7ggM bc4Mx0idYpRUUqcVwAkIQCSyCjNg2uDRd4lRlkpYV5GBgYGIZ6C1KLczBJU+VeM4hyMSsK8HC BTeDLzSuCmvwJazAS0eOmJFyCLSxIRUlINjDKHAxKjbG6x3Eh9vtN/XsgPb/829YDAuxrBHp8 rvDjiM4rSS/7rXwl9Mceocv493/UxErUfKm/NcDNyX6BwsD1CsjJUdq1tif7s6lxRCcULvUZ3 X08z6xDskV3O//PY373i54smRO/neuPhqrUl/NSLFxvDJD40bTz55tsDT+nlT40zOsK+K7EUZ yQaajEXFScCAEr+qU63AgAA X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-14.tower-31.messagelabs.com!1474892881!62698393!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.84; banners=-,-,- X-VirusChecked: Checked Received: (qmail 57948 invoked from network); 26 Sep 2016 12:28:03 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-14.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 26 Sep 2016 12:28:03 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Mon, 26 Sep 2016 06:28:00 -0600 Message-Id: <57E9306C02000078001126D8@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Mon, 26 Sep 2016 06:27:56 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH] x86/AMD: apply erratum 665 workaround X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Emanuel Czirai AMD F12h machines have an erratum which can cause DIV/IDIV to behave unpredictably. The workaround is to set MSRC001_1029[31] but sometimes there is no BIOS update containing that workaround so let's do it ourselves unconditionally. It is simple enough. [ Borislav: Wrote commit message. ] Signed-off-by: Emanuel Czirai Signed-off-by: Borislav Petkov [Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4] Make applicable to Xen. Signed-off-by: Jan Beulich x86/AMD: apply erratum 665 workaround From: Emanuel Czirai AMD F12h machines have an erratum which can cause DIV/IDIV to behave unpredictably. The workaround is to set MSRC001_1029[31] but sometimes there is no BIOS update containing that workaround so let's do it ourselves unconditionally. It is simple enough. [ Borislav: Wrote commit message. ] Signed-off-by: Emanuel Czirai Signed-off-by: Borislav Petkov [Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4] Make applicable to Xen. Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -661,6 +661,18 @@ static void init_amd(struct cpuinfo_x86 smp_processor_id()); wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15)); } + } else if (c->x86 == 0x12) { + rdmsrl(MSR_AMD64_DE_CFG, value); + if (!(value & (1U << 31))) { + static bool warned; + + if (c == &boot_cpu_data || opt_cpu_info || + !test_and_set_bool(warned)) + printk(KERN_WARNING + "CPU%u: Applying workaround for erratum 665\n", + smp_processor_id()); + wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31)); + } } /* AMD CPUs do not support SYSENTER outside of legacy mode. */ --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -199,10 +199,11 @@ /* AMD64 MSRs */ #define MSR_AMD64_NB_CFG 0xc001001f +#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_IC_CFG 0xc0011021 #define MSR_AMD64_DC_CFG 0xc0011022 -#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 +#define MSR_AMD64_DE_CFG 0xc0011029 #define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019 Reviewed-by: Andrew Cooper --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -661,6 +661,18 @@ static void init_amd(struct cpuinfo_x86 smp_processor_id()); wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15)); } + } else if (c->x86 == 0x12) { + rdmsrl(MSR_AMD64_DE_CFG, value); + if (!(value & (1U << 31))) { + static bool warned; + + if (c == &boot_cpu_data || opt_cpu_info || + !test_and_set_bool(warned)) + printk(KERN_WARNING + "CPU%u: Applying workaround for erratum 665\n", + smp_processor_id()); + wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31)); + } } /* AMD CPUs do not support SYSENTER outside of legacy mode. */ --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -199,10 +199,11 @@ /* AMD64 MSRs */ #define MSR_AMD64_NB_CFG 0xc001001f +#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_IC_CFG 0xc0011021 #define MSR_AMD64_DC_CFG 0xc0011022 -#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 +#define MSR_AMD64_DE_CFG 0xc0011029 #define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019