From patchwork Thu Oct 13 12:57:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9374939 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BFA9860487 for ; Thu, 13 Oct 2016 12:59:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B12942A059 for ; Thu, 13 Oct 2016 12:59:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5CCE2A05B; Thu, 13 Oct 2016 12:59:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 776D92A059 for ; Thu, 13 Oct 2016 12:59:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bufZY-0005wt-M6; Thu, 13 Oct 2016 12:57:20 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bufZW-0005wn-M1 for xen-devel@lists.xenproject.org; Thu, 13 Oct 2016 12:57:18 +0000 Received: from [85.158.139.211] by server-12.bemta-5.messagelabs.com id 1A/D2-09561-DA48FF75; Thu, 13 Oct 2016 12:57:17 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRWlGSWpSXmKPExsXS6fjDS3dVy/9 wg9Pb2S2+b5nM5MDocfjDFZYAxijWzLyk/IoE1ozvr/cxFhzWrGg8tpixgXG/bBcjJ4eQQJ7E i9O72UFsXgE7ie1fzzGB2BIChhJP319nA7FZBFQlnv/YzgxiswmoS7Q9287axcjBISJgIHHua BKIySygL7FtHQtIhbCAhsSv/fOZQcK8AoISf3cIg4SZgYZfmfGabQIj1yyEzCwkGQhbS+Lhr1 ssELa2xLKFr5lngc2Xllj+jwMibCuxveMKmhIQ20OiYeVB1gWMHKsYNYpTi8pSi3SNzPWSijL TM0pyEzNzdA0NTPVyU4uLE9NTcxKTivWS83M3MQJDr56BgXEH49UtfocYJTmYlER5f/n9Dxfi S8pPqcxILM6ILyrNSS0+xKjBwSGwbdfqC4xSLHn5ealKErybmoHqBItS01Mr0jJzgNEBUyrBw aMkwvsbJM1bXJCYW5yZDpE6xagoJc57HiQhAJLIKM2Da4NF5CVGWSlhXkYGBgYhnoLUotzMEl T5V4ziHIxKwrxpIFN4MvNK4Ka/AlrMBLTYZtIfkMUliQgpqQbGSaZaqtsnNq7IlL2x2Un7Ed9 589ynK5cci2JcEB+k93Bz36q16Xtu33J8EegVtlht6fqdbRwipixRS7L71RxiVF/bitl+flUu X9oj3P/h5+6pCQ+lnxp+XKKhI92henLC1L/xTc/Winx52pg7/8xi/fSFX45vKnnWntEuuPR+f c+DTTz1YbmtSizFGYmGWsxFxYkAuOvkRMMCAAA= X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-7.tower-206.messagelabs.com!1476363432!64507955!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.84; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22257 invoked from network); 13 Oct 2016 12:57:13 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-7.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 13 Oct 2016 12:57:13 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Thu, 13 Oct 2016 06:57:10 -0600 Message-Id: <57FFA0C60200007800117173@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Thu, 13 Oct 2016 06:57:10 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH] x86emul: honor MXCSR.MM X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory operands") didn't consider a specific AMD mode: Mis-alignment #GP faults can be masked on some of their hardware. Signed-off-by: Jan Beulich x86emul: honor MXCSR.MM Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory operands") didn't consider a specific AMD mode: Mis-alignment #GP faults can be masked on some of their hardware. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -446,6 +446,9 @@ typedef union { #define EFLG_PF (1<<2) #define EFLG_CF (1<<0) +/* MXCSR bit definitions. */ +#define MXCSR_MM (1U << 17) + /* Exception definitions. */ #define EXC_DE 0 #define EXC_DB 1 @@ -1253,6 +1256,7 @@ static bool_t vcpu_has( #define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) #define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) +#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) #define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops) #define vcpu_has_hle() vcpu_has(0x00000007, EBX, 4, ctxt, ops) #define vcpu_has_rtm() vcpu_has(0x00000007, EBX, 11, ctxt, ops) @@ -4675,7 +4679,13 @@ x86_emulate( ea.bytes = vex.pfx & VEX_PREFIX_DOUBLE_MASK ? 8 : 4; if ( ea.type == OP_MEM ) { - generate_exception_if((b >= 0x28) && + uint32_t mxcsr = 0; + + if ( b < 0x28 ) + mxcsr = MXCSR_MM; + else if ( vcpu_has_misalignsse() ) + asm ( "stmxcsr %0" : "=m" (mxcsr) ); + generate_exception_if(!(mxcsr & MXCSR_MM) && !is_aligned(ea.mem.seg, ea.mem.off, ea.bytes, ctxt, ops), EXC_GP, 0); @@ -4955,7 +4965,13 @@ x86_emulate( } if ( ea.type == OP_MEM ) { - generate_exception_if((vex.pfx == vex_66) && + uint32_t mxcsr = 0; + + if ( vex.pfx != vex_66 ) + mxcsr = MXCSR_MM; + else if ( vcpu_has_misalignsse() ) + asm ( "stmxcsr %0" : "=m" (mxcsr) ); + generate_exception_if(!(mxcsr & MXCSR_MM) && !is_aligned(ea.mem.seg, ea.mem.off, ea.bytes, ctxt, ops), EXC_GP, 0); --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -446,6 +446,9 @@ typedef union { #define EFLG_PF (1<<2) #define EFLG_CF (1<<0) +/* MXCSR bit definitions. */ +#define MXCSR_MM (1U << 17) + /* Exception definitions. */ #define EXC_DE 0 #define EXC_DB 1 @@ -1253,6 +1256,7 @@ static bool_t vcpu_has( #define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) #define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) +#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) #define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops) #define vcpu_has_hle() vcpu_has(0x00000007, EBX, 4, ctxt, ops) #define vcpu_has_rtm() vcpu_has(0x00000007, EBX, 11, ctxt, ops) @@ -4675,7 +4679,13 @@ x86_emulate( ea.bytes = vex.pfx & VEX_PREFIX_DOUBLE_MASK ? 8 : 4; if ( ea.type == OP_MEM ) { - generate_exception_if((b >= 0x28) && + uint32_t mxcsr = 0; + + if ( b < 0x28 ) + mxcsr = MXCSR_MM; + else if ( vcpu_has_misalignsse() ) + asm ( "stmxcsr %0" : "=m" (mxcsr) ); + generate_exception_if(!(mxcsr & MXCSR_MM) && !is_aligned(ea.mem.seg, ea.mem.off, ea.bytes, ctxt, ops), EXC_GP, 0); @@ -4955,7 +4965,13 @@ x86_emulate( } if ( ea.type == OP_MEM ) { - generate_exception_if((vex.pfx == vex_66) && + uint32_t mxcsr = 0; + + if ( vex.pfx != vex_66 ) + mxcsr = MXCSR_MM; + else if ( vcpu_has_misalignsse() ) + asm ( "stmxcsr %0" : "=m" (mxcsr) ); + generate_exception_if(!(mxcsr & MXCSR_MM) && !is_aligned(ea.mem.seg, ea.mem.off, ea.bytes, ctxt, ops), EXC_GP, 0);