| Message ID | 580E17FB0200007800118FB7@prv-mh.provo.novell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 24/10/16 13:17, Jan Beulich wrote: > Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> > Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> > > --- a/xen/tools/gen-cpuid.py > +++ b/xen/tools/gen-cpuid.py > @@ -196,8 +196,9 @@ def crunch_numbers(state): > > # SSE is taken to mean support for the %XMM registers as well as the > # instructions. Several futher instruction sets are built on core > - # %XMM support, without specific inter-dependencies. > - SSE: [SSE2, SSE3, SSSE3, SSE4A, > + # %XMM support, without specific inter-dependencies. Additionally > + # AMD has a special mis-alignment sub-mode. > + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE, > AESNI, SHA], > > # SSE2 was re-specified as core instructions for 64bit. > > >
On Mon, Oct 24, 2016 at 03:10:49PM +0100, Andrew Cooper wrote: > On 24/10/16 13:17, Jan Beulich wrote: > > Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> > > Signed-off-by: Jan Beulich <jbeulich@suse.com> > > Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> > Release-acked-by: Wei Liu <wei.liu2@citrix.com>
--- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -196,8 +196,9 @@ def crunch_numbers(state): # SSE is taken to mean support for the %XMM registers as well as the # instructions. Several futher instruction sets are built on core - # %XMM support, without specific inter-dependencies. - SSE: [SSE2, SSE3, SSSE3, SSE4A, + # %XMM support, without specific inter-dependencies. Additionally + # AMD has a special mis-alignment sub-mode. + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE, AESNI, SHA], # SSE2 was re-specified as core instructions for 64bit.