From patchwork Mon Oct 24 12:17:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9391971 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B47AE6077A for ; Mon, 24 Oct 2016 12:19:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A73C328FC3 for ; Mon, 24 Oct 2016 12:19:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C04328FC5; Mon, 24 Oct 2016 12:19:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1048E28FC4 for ; Mon, 24 Oct 2016 12:19:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byeCD-0002Cw-4R; Mon, 24 Oct 2016 12:17:41 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byeCC-0002Cg-4O for xen-devel@lists.xenproject.org; Mon, 24 Oct 2016 12:17:40 +0000 Received: from [85.158.137.68] by server-2.bemta-3.messagelabs.com id 7D/32-01907-3EBFD085; Mon, 24 Oct 2016 12:17:39 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCIsWRWlGSWpSXmKPExsXS6fjDS/fRb94 Ig8dtPBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8blHe3MBS8FKuaePcfawHiRt4uRk0NIIE/i 47xJbF2MHBy8AnYSe6/Gg4QlBAwlnr6/zgZiswioSvx++pUJxGYTUJdoe7adFaRcRMBA4tzRJ JAws0CgxK37MxhBbGEBC4kz73awQkwUlPi7QxiixE5i7s1TjBMYuWYhZGYhyUDYWhIPf91igb C1JZYtfM0MUs4sIC2x/B8HRNhK4sXyWcyoSkBsV4mbd8+zL2DkWMWoUZxaVJZapGtkrJdUlJm eUZKbmJmja2hgrJebWlycmJ6ak5hUrJecn7uJERh69QwMjDsY+/b6HWKU5GBSEuVdeJE3Qogv KT+lMiOxOCO+qDQntfgQowwHh5IE775fQDnBotT01Iq0zBxgFMCkJTh4lER4L4CkeYsLEnOLM 9MhUqcYFaXEebeDJARAEhmleXBtsMi7xCgrJczLyMDAIMRTkFqUm1mCKv+KUZyDUUmY9zvIFJ 7MvBK46a+AFjMBLRaM5wFZXJKIkJJqYMz4r79u4pTZDSfbKrXVfCWlZgRoT9nO/+QQ0+SLMa+ MnK2XV7/rWFHd2PX89MzkdXdvi3sc3VN9oP5Nx+kpBuWvW/XFTa66sgatPH/jcaNcXsCG3slC 1cU14bwbeUWWs3wP9D4XEvfyKs8Tq30n0m7FbN3y6jnrLHaxJymtx43z+ljPM7NyGCqxFGckG moxFxUnAgBuVejhtwIAAA== X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1477311456!63822175!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.13; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36124 invoked from network); 24 Oct 2016 12:17:37 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-5.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 24 Oct 2016 12:17:37 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Mon, 24 Oct 2016 06:17:35 -0600 Message-Id: <580E17FB0200007800118FB7@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Mon, 24 Oct 2016 06:17:31 -0600 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper , Wei Liu Subject: [Xen-devel] [PATCH] x86: MISALIGNSSE feature depends on SSE X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Suggested-by: Andrew Cooper Signed-off-by: Jan Beulich x86: MISALIGNSSE feature depends on SSE Suggested-by: Andrew Cooper Signed-off-by: Jan Beulich --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -196,8 +196,9 @@ def crunch_numbers(state): # SSE is taken to mean support for the %XMM registers as well as the # instructions. Several futher instruction sets are built on core - # %XMM support, without specific inter-dependencies. - SSE: [SSE2, SSE3, SSSE3, SSE4A, + # %XMM support, without specific inter-dependencies. Additionally + # AMD has a special mis-alignment sub-mode. + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE, AESNI, SHA], # SSE2 was re-specified as core instructions for 64bit. Reviewed-by: Andrew Cooper --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -196,8 +196,9 @@ def crunch_numbers(state): # SSE is taken to mean support for the %XMM registers as well as the # instructions. Several futher instruction sets are built on core - # %XMM support, without specific inter-dependencies. - SSE: [SSE2, SSE3, SSSE3, SSE4A, + # %XMM support, without specific inter-dependencies. Additionally + # AMD has a special mis-alignment sub-mode. + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE, AESNI, SHA], # SSE2 was re-specified as core instructions for 64bit.