diff mbox

x86emul: suppress alignment check for {, v}mov{d, q}

Message ID 5824763C020000780011DA56@prv-mh.provo.novell.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jan Beulich Nov. 10, 2016, 12:29 p.m. UTC 
When introducing support for these instructions, adjustment for the
alignment check logic (generating #GP(0)) was overlooked.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
x86emul: suppress alignment check for {,v}mov{d,q}

When introducing support for these instructions, adjustment for the
alignment check logic (generating #GP(0)) was overlooked.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -4940,7 +4940,7 @@ x86_emulate(
         {
             uint32_t mxcsr = 0;
 
-            if ( vex.pfx != vex_66 )
+            if ( ea.bytes < 16 || vex.pfx == vex_f3 )
                 mxcsr = MXCSR_MM;
             else if ( vcpu_has_misalignsse() )
                 asm ( "stmxcsr %0" : "=m" (mxcsr) );

Comments

Andrew Cooper Nov. 11, 2016, 3:36 p.m. UTC | #1 
On 10/11/16 12:29, Jan Beulich wrote:
> When introducing support for these instructions, adjustment for the
> alignment check logic (generating #GP(0)) was overlooked.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Wei Liu Nov. 12, 2016, 6:45 a.m. UTC | #2 
On Fri, Nov 11, 2016 at 03:36:13PM +0000, Andrew Cooper wrote:
> On 10/11/16 12:29, Jan Beulich wrote:
> > When introducing support for these instructions, adjustment for the
> > alignment check logic (generating #GP(0)) was overlooked.
> >
> > Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

Applied.
diff mbox

Patch

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -4940,7 +4940,7 @@  x86_emulate(
         {
             uint32_t mxcsr = 0;
 
-            if ( vex.pfx != vex_66 )
+            if ( ea.bytes < 16 || vex.pfx == vex_f3 )
                 mxcsr = MXCSR_MM;
             else if ( vcpu_has_misalignsse() )
                 asm ( "stmxcsr %0" : "=m" (mxcsr) );