From patchwork Fri Dec 9 11:53:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9468013 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 684FB60586 for ; Fri, 9 Dec 2016 11:56:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57B9E285DE for ; Fri, 9 Dec 2016 11:56:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A272285F8; Fri, 9 Dec 2016 11:56:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6829E285DE for ; Fri, 9 Dec 2016 11:56:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cFJkY-0005Ow-Jh; Fri, 09 Dec 2016 11:54:02 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cFJkX-0005Oq-Mx for xen-devel@lists.xenproject.org; Fri, 09 Dec 2016 11:54:01 +0000 Received: from [85.158.139.211] by server-13.bemta-5.messagelabs.com id 4F/A5-30393-65B9A485; Fri, 09 Dec 2016 11:53:58 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNIsWRWlGSWpSXmKPExsXS6fjDSzdktle Ewa3nwhbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8bDgzMYCw7HVHzu2s/SwLjWo4uRk0NIIE9i 7cbVjCA2r4CdxNePX9lBbAkBQ4mn76+zgdgsAqoS+74vZQWx2QTUJdqebQeyOThEBAwkzh1NA jGZBfQltq1jAakQFnCVOH3gKDvEdDuJ3nXHwGxOAXuJVx8PsIOU8woISvzdIQwSZgYqeTN7L8 sERp5ZCJlZSDIQtpbEw1+3oGxtiWULXzPPAtsrLbH8HwdE2FZix4RvjKhKQGwPiRe7GxgXMHK sYlQvTi0qSy3StdBLKspMzyjJTczM0TU0MNXLTS0uTkxPzUlMKtZLzs/dxAgMVAYg2MF4sNn5 EKMkB5OSKG8xk1eEEF9SfkplRmJxRnxRaU5q8SFGGQ4OJQlex1lAOcGi1PTUirTMHGDMwKQlO HiURHhvzwBK8xYXJOYWZ6ZDpE4xKkqJ816dCZQQAElklObBtcHi9BKjrJQwLyPQIUI8BalFuZ klqPKvGMU5GJWEeZ1BtvNk5pXATX8FtJgJaPG8G+4gi0sSEVJSDYzeCZE577udXedumH7iYsZ 3/+dFs751sgkZK3Fe3it67sRaH+MjUUriEepcxcHbG1LvHj9unF8bl5qXtbjIJEptt/9k5T/3 Wd7U3lwbJjKHQXvaLu5vVknrDI5fc/w2q+vBGduHK7k4xW4aJt0QPfztOSPHmWNOF0qTG9dtX 5f7SrR176f9bC+UWIozEg21mIuKEwFNYRxvzgIAAA== X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-4.tower-206.messagelabs.com!1481284431!74714056!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6516 invoked from network); 9 Dec 2016 11:53:54 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-4.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 9 Dec 2016 11:53:54 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Fri, 09 Dec 2016 04:53:52 -0700 Message-Id: <584AA95F02000078001273AA@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Fri, 09 Dec 2016 04:53:51 -0700 From: "Jan Beulich" To: "xen-devel" References: <584AA71A020000780012738C@prv-mh.provo.novell.com> In-Reply-To: <584AA71A020000780012738C@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH 1/2] x86emul: derive vcpu_must_have() from vcpu_has() X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP ... to avoid introducing further redundancy when adding further feature flag checks, and to bring its use better in line with its host_and_*() sibling. Signed-off-by: Jan Beulich x86emul: derive vcpu_must_have() from vcpu_has() ... to avoid introducing further redundancy when adding further feature flag checks, and to bring its use better in line with its host_and_*() sibling. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1260,39 +1260,39 @@ static bool vcpu_has( return rc == X86EMUL_OKAY; } -#define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) -#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) -#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) -#define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops) -#define vcpu_has_hle() vcpu_has(0x00000007, EBX, 4, ctxt, ops) -#define vcpu_has_rtm() vcpu_has(0x00000007, EBX, 11, ctxt, ops) - -#define vcpu_must_have(leaf, reg, bit) \ - generate_exception_if(!vcpu_has(leaf, reg, bit, ctxt, ops), EXC_UD) -#define vcpu_must_have_fpu() vcpu_must_have(0x00000001, EDX, 0) -#define vcpu_must_have_cmov() vcpu_must_have(0x00000001, EDX, 15) -#define vcpu_must_have_mmx() vcpu_must_have(0x00000001, EDX, 23) -#define vcpu_must_have_sse() vcpu_must_have(0x00000001, EDX, 25) -#define vcpu_must_have_sse2() vcpu_must_have(0x00000001, EDX, 26) -#define vcpu_must_have_sse3() vcpu_must_have(0x00000001, ECX, 0) -#define vcpu_must_have_cx16() vcpu_must_have(0x00000001, ECX, 13) -#define vcpu_must_have_sse4_2() vcpu_must_have(0x00000001, ECX, 20) -#define vcpu_must_have_movbe() vcpu_must_have(0x00000001, ECX, 22) -#define vcpu_must_have_avx() vcpu_must_have(0x00000001, ECX, 28) +#define vcpu_has_fpu() vcpu_has( 1, EDX, 0, ctxt, ops) +#define vcpu_has_cmov() vcpu_has( 1, EDX, 15, ctxt, ops) +#define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) +#define vcpu_has_mmx() vcpu_has( 1, EDX, 23, ctxt, ops) +#define vcpu_has_sse() vcpu_has( 1, EDX, 25, ctxt, ops) +#define vcpu_has_sse2() vcpu_has( 1, EDX, 26, ctxt, ops) +#define vcpu_has_sse3() vcpu_has( 1, ECX, 0, ctxt, ops) +#define vcpu_has_cx16() vcpu_has( 1, ECX, 13, ctxt, ops) +#define vcpu_has_sse4_2() vcpu_has( 1, ECX, 20, ctxt, ops) +#define vcpu_has_movbe() vcpu_has( 1, ECX, 22, ctxt, ops) +#define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops) +#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) +#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) +#define vcpu_has_bmi1() vcpu_has( 7, EBX, 3, ctxt, ops) +#define vcpu_has_hle() vcpu_has( 7, EBX, 4, ctxt, ops) +#define vcpu_has_rtm() vcpu_has( 7, EBX, 11, ctxt, ops) + +#define vcpu_must_have(feat) \ + generate_exception_if(!vcpu_has_##feat(), EXC_UD) #ifdef __XEN__ /* - * Note the difference between vcpu_must_have_() and + * Note the difference between vcpu_must_have() and * host_and_vcpu_must_have(): The latter needs to be used when * emulation code is using the same instruction class for carrying out * the actual operation. */ #define host_and_vcpu_must_have(feat) ({ \ generate_exception_if(!cpu_has_##feat, EXC_UD); \ - vcpu_must_have_##feat(); \ + vcpu_must_have(feat); \ }) #else -#define host_and_vcpu_must_have(feat) vcpu_must_have_##feat() +#define host_and_vcpu_must_have(feat) vcpu_must_have(feat) #endif static int @@ -3651,7 +3651,7 @@ x86_emulate( case 0xc8 ... 0xcf: /* fcmove %stN */ case 0xd0 ... 0xd7: /* fcmovbe %stN */ case 0xd8 ... 0xdf: /* fcmovu %stN */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); emulate_fpu_insn_stub_eflags(0xda, modrm); break; case 0xe9: /* fucompp */ @@ -3704,7 +3704,7 @@ x86_emulate( case 0xd8 ... 0xdf: /* fcmovnu %stN */ case 0xe8 ... 0xef: /* fucomi %stN */ case 0xf0 ... 0xf7: /* fcomi %stN */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); emulate_fpu_insn_stub_eflags(0xdb, modrm); break; case 0xe0: /* fneni - 8087 only, ignored by 287 */ @@ -3927,7 +3927,7 @@ x86_emulate( break; case 0xe8 ... 0xef: /* fucomip %stN */ case 0xf0 ... 0xf7: /* fcomip %stN */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); emulate_fpu_insn_stub_eflags(0xdf, modrm); break; case 0xc0 ... 0xc7: /* ffreep %stN */ @@ -4824,7 +4824,7 @@ x86_emulate( } case X86EMUL_OPC(0x0f, 0x40) ... X86EMUL_OPC(0x0f, 0x4f): /* cmovcc */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); if ( test_cc(b, _regs.eflags) ) dst.val = src.val; break; @@ -5280,7 +5280,7 @@ x86_emulate( case X86EMUL_OPC(0x0f, 0xc3): /* movnti */ /* Ignore the non-temporal hint for now. */ - vcpu_must_have_sse2(); + vcpu_must_have(sse2); generate_exception_if(dst.bytes <= 2, EXC_UD); dst.val = src.val; break; @@ -5352,7 +5352,7 @@ x86_emulate( case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */ case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */ - vcpu_must_have_movbe(); + vcpu_must_have(movbe); switch ( op_bytes ) { case 2: Reviewed-by: Andrew Cooper --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1260,39 +1260,39 @@ static bool vcpu_has( return rc == X86EMUL_OKAY; } -#define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) -#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) -#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) -#define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops) -#define vcpu_has_hle() vcpu_has(0x00000007, EBX, 4, ctxt, ops) -#define vcpu_has_rtm() vcpu_has(0x00000007, EBX, 11, ctxt, ops) - -#define vcpu_must_have(leaf, reg, bit) \ - generate_exception_if(!vcpu_has(leaf, reg, bit, ctxt, ops), EXC_UD) -#define vcpu_must_have_fpu() vcpu_must_have(0x00000001, EDX, 0) -#define vcpu_must_have_cmov() vcpu_must_have(0x00000001, EDX, 15) -#define vcpu_must_have_mmx() vcpu_must_have(0x00000001, EDX, 23) -#define vcpu_must_have_sse() vcpu_must_have(0x00000001, EDX, 25) -#define vcpu_must_have_sse2() vcpu_must_have(0x00000001, EDX, 26) -#define vcpu_must_have_sse3() vcpu_must_have(0x00000001, ECX, 0) -#define vcpu_must_have_cx16() vcpu_must_have(0x00000001, ECX, 13) -#define vcpu_must_have_sse4_2() vcpu_must_have(0x00000001, ECX, 20) -#define vcpu_must_have_movbe() vcpu_must_have(0x00000001, ECX, 22) -#define vcpu_must_have_avx() vcpu_must_have(0x00000001, ECX, 28) +#define vcpu_has_fpu() vcpu_has( 1, EDX, 0, ctxt, ops) +#define vcpu_has_cmov() vcpu_has( 1, EDX, 15, ctxt, ops) +#define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops) +#define vcpu_has_mmx() vcpu_has( 1, EDX, 23, ctxt, ops) +#define vcpu_has_sse() vcpu_has( 1, EDX, 25, ctxt, ops) +#define vcpu_has_sse2() vcpu_has( 1, EDX, 26, ctxt, ops) +#define vcpu_has_sse3() vcpu_has( 1, ECX, 0, ctxt, ops) +#define vcpu_has_cx16() vcpu_has( 1, ECX, 13, ctxt, ops) +#define vcpu_has_sse4_2() vcpu_has( 1, ECX, 20, ctxt, ops) +#define vcpu_has_movbe() vcpu_has( 1, ECX, 22, ctxt, ops) +#define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops) +#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) +#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops) +#define vcpu_has_bmi1() vcpu_has( 7, EBX, 3, ctxt, ops) +#define vcpu_has_hle() vcpu_has( 7, EBX, 4, ctxt, ops) +#define vcpu_has_rtm() vcpu_has( 7, EBX, 11, ctxt, ops) + +#define vcpu_must_have(feat) \ + generate_exception_if(!vcpu_has_##feat(), EXC_UD) #ifdef __XEN__ /* - * Note the difference between vcpu_must_have_() and + * Note the difference between vcpu_must_have() and * host_and_vcpu_must_have(): The latter needs to be used when * emulation code is using the same instruction class for carrying out * the actual operation. */ #define host_and_vcpu_must_have(feat) ({ \ generate_exception_if(!cpu_has_##feat, EXC_UD); \ - vcpu_must_have_##feat(); \ + vcpu_must_have(feat); \ }) #else -#define host_and_vcpu_must_have(feat) vcpu_must_have_##feat() +#define host_and_vcpu_must_have(feat) vcpu_must_have(feat) #endif static int @@ -3651,7 +3651,7 @@ x86_emulate( case 0xc8 ... 0xcf: /* fcmove %stN */ case 0xd0 ... 0xd7: /* fcmovbe %stN */ case 0xd8 ... 0xdf: /* fcmovu %stN */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); emulate_fpu_insn_stub_eflags(0xda, modrm); break; case 0xe9: /* fucompp */ @@ -3704,7 +3704,7 @@ x86_emulate( case 0xd8 ... 0xdf: /* fcmovnu %stN */ case 0xe8 ... 0xef: /* fucomi %stN */ case 0xf0 ... 0xf7: /* fcomi %stN */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); emulate_fpu_insn_stub_eflags(0xdb, modrm); break; case 0xe0: /* fneni - 8087 only, ignored by 287 */ @@ -3927,7 +3927,7 @@ x86_emulate( break; case 0xe8 ... 0xef: /* fucomip %stN */ case 0xf0 ... 0xf7: /* fcomip %stN */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); emulate_fpu_insn_stub_eflags(0xdf, modrm); break; case 0xc0 ... 0xc7: /* ffreep %stN */ @@ -4824,7 +4824,7 @@ x86_emulate( } case X86EMUL_OPC(0x0f, 0x40) ... X86EMUL_OPC(0x0f, 0x4f): /* cmovcc */ - vcpu_must_have_cmov(); + vcpu_must_have(cmov); if ( test_cc(b, _regs.eflags) ) dst.val = src.val; break; @@ -5280,7 +5280,7 @@ x86_emulate( case X86EMUL_OPC(0x0f, 0xc3): /* movnti */ /* Ignore the non-temporal hint for now. */ - vcpu_must_have_sse2(); + vcpu_must_have(sse2); generate_exception_if(dst.bytes <= 2, EXC_UD); dst.val = src.val; break; @@ -5352,7 +5352,7 @@ x86_emulate( case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */ case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */ - vcpu_must_have_movbe(); + vcpu_must_have(movbe); switch ( op_bytes ) { case 2: