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[6/6] x86emul: check for LAHF_LM availability

Message ID 58500E9702000078001289FC@prv-mh.provo.novell.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jan Beulich Dec. 13, 2016, 2:07 p.m. UTC 
We can't exclude someone wanting to hide LAHF/SAHF from 64-bit guests.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
x86emul: check for LAHF_LM availability

We can't exclude someone wanting to hide LAHF/SAHF from 64-bit guests.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1291,6 +1291,7 @@ static bool vcpu_has(
 #define vcpu_has_sse4_2()      vcpu_has(         1, ECX, 20, ctxt, ops)
 #define vcpu_has_movbe()       vcpu_has(         1, ECX, 22, ctxt, ops)
 #define vcpu_has_avx()         vcpu_has(         1, ECX, 28, ctxt, ops)
+#define vcpu_has_lahf_lm()     vcpu_has(0x80000001, ECX,  0, ctxt, ops)
 #define vcpu_has_lzcnt()       vcpu_has(0x80000001, ECX,  5, ctxt, ops)
 #define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX,  7, ctxt, ops)
 #define vcpu_has_bmi1()        vcpu_has(         7, EBX,  3, ctxt, ops)
@@ -3201,11 +3202,15 @@ x86_emulate(
     }
 
     case 0x9e: /* sahf */
+        if ( mode_64bit() )
+            vcpu_must_have(lahf_lm);
         *(uint8_t *)&_regs.eflags = (((uint8_t *)&_regs.eax)[1] &
                                      EFLAGS_MASK) | EFLG_MBS;
         break;
 
     case 0x9f: /* lahf */
+        if ( mode_64bit() )
+            vcpu_must_have(lahf_lm);
         ((uint8_t *)&_regs.eax)[1] = (_regs.eflags & EFLAGS_MASK) | EFLG_MBS;
         break;

Comments

Andrew Cooper Dec. 13, 2016, 2:28 p.m. UTC | #1 
On 13/12/16 14:07, Jan Beulich wrote:
> We can't exclude someone wanting to hide LAHF/SAHF from 64-bit guests.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
diff mbox

Patch

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1291,6 +1291,7 @@  static bool vcpu_has(
 #define vcpu_has_sse4_2()      vcpu_has(         1, ECX, 20, ctxt, ops)
 #define vcpu_has_movbe()       vcpu_has(         1, ECX, 22, ctxt, ops)
 #define vcpu_has_avx()         vcpu_has(         1, ECX, 28, ctxt, ops)
+#define vcpu_has_lahf_lm()     vcpu_has(0x80000001, ECX,  0, ctxt, ops)
 #define vcpu_has_lzcnt()       vcpu_has(0x80000001, ECX,  5, ctxt, ops)
 #define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX,  7, ctxt, ops)
 #define vcpu_has_bmi1()        vcpu_has(         7, EBX,  3, ctxt, ops)
@@ -3201,11 +3202,15 @@  x86_emulate(
     }
 
     case 0x9e: /* sahf */
+        if ( mode_64bit() )
+            vcpu_must_have(lahf_lm);
         *(uint8_t *)&_regs.eflags = (((uint8_t *)&_regs.eax)[1] &
                                      EFLAGS_MASK) | EFLG_MBS;
         break;
 
     case 0x9f: /* lahf */
+        if ( mode_64bit() )
+            vcpu_must_have(lahf_lm);
         ((uint8_t *)&_regs.eax)[1] = (_regs.eflags & EFLAGS_MASK) | EFLG_MBS;
         break;