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x86emul: support fencing insns

Message ID 585120EA020000780012902C@prv-mh.provo.novell.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jan Beulich Dec. 14, 2016, 9:37 a.m. UTC 
Signed-off-by: Jan Beulich <jbeulich@suse.com>
x86emul: support fencing insns

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -5190,8 +5190,26 @@ x86_emulate(
     case X86EMUL_OPC(0x0f, 0xae): case X86EMUL_OPC_66(0x0f, 0xae): /* Grp15 */
         switch ( modrm_reg & 7 )
         {
-        case 7: /* clflush{,opt} */
-            fail_if(modrm_mod == 3);
+        case 5: /* lfence */
+            fail_if(modrm_mod != 3);
+            generate_exception_if(vex.pfx, EXC_UD);
+            vcpu_must_have(sse2);
+            asm volatile ( "lfence" ::: "memory" );
+            break;
+        case 6: /* mfence */
+            fail_if(modrm_mod != 3);
+            generate_exception_if(vex.pfx, EXC_UD);
+            vcpu_must_have(sse2);
+            asm volatile ( "mfence" ::: "memory" );
+            break;
+        case 7: /* clflush{,opt} / sfence */
+            if ( modrm_mod == 3 )
+            {
+                generate_exception_if(vex.pfx, EXC_UD);
+                vcpu_must_have(sse);
+                asm volatile ( "sfence" ::: "memory" );
+                break;
+            }
             if ( !vex.pfx )
                 vcpu_must_have(clflush);
             else

Comments

Andrew Cooper Jan. 5, 2017, 7:26 p.m. UTC | #1 
On 14/12/16 09:37, Jan Beulich wrote:
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -5190,8 +5190,26 @@ x86_emulate(
>      case X86EMUL_OPC(0x0f, 0xae): case X86EMUL_OPC_66(0x0f, 0xae): /* Grp15 */
>          switch ( modrm_reg & 7 )
>          {
> -        case 7: /* clflush{,opt} */
> -            fail_if(modrm_mod == 3);
> +        case 5: /* lfence */
> +            fail_if(modrm_mod != 3);
> +            generate_exception_if(vex.pfx, EXC_UD);
> +            vcpu_must_have(sse2);
> +            asm volatile ( "lfence" ::: "memory" );
> +            break;
> +        case 6: /* mfence */
> +            fail_if(modrm_mod != 3);
> +            generate_exception_if(vex.pfx, EXC_UD);
> +            vcpu_must_have(sse2);
> +            asm volatile ( "mfence" ::: "memory" );
> +            break;
> +        case 7: /* clflush{,opt} / sfence */
> +            if ( modrm_mod == 3 )

Could I talk you into having

if ( modrm_mod == 3 ) /* sfence */

and

> +            {
> +                generate_exception_if(vex.pfx, EXC_UD);
> +                vcpu_must_have(sse);
> +                asm volatile ( "sfence" ::: "memory" );
> +                break;
> +            }

/* else clflush{,opt} */ ?

Even knowing what is going on, this is a little hard to follow.

Otherwise, Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

>              if ( !vex.pfx )
>                  vcpu_must_have(clflush);
>              else
>
>
>
Jan Beulich Jan. 6, 2017, 1:37 p.m. UTC | #2 
>>> On 05.01.17 at 20:26, <andrew.cooper3@citrix.com> wrote:
> On 14/12/16 09:37, Jan Beulich wrote:
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>
>> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
>> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
>> @@ -5190,8 +5190,26 @@ x86_emulate(
>>      case X86EMUL_OPC(0x0f, 0xae): case X86EMUL_OPC_66(0x0f, 0xae): /* Grp15 
> */
>>          switch ( modrm_reg & 7 )
>>          {
>> -        case 7: /* clflush{,opt} */
>> -            fail_if(modrm_mod == 3);
>> +        case 5: /* lfence */
>> +            fail_if(modrm_mod != 3);
>> +            generate_exception_if(vex.pfx, EXC_UD);
>> +            vcpu_must_have(sse2);
>> +            asm volatile ( "lfence" ::: "memory" );
>> +            break;
>> +        case 6: /* mfence */
>> +            fail_if(modrm_mod != 3);
>> +            generate_exception_if(vex.pfx, EXC_UD);
>> +            vcpu_must_have(sse2);
>> +            asm volatile ( "mfence" ::: "memory" );
>> +            break;
>> +        case 7: /* clflush{,opt} / sfence */
>> +            if ( modrm_mod == 3 )
> 
> Could I talk you into having
> 
> if ( modrm_mod == 3 ) /* sfence */
> 
> and
> 
>> +            {
>> +                generate_exception_if(vex.pfx, EXC_UD);
>> +                vcpu_must_have(sse);
>> +                asm volatile ( "sfence" ::: "memory" );
>> +                break;
>> +            }
> 
> /* else clflush{,opt} */ ?
> 
> Even knowing what is going on, this is a little hard to follow.

No problem.

> Otherwise, Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

Thanks.

Jan
diff mbox

Patch

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -5190,8 +5190,26 @@  x86_emulate(
     case X86EMUL_OPC(0x0f, 0xae): case X86EMUL_OPC_66(0x0f, 0xae): /* Grp15 */
         switch ( modrm_reg & 7 )
         {
-        case 7: /* clflush{,opt} */
-            fail_if(modrm_mod == 3);
+        case 5: /* lfence */
+            fail_if(modrm_mod != 3);
+            generate_exception_if(vex.pfx, EXC_UD);
+            vcpu_must_have(sse2);
+            asm volatile ( "lfence" ::: "memory" );
+            break;
+        case 6: /* mfence */
+            fail_if(modrm_mod != 3);
+            generate_exception_if(vex.pfx, EXC_UD);
+            vcpu_must_have(sse2);
+            asm volatile ( "mfence" ::: "memory" );
+            break;
+        case 7: /* clflush{,opt} / sfence */
+            if ( modrm_mod == 3 )
+            {
+                generate_exception_if(vex.pfx, EXC_UD);
+                vcpu_must_have(sse);
+                asm volatile ( "sfence" ::: "memory" );
+                break;
+            }
             if ( !vex.pfx )
                 vcpu_must_have(clflush);
             else