From patchwork Tue Dec 20 10:42:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9481423 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7448A600CA for ; Tue, 20 Dec 2016 10:44:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 733D328161 for ; Tue, 20 Dec 2016 10:44:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 682F6283A6; Tue, 20 Dec 2016 10:44:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B55B728161 for ; Tue, 20 Dec 2016 10:44:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cJHsP-0001mL-T3; Tue, 20 Dec 2016 10:42:33 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cJHsP-0001lz-HB for xen-devel@lists.xenproject.org; Tue, 20 Dec 2016 10:42:33 +0000 Received: from [85.158.143.35] by server-11.bemta-6.messagelabs.com id 78/F2-25337-81B09585; Tue, 20 Dec 2016 10:42:32 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRWlGSWpSXmKPExsXS6fjDS1eCOzL CoHUJj8X3LZOZHBg9Dn+4whLAGMWamZeUX5HAmrG88T1TwQqLiq7dNg2M9wy6GDk4hATyJJ6v D+1i5OTgFbCTWNj7kBHElhAwlHj6/jobiM0ioCrR9PIGWJxNQF2i7dl2VpBWEQEDiXNHk7oYu TiYBZYySnTsnsEOUiMs4Cyx5vg6FhBbCGjm4fu3mUDqOQXsJdrvgm3lFRCU+LtDGKSCGahiz4 a5TBMYeWYhZGYhyUDYWhIPf91igbC1JZYtfM0MUs4sIC2x/B8HRNhS4sKhb2yoSkBsF4llP2Y wLWDkWMWoUZxaVJZapGtsrJdUlJmeUZKbmJmja2hgppebWlycmJ6ak5hUrJecn7uJERioDECw g3Hn+sBDjJIcTEqivPt5IiKE+JLyUyozEosz4otKc1KLDzFqcHAIbNu1+gKjFEtefl6qkgTvZ c7ICCHBotT01Iq0zBxgLMGUSnDwKInwngVJ8xYXJOYWZ6ZDpE4x6nJMe7b4KZMQ2Awpcd4akC IBkKKM0jy4EbC4vsQoKyXMywh0oBBPQWpRbmYJqvwrRnEORiVhXmEuoCk8mXklcJteAR3BBHT Ewu5wkCNKEhFSUg2MV6p+693qFTBYsmnzvUe5rXmq14q/5rQ8k3jHKnKPbcLOr5Ou8fIwxfRk tDsasb1/Vn9rQxNvfshXg/+HxLwuGyZxbNju6Pbu4OZ3E5hv761d4jHB5cA6Nb0Nmz08mZPlv 8zqV5wp9jS0g9HpIXt9QOvqyoJ2z3XPxZIYFhTf/Vy8hSWy5quvEktxRqKhFnNRcSIAMvCQWe YCAAA= X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-5.tower-21.messagelabs.com!1482230550!41177171!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6346 invoked from network); 20 Dec 2016 10:42:31 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-5.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 20 Dec 2016 10:42:31 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Tue, 20 Dec 2016 03:42:20 -0700 Message-Id: <5859191B020000780012AE08@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Tue, 20 Dec 2016 03:42:19 -0700 From: "Jan Beulich" To: "xen-devel" References: <58590E27020000780012AD5E@prv-mh.provo.novell.com> In-Reply-To: <58590E27020000780012AD5E@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: George Dunlap , Andrew Cooper , tamas@tklengyel.com, Razvan Cojocaru Subject: [Xen-devel] [PATCH 08/10] x86/vm-event: use unambiguous register names X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This is in preparation of eliminating the mis-naming of 64-bit fields with 32-bit register names (eflags instead of rflags etc). Signed-off-by: Jan Beulich x86/vm-event: use unambiguous register names This is in preparation of eliminating the mis-naming of 64-bit fields with 32-bit register names (eflags instead of rflags etc). Signed-off-by: Jan Beulich --- a/xen/arch/x86/vm_event.c +++ b/xen/arch/x86/vm_event.c @@ -112,14 +112,14 @@ void vm_event_set_registers(struct vcpu { ASSERT(atomic_read(&v->vm_event_pause_count)); - v->arch.user_regs.eax = rsp->data.regs.x86.rax; - v->arch.user_regs.ebx = rsp->data.regs.x86.rbx; - v->arch.user_regs.ecx = rsp->data.regs.x86.rcx; - v->arch.user_regs.edx = rsp->data.regs.x86.rdx; - v->arch.user_regs.esp = rsp->data.regs.x86.rsp; - v->arch.user_regs.ebp = rsp->data.regs.x86.rbp; - v->arch.user_regs.esi = rsp->data.regs.x86.rsi; - v->arch.user_regs.edi = rsp->data.regs.x86.rdi; + v->arch.user_regs.rax = rsp->data.regs.x86.rax; + v->arch.user_regs.rbx = rsp->data.regs.x86.rbx; + v->arch.user_regs.rcx = rsp->data.regs.x86.rcx; + v->arch.user_regs.rdx = rsp->data.regs.x86.rdx; + v->arch.user_regs.rsp = rsp->data.regs.x86.rsp; + v->arch.user_regs.rbp = rsp->data.regs.x86.rbp; + v->arch.user_regs.rsi = rsp->data.regs.x86.rsi; + v->arch.user_regs.rdi = rsp->data.regs.x86.rdi; v->arch.user_regs.r8 = rsp->data.regs.x86.r8; v->arch.user_regs.r9 = rsp->data.regs.x86.r9; @@ -130,8 +130,8 @@ void vm_event_set_registers(struct vcpu v->arch.user_regs.r14 = rsp->data.regs.x86.r14; v->arch.user_regs.r15 = rsp->data.regs.x86.r15; - v->arch.user_regs.eflags = rsp->data.regs.x86.rflags; - v->arch.user_regs.eip = rsp->data.regs.x86.rip; + v->arch.user_regs.rflags = rsp->data.regs.x86.rflags; + v->arch.user_regs.rip = rsp->data.regs.x86.rip; } void vm_event_monitor_next_interrupt(struct vcpu *v) @@ -151,14 +151,14 @@ void vm_event_fill_regs(vm_event_request /* Architecture-specific vmcs/vmcb bits */ hvm_funcs.save_cpu_ctxt(curr, &ctxt); - req->data.regs.x86.rax = regs->eax; - req->data.regs.x86.rcx = regs->ecx; - req->data.regs.x86.rdx = regs->edx; - req->data.regs.x86.rbx = regs->ebx; - req->data.regs.x86.rsp = regs->esp; - req->data.regs.x86.rbp = regs->ebp; - req->data.regs.x86.rsi = regs->esi; - req->data.regs.x86.rdi = regs->edi; + req->data.regs.x86.rax = regs->rax; + req->data.regs.x86.rcx = regs->rcx; + req->data.regs.x86.rdx = regs->rdx; + req->data.regs.x86.rbx = regs->rbx; + req->data.regs.x86.rsp = regs->rsp; + req->data.regs.x86.rbp = regs->rbp; + req->data.regs.x86.rsi = regs->rsi; + req->data.regs.x86.rdi = regs->rdi; req->data.regs.x86.r8 = regs->r8; req->data.regs.x86.r9 = regs->r9; @@ -169,8 +169,8 @@ void vm_event_fill_regs(vm_event_request req->data.regs.x86.r14 = regs->r14; req->data.regs.x86.r15 = regs->r15; - req->data.regs.x86.rflags = regs->eflags; - req->data.regs.x86.rip = regs->eip; + req->data.regs.x86.rflags = regs->rflags; + req->data.regs.x86.rip = regs->rip; req->data.regs.x86.dr7 = curr->arch.debugreg[7]; req->data.regs.x86.cr0 = ctxt.cr0; Acked-by: Razvan Cojocaru --- a/xen/arch/x86/vm_event.c +++ b/xen/arch/x86/vm_event.c @@ -112,14 +112,14 @@ void vm_event_set_registers(struct vcpu { ASSERT(atomic_read(&v->vm_event_pause_count)); - v->arch.user_regs.eax = rsp->data.regs.x86.rax; - v->arch.user_regs.ebx = rsp->data.regs.x86.rbx; - v->arch.user_regs.ecx = rsp->data.regs.x86.rcx; - v->arch.user_regs.edx = rsp->data.regs.x86.rdx; - v->arch.user_regs.esp = rsp->data.regs.x86.rsp; - v->arch.user_regs.ebp = rsp->data.regs.x86.rbp; - v->arch.user_regs.esi = rsp->data.regs.x86.rsi; - v->arch.user_regs.edi = rsp->data.regs.x86.rdi; + v->arch.user_regs.rax = rsp->data.regs.x86.rax; + v->arch.user_regs.rbx = rsp->data.regs.x86.rbx; + v->arch.user_regs.rcx = rsp->data.regs.x86.rcx; + v->arch.user_regs.rdx = rsp->data.regs.x86.rdx; + v->arch.user_regs.rsp = rsp->data.regs.x86.rsp; + v->arch.user_regs.rbp = rsp->data.regs.x86.rbp; + v->arch.user_regs.rsi = rsp->data.regs.x86.rsi; + v->arch.user_regs.rdi = rsp->data.regs.x86.rdi; v->arch.user_regs.r8 = rsp->data.regs.x86.r8; v->arch.user_regs.r9 = rsp->data.regs.x86.r9; @@ -130,8 +130,8 @@ void vm_event_set_registers(struct vcpu v->arch.user_regs.r14 = rsp->data.regs.x86.r14; v->arch.user_regs.r15 = rsp->data.regs.x86.r15; - v->arch.user_regs.eflags = rsp->data.regs.x86.rflags; - v->arch.user_regs.eip = rsp->data.regs.x86.rip; + v->arch.user_regs.rflags = rsp->data.regs.x86.rflags; + v->arch.user_regs.rip = rsp->data.regs.x86.rip; } void vm_event_monitor_next_interrupt(struct vcpu *v) @@ -151,14 +151,14 @@ void vm_event_fill_regs(vm_event_request /* Architecture-specific vmcs/vmcb bits */ hvm_funcs.save_cpu_ctxt(curr, &ctxt); - req->data.regs.x86.rax = regs->eax; - req->data.regs.x86.rcx = regs->ecx; - req->data.regs.x86.rdx = regs->edx; - req->data.regs.x86.rbx = regs->ebx; - req->data.regs.x86.rsp = regs->esp; - req->data.regs.x86.rbp = regs->ebp; - req->data.regs.x86.rsi = regs->esi; - req->data.regs.x86.rdi = regs->edi; + req->data.regs.x86.rax = regs->rax; + req->data.regs.x86.rcx = regs->rcx; + req->data.regs.x86.rdx = regs->rdx; + req->data.regs.x86.rbx = regs->rbx; + req->data.regs.x86.rsp = regs->rsp; + req->data.regs.x86.rbp = regs->rbp; + req->data.regs.x86.rsi = regs->rsi; + req->data.regs.x86.rdi = regs->rdi; req->data.regs.x86.r8 = regs->r8; req->data.regs.x86.r9 = regs->r9; @@ -169,8 +169,8 @@ void vm_event_fill_regs(vm_event_request req->data.regs.x86.r14 = regs->r14; req->data.regs.x86.r15 = regs->r15; - req->data.regs.x86.rflags = regs->eflags; - req->data.regs.x86.rip = regs->eip; + req->data.regs.x86.rflags = regs->rflags; + req->data.regs.x86.rip = regs->rip; req->data.regs.x86.dr7 = curr->arch.debugreg[7]; req->data.regs.x86.cr0 = ctxt.cr0;