From patchwork Thu Jan 5 15:12:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9499167 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D1BA0606DE for ; Thu, 5 Jan 2017 15:14:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8B3926B39 for ; Thu, 5 Jan 2017 15:14:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD98B28401; Thu, 5 Jan 2017 15:14:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 37A9626B39 for ; Thu, 5 Jan 2017 15:14:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cP9iZ-0008NM-Sv; Thu, 05 Jan 2017 15:12:39 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cP9iY-0008NF-94 for xen-devel@lists.xenproject.org; Thu, 05 Jan 2017 15:12:38 +0000 Received: from [85.158.139.211] by server-1.bemta-5.messagelabs.com id D6/76-12836-5626E685; Thu, 05 Jan 2017 15:12:37 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLIsWRWlGSWpSXmKPExsXS6fjDSzclKS/ CYGKnqcX3LZOZHBg9Dn+4whLAGMWamZeUX5HAmnFy+3+mgt/aFR3bl7A1MC5X7GLk5BASyJOY vHg1I4jNK2AnsfP9OlYQW0LAUOLp++tsXYwcHCwCqhJd3wVBwmwC6hJtz7azgoRFBAwkzh1NA jGZBfQltq1jAakQFtCVWHFkChNImFdAUOLvDmGQMDPQ7PVP/zFNYOSahZCZhSQDYWtJPPx1iw XC1pZYtvA18yyw+dISy/9xQIStJL5v+c+OqcRV4vj+/AWMHKsY1YtTi8pSi3RN9ZKKMtMzSnI TM3N0DQ1M9XJTi4sT01NzEpOK9ZLzczcxAoOOAQh2MH7pdz7EKMnBpCTKa/0tN0KILyk/pTIj sTgjvqg0J7X4EKMMB4eSBC9fYl6EkGBRanpqRVpmDjD8YdISHDxKIrwxIGne4oLE3OLMdIjUK UZdjmnPFj9lEmLJy89LlRLnfZ4AVCQAUpRRmgc3AhaLlxhlpYR5GYGOEuIpSC3KzSxBlX/FKM 7BqCTMqw2yiiczrwRu0yugI5iAjtgekA1yREkiQkqqgTG7alHI0j0cCkWrb+V4PUlYterH4SO GqmZ9R+bP2bz96/yWLQ/OH4oOXj9vy/Q12pmyEzTPh/+2LwpiLAtjc5BMnXBQy9CYIT09Trpf 5PW2FjmjC5+7FJoWNcpapjd1fEq0eymf8VmhMbku/d5nSasvIgcSzkzy881X+xl0R+KQY+6UZ +8bniixFGckGmoxFxUnAgBOYg/xwAIAAA== X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-2.tower-206.messagelabs.com!1483629154!57891682!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7610 invoked from network); 5 Jan 2017 15:12:36 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-2.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 5 Jan 2017 15:12:36 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Thu, 05 Jan 2017 08:12:34 -0700 Message-Id: <586E7072020000780012D7AC@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Thu, 05 Jan 2017 08:12:34 -0700 From: "Jan Beulich" To: "xen-devel" Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH v2] x86: drop cpu_has_sse{,2} X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Commit dc88221c97 ("x86: rename XMM* features to SSE*") pointlessly added them - these features are always available on 64-bit CPUs. (Let's not assume this for MMX though in at least the insn emulator.) Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- v2: Add a test harness comment clarifying host_and_vcpu_must_have() vs vcpu_must_have() use there. x86: drop cpu_has_sse{,2} Commit dc88221c97 ("x86: rename XMM* features to SSE*") pointlessly added them - these features are always available on 64-bit CPUs. (Let's not assume this for MMX though in at least the insn emulator.) Signed-off-by: Jan Beulich --- v2: Add a test harness comment clarifying host_and_vcpu_must_have() vs vcpu_must_have() use there. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1326,6 +1326,11 @@ static bool vcpu_has( vcpu_must_have(feat); \ }) #else +/* + * For the test harness both are fine to be used interchangeably, i.e. + * features known to always be available (e.g. SSE/SSE2) to (64-bit) Xen + * may be checked for by just vcpu_must_have(). + */ #define host_and_vcpu_must_have(feat) vcpu_must_have(feat) #endif @@ -4910,9 +4915,9 @@ x86_emulate( if ( vex.opcx == vex_none ) { if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK ) - host_and_vcpu_must_have(sse2); + vcpu_must_have(sse2); else - host_and_vcpu_must_have(sse); + vcpu_must_have(sse); ea.bytes = 16; SET_SSE_PREFIX(buf[0], vex.pfx); get_fpu(X86EMUL_FPU_xmm, &fic); @@ -5183,7 +5188,7 @@ x86_emulate( { case vex_66: case vex_f3: - host_and_vcpu_must_have(sse2); + vcpu_must_have(sse2); /* Converting movdqu to movdqa here: Our buffer is aligned. */ buf[0] = 0x66; get_fpu(X86EMUL_FPU_xmm, &fic); @@ -5193,7 +5198,7 @@ x86_emulate( if ( b != 0xe7 ) host_and_vcpu_must_have(mmx); else - host_and_vcpu_must_have(sse); + vcpu_must_have(sse); get_fpu(X86EMUL_FPU_mmx, &fic); ea.bytes = 8; break; --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -38,8 +38,6 @@ #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) #define cpu_has_mtrr 1 #define cpu_has_mmx 1 -#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE) -#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2) #define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3) #define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2) #define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1326,6 +1326,11 @@ static bool vcpu_has( vcpu_must_have(feat); \ }) #else +/* + * For the test harness both are fine to be used interchangeably, i.e. + * features known to always be available (e.g. SSE/SSE2) to (64-bit) Xen + * may be checked for by just vcpu_must_have(). + */ #define host_and_vcpu_must_have(feat) vcpu_must_have(feat) #endif @@ -4910,9 +4915,9 @@ x86_emulate( if ( vex.opcx == vex_none ) { if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK ) - host_and_vcpu_must_have(sse2); + vcpu_must_have(sse2); else - host_and_vcpu_must_have(sse); + vcpu_must_have(sse); ea.bytes = 16; SET_SSE_PREFIX(buf[0], vex.pfx); get_fpu(X86EMUL_FPU_xmm, &fic); @@ -5183,7 +5188,7 @@ x86_emulate( { case vex_66: case vex_f3: - host_and_vcpu_must_have(sse2); + vcpu_must_have(sse2); /* Converting movdqu to movdqa here: Our buffer is aligned. */ buf[0] = 0x66; get_fpu(X86EMUL_FPU_xmm, &fic); @@ -5193,7 +5198,7 @@ x86_emulate( if ( b != 0xe7 ) host_and_vcpu_must_have(mmx); else - host_and_vcpu_must_have(sse); + vcpu_must_have(sse); get_fpu(X86EMUL_FPU_mmx, &fic); ea.bytes = 8; break; --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -38,8 +38,6 @@ #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) #define cpu_has_mtrr 1 #define cpu_has_mmx 1 -#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE) -#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2) #define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3) #define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2) #define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT)