From patchwork Tue Feb 28 12:54:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9595435 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BAB0360429 for ; Tue, 28 Feb 2017 12:56:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA9F6280FC for ; Tue, 28 Feb 2017 12:56:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9F81228518; Tue, 28 Feb 2017 12:56:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3EE9F280FC for ; Tue, 28 Feb 2017 12:56:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cihId-00009q-7N; Tue, 28 Feb 2017 12:54:39 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cihIb-00009J-IV for xen-devel@lists.xenproject.org; Tue, 28 Feb 2017 12:54:37 +0000 Received: from [85.158.139.211] by server-11.bemta-5.messagelabs.com id 2F/46-01711-C0375B85; Tue, 28 Feb 2017 12:54:36 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRWlGSWpSXmKPExsXS6fjDS5eneGu EwflTrBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8anw9vYCnboV+zYMp2pgXG+YhcjJ4eQQJ5E U/NWFhCbV8BO4vH0P2wgtoSAocTT99fBbBYBVYnjfa+YQWw2AXWJtmfbWbsYOThEBAwkzh1NA jGZBfQltq0DmyIsYCPxZulndojpdhKf5r1hBLE5BewlVrVcYgIp5xUQlPi7Qxii005iybGiCY w8sxASsxASs4BamQW0JB7+usUCYWtLLFv4mhmiRFpi+T8OiLCpxKcfz5lQlYDYDhKr9zxkXcD IsYpRvTi1qCy1SNdCL6koMz2jJDcxM0fX0MBULze1uDgxPTUnMalYLzk/dxMjMEgZgGAH48Fm 50OMkhxMSqK8WclbI4T4kvJTKjMSizPii0pzUosPMcpwcChJ8OoUAeUEi1LTUyvSMnOA8QKTl uDgURLhPVoIlOYtLkjMLc5Mh0idYlSUEueVB+kTAElklObBtcFi9BKjrJQwLyPQIUI8BalFuZ klqPKvGMU5GJWEeZ+BjOfJzCuBm/4KaDET0OIXKmCLSxIRUlINjK43VLLEP9xZsPqs03Qu4bQ 3zpk1y+O9le8cUfkoW1TcvW/mlG+aHqee6S3eFhp1Jqfz0u6qB8tiVzE/+PFfJzIvwXXeJSvr AyHm6xM756efCdjyN3+Cx6TQNBtWm8VNybcEqr+8eJjUIGBTu3c98/SKDbet/+4QtNwlMDss3 tDaPfSU0z6dNUosxRmJhlrMRcWJAN/UZjnMAgAA X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1488286473!73097068!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36669 invoked from network); 28 Feb 2017 12:54:35 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-15.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 28 Feb 2017 12:54:35 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Tue, 28 Feb 2017 05:54:33 -0700 Message-Id: <58B58115020000780013E2E5@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Tue, 28 Feb 2017 05:54:29 -0700 From: "Jan Beulich" To: "xen-devel" References: <58B57E43020000780013E26B@prv-mh.provo.novell.com> In-Reply-To: <58B57E43020000780013E26B@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH v4 09/17] x86emul: honor MMXEXT feature flag X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This being a strict (MMX register only) subset of SSE, we can simply adjust the respective checks while making the new predicate look at both flags. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper x86emul: honor MMXEXT feature flag This being a strict (MMX register only) subset of SSE, we can simply adjust the respective checks while making the new predicate look at both flags. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1405,6 +1405,8 @@ static bool vcpu_has( #define vcpu_has_popcnt() vcpu_has( 1, ECX, 23, ctxt, ops) #define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops) #define vcpu_has_rdrand() vcpu_has( 1, ECX, 30, ctxt, ops) +#define vcpu_has_mmxext() (vcpu_has(0x80000001, EDX, 22, ctxt, ops) || \ + vcpu_has_sse()) #define vcpu_has_lahf_lm() vcpu_has(0x80000001, ECX, 0, ctxt, ops) #define vcpu_has_cr8_legacy() vcpu_has(0x80000001, ECX, 4, ctxt, ops) #define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) @@ -5707,8 +5709,12 @@ x86_emulate( else { if ( b != 0x50 ) + { host_and_vcpu_must_have(mmx); - vcpu_must_have(sse); + vcpu_must_have(mmxext); + } + else + vcpu_must_have(sse); } if ( b == 0x50 || (vex.pfx & VEX_PREFIX_DOUBLE_MASK) ) get_fpu(X86EMUL_FPU_xmm, &fic); @@ -5966,7 +5972,7 @@ x86_emulate( else { host_and_vcpu_must_have(mmx); - vcpu_must_have(sse); + vcpu_must_have(mmxext); get_fpu(X86EMUL_FPU_mmx, &fic); } simd_0f_imm8: @@ -6252,7 +6258,7 @@ x86_emulate( if ( modrm_mod == 3 ) /* sfence */ { generate_exception_if(vex.pfx, EXC_UD); - vcpu_must_have(sse); + vcpu_must_have(mmxext); asm volatile ( "sfence" ::: "memory" ); break; } @@ -6736,7 +6742,7 @@ x86_emulate( case X86EMUL_OPC(0x0f, 0xe3): /* pavgw mm/m64,mm */ case X86EMUL_OPC(0x0f, 0xe4): /* pmulhuw mm/m64,mm */ case X86EMUL_OPC(0x0f, 0xf6): /* psadbw mm/m64,mm */ - vcpu_must_have(sse); + vcpu_must_have(mmxext); goto simd_0f_mmx; case X86EMUL_OPC_66(0x0f, 0xe6): /* cvttpd2dq xmm/mem,xmm */ @@ -6767,7 +6773,7 @@ x86_emulate( else { host_and_vcpu_must_have(mmx); - vcpu_must_have(sse); + vcpu_must_have(mmxext); get_fpu(X86EMUL_FPU_mmx, &fic); } --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1405,6 +1405,8 @@ static bool vcpu_has( #define vcpu_has_popcnt() vcpu_has( 1, ECX, 23, ctxt, ops) #define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops) #define vcpu_has_rdrand() vcpu_has( 1, ECX, 30, ctxt, ops) +#define vcpu_has_mmxext() (vcpu_has(0x80000001, EDX, 22, ctxt, ops) || \ + vcpu_has_sse()) #define vcpu_has_lahf_lm() vcpu_has(0x80000001, ECX, 0, ctxt, ops) #define vcpu_has_cr8_legacy() vcpu_has(0x80000001, ECX, 4, ctxt, ops) #define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) @@ -5707,8 +5709,12 @@ x86_emulate( else { if ( b != 0x50 ) + { host_and_vcpu_must_have(mmx); - vcpu_must_have(sse); + vcpu_must_have(mmxext); + } + else + vcpu_must_have(sse); } if ( b == 0x50 || (vex.pfx & VEX_PREFIX_DOUBLE_MASK) ) get_fpu(X86EMUL_FPU_xmm, &fic); @@ -5966,7 +5972,7 @@ x86_emulate( else { host_and_vcpu_must_have(mmx); - vcpu_must_have(sse); + vcpu_must_have(mmxext); get_fpu(X86EMUL_FPU_mmx, &fic); } simd_0f_imm8: @@ -6252,7 +6258,7 @@ x86_emulate( if ( modrm_mod == 3 ) /* sfence */ { generate_exception_if(vex.pfx, EXC_UD); - vcpu_must_have(sse); + vcpu_must_have(mmxext); asm volatile ( "sfence" ::: "memory" ); break; } @@ -6736,7 +6742,7 @@ x86_emulate( case X86EMUL_OPC(0x0f, 0xe3): /* pavgw mm/m64,mm */ case X86EMUL_OPC(0x0f, 0xe4): /* pmulhuw mm/m64,mm */ case X86EMUL_OPC(0x0f, 0xf6): /* psadbw mm/m64,mm */ - vcpu_must_have(sse); + vcpu_must_have(mmxext); goto simd_0f_mmx; case X86EMUL_OPC_66(0x0f, 0xe6): /* cvttpd2dq xmm/mem,xmm */ @@ -6767,7 +6773,7 @@ x86_emulate( else { host_and_vcpu_must_have(mmx); - vcpu_must_have(sse); + vcpu_must_have(mmxext); get_fpu(X86EMUL_FPU_mmx, &fic); }