From patchwork Tue Feb 28 12:58:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9595499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8BB2560429 for ; Tue, 28 Feb 2017 13:00:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 798D0284D4 for ; Tue, 28 Feb 2017 13:00:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B2CD284F9; Tue, 28 Feb 2017 13:00:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C7561284D4 for ; Tue, 28 Feb 2017 13:00:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cihMi-0001CJ-Lc; Tue, 28 Feb 2017 12:58:52 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cihMh-0001Bs-JQ for xen-devel@lists.xenproject.org; Tue, 28 Feb 2017 12:58:51 +0000 Received: from [193.109.254.147] by server-8.bemta-6.messagelabs.com id 7C/EC-21675-A0475B85; Tue, 28 Feb 2017 12:58:50 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRWlGSWpSXmKPExsXS6fjDS5ezZGu EwaVWMYvvWyYzOTB6HP5whSWAMYo1My8pvyKBNaNj4ROmgiXOFce2LmdrYFxg1sXIySEkkCfR uPsBI4jNK2AnMe3qLzBbQsBQ4un762wgNouAqsSh5/PZQWw2AXWJtmfbWbsYOThEBAwkzh1NA jGZBfQltq1jAakQFjCTmHrsGivEdDuJT/PegE3kFLCXWNVyiQmknFdAUOLvDmGQMDNQydQ9T5 gmMPLMQsjMQpKBsLUkHv66xQJha0ssW/iaeRbYXmmJ5f84IMJGEns3bmTFVGIr0b8pZwEjxyp GjeLUorLUIl1DA72kosz0jJLcxMwcIM9MLze1uDgxPTUnMalYLzk/dxMjMFAZgGAH471lAYcY JTmYlER5s5K3RgjxJeWnVGYkFmfEF5XmpBYfYtTg4BDYtmv1BUYplrz8vFQlCd6FRUB1gkWp6 akVaZk5wFiCKZXg4FES4f1fCJTmLS5IzC3OTIdInWLU5Zgze/cbJiGwGVLivNNBZgiAFGWU5s GNgMX1JUZZKWFeRqADhXgKUotyM0tQ5V8xinMwKgnzXgKZwpOZVwK36RXQEUxAR7xQATuiJBE hJdXAyHPy3gsXe9ctXZ2Xi7vz5i+Ye4uF9Rtb4akX3q1r7rPvn6KZ2DRXbl21rMDDdT+8pJZm KH1tm+P/aO/FFykdW5/erFGfFej3Pzf3+44H7y0OdualNXrvC03kmK2z7JLJot7N28+qxE1vl /hs+DpBS0zzK1dC30eu54J1e5wlzfWt3mydJxU0T4mlOCPRUIu5qDgRAD+tvnbmAgAA X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-10.tower-27.messagelabs.com!1488286727!66040007!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 42641 invoked from network); 28 Feb 2017 12:58:48 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-10.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 28 Feb 2017 12:58:48 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Tue, 28 Feb 2017 05:58:46 -0700 Message-Id: <58B58213020000780013E360@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.1 Date: Tue, 28 Feb 2017 05:58:43 -0700 From: "Jan Beulich" To: "xen-devel" References: <58B57E43020000780013E26B@prv-mh.provo.novell.com> In-Reply-To: <58B57E43020000780013E26B@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH v4 16/17] x86emul: support AESNI insns X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP ... and their AVX equivalents. Signed-off-by: Jan Beulich --- v3: New. x86emul: support AESNI insns ... and their AVX equivalents. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -368,6 +368,8 @@ static const struct { [0x37 ... 0x3f] = { .simd_size = simd_packed_int }, [0x40] = { .simd_size = simd_packed_int }, [0x41] = { .simd_size = simd_packed_int, .two_op = 1 }, + [0xdb] = { .simd_size = simd_packed_int, .two_op = 1 }, + [0xdc ... 0xdf] = { .simd_size = simd_packed_int }, [0xf0] = { .two_op = 1 }, [0xf1] = { .to_memory = 1, .two_op = 1 }, [0xf2 ... 0xf3] = {}, @@ -397,6 +399,7 @@ static const struct { [0x4a ... 0x4b] = { .simd_size = simd_packed_fp, .four_op = 1 }, [0x4c] = { .simd_size = simd_packed_int, .four_op = 1 }, [0x60 ... 0x63] = { .simd_size = simd_packed_int, .two_op = 1 }, + [0xdf] = { .simd_size = simd_packed_int, .two_op = 1 }, [0xf0] = {}, }; @@ -1465,6 +1468,7 @@ static bool vcpu_has( #define vcpu_has_sse4_2() vcpu_has( 1, ECX, 20, ctxt, ops) #define vcpu_has_movbe() vcpu_has( 1, ECX, 22, ctxt, ops) #define vcpu_has_popcnt() vcpu_has( 1, ECX, 23, ctxt, ops) +#define vcpu_has_aesni() vcpu_has( 1, ECX, 25, ctxt, ops) #define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops) #define vcpu_has_rdrand() vcpu_has( 1, ECX, 30, ctxt, ops) #define vcpu_has_mmxext() (vcpu_has(0x80000001, EDX, 22, ctxt, ops) || \ @@ -7155,6 +7159,22 @@ x86_emulate( host_and_vcpu_must_have(sse4_2); goto simd_0f38_common; + case X86EMUL_OPC_66(0x0f38, 0xdb): /* aesimc xmm/m128,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xdc): /* aesenc xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc xmm/m128,xmm,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xdd): /* aesenclast xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast xmm/m128,xmm,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xde): /* aesdec xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec xmm/m128,xmm,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xdf): /* aesdeclast xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast xmm/m128,xmm,xmm */ + host_and_vcpu_must_have(aesni); + if ( vex.opcx == vex_none ) + goto simd_0f38_common; + generate_exception_if(vex.l, EXC_UD); + goto simd_0f_avx; + case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */ case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */ vcpu_must_have(movbe); @@ -7510,6 +7530,14 @@ x86_emulate( dst.type = OP_NONE; break; + case X86EMUL_OPC_66(0x0f3a, 0xdf): /* aeskeygenassist $imm8,xmm/m128,xmm */ + case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist $imm8,xmm/m128,xmm */ + host_and_vcpu_must_have(aesni); + if ( vex.opcx == vex_none ) + goto simd_0f3a_common; + generate_exception_if(vex.l, EXC_UD); + goto simd_0f_imm8_avx; + case X86EMUL_OPC_VEX_F2(0x0f3a, 0xf0): /* rorx imm,r/m,r */ vcpu_must_have(bmi2); generate_exception_if(vex.l || vex.reg != 0xf, EXC_UD); --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -44,6 +44,7 @@ #define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2) #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) #define cpu_has_popcnt boot_cpu_has(X86_FEATURE_POPCNT) +#define cpu_has_aesni boot_cpu_has(X86_FEATURE_AESNI) #define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT) #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -368,6 +368,8 @@ static const struct { [0x37 ... 0x3f] = { .simd_size = simd_packed_int }, [0x40] = { .simd_size = simd_packed_int }, [0x41] = { .simd_size = simd_packed_int, .two_op = 1 }, + [0xdb] = { .simd_size = simd_packed_int, .two_op = 1 }, + [0xdc ... 0xdf] = { .simd_size = simd_packed_int }, [0xf0] = { .two_op = 1 }, [0xf1] = { .to_memory = 1, .two_op = 1 }, [0xf2 ... 0xf3] = {}, @@ -397,6 +399,7 @@ static const struct { [0x4a ... 0x4b] = { .simd_size = simd_packed_fp, .four_op = 1 }, [0x4c] = { .simd_size = simd_packed_int, .four_op = 1 }, [0x60 ... 0x63] = { .simd_size = simd_packed_int, .two_op = 1 }, + [0xdf] = { .simd_size = simd_packed_int, .two_op = 1 }, [0xf0] = {}, }; @@ -1465,6 +1468,7 @@ static bool vcpu_has( #define vcpu_has_sse4_2() vcpu_has( 1, ECX, 20, ctxt, ops) #define vcpu_has_movbe() vcpu_has( 1, ECX, 22, ctxt, ops) #define vcpu_has_popcnt() vcpu_has( 1, ECX, 23, ctxt, ops) +#define vcpu_has_aesni() vcpu_has( 1, ECX, 25, ctxt, ops) #define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops) #define vcpu_has_rdrand() vcpu_has( 1, ECX, 30, ctxt, ops) #define vcpu_has_mmxext() (vcpu_has(0x80000001, EDX, 22, ctxt, ops) || \ @@ -7155,6 +7159,22 @@ x86_emulate( host_and_vcpu_must_have(sse4_2); goto simd_0f38_common; + case X86EMUL_OPC_66(0x0f38, 0xdb): /* aesimc xmm/m128,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xdc): /* aesenc xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc xmm/m128,xmm,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xdd): /* aesenclast xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast xmm/m128,xmm,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xde): /* aesdec xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec xmm/m128,xmm,xmm */ + case X86EMUL_OPC_66(0x0f38, 0xdf): /* aesdeclast xmm/m128,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast xmm/m128,xmm,xmm */ + host_and_vcpu_must_have(aesni); + if ( vex.opcx == vex_none ) + goto simd_0f38_common; + generate_exception_if(vex.l, EXC_UD); + goto simd_0f_avx; + case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */ case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */ vcpu_must_have(movbe); @@ -7510,6 +7530,14 @@ x86_emulate( dst.type = OP_NONE; break; + case X86EMUL_OPC_66(0x0f3a, 0xdf): /* aeskeygenassist $imm8,xmm/m128,xmm */ + case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist $imm8,xmm/m128,xmm */ + host_and_vcpu_must_have(aesni); + if ( vex.opcx == vex_none ) + goto simd_0f3a_common; + generate_exception_if(vex.l, EXC_UD); + goto simd_0f_imm8_avx; + case X86EMUL_OPC_VEX_F2(0x0f3a, 0xf0): /* rorx imm,r/m,r */ vcpu_must_have(bmi2); generate_exception_if(vex.l || vex.reg != 0xf, EXC_UD); --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -44,6 +44,7 @@ #define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2) #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) #define cpu_has_popcnt boot_cpu_has(X86_FEATURE_POPCNT) +#define cpu_has_aesni boot_cpu_has(X86_FEATURE_AESNI) #define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT) #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)