From patchwork Wed Jun 21 09:35:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 9801339 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D80A60329 for ; Wed, 21 Jun 2017 09:37:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A4B71FE82 for ; Wed, 21 Jun 2017 09:37:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CAC928511; Wed, 21 Jun 2017 09:37:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 966571FE82 for ; Wed, 21 Jun 2017 09:37:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dNc2g-00008D-Tb; Wed, 21 Jun 2017 09:35:18 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dNc2f-00007r-Dx for xen-devel@lists.xenproject.org; Wed, 21 Jun 2017 09:35:17 +0000 Received: from [193.109.254.147] by server-5.bemta-6.messagelabs.com id 99/35-03371-4DD3A495; Wed, 21 Jun 2017 09:35:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRWlGSWpSXmKPExsXS6fjDS/eKrVe kwf11HBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8bhnavYCrbpVjzZd5O9gXGWahcjJ4eQQJ7E n70/mUBsXgE7ieu/f4HZEgKGEqcX3mQBsVkEVCUWLngIFmcTUJdoe7adtYuRg0NEwEDi3NGkL kYuDmaBq0wSTYtXsoPUCAuYS9y7soEFYn6RxNYDq8HinAL2EnOWvWYD6eUVEJT4u0MYJMwMtH bFi8XsExh5ZiFkZiHJQNhaEg9/3WKBsLUlli18zQxSziwgLbH8HwdE2FTi24y3TKhKQGwHicd v57IvYORYxahRnFpUllqka2iol1SUmZ5RkpuYmaNraGCml5taXJyYnpqTmFSsl5yfu4kRGK4M QLCD8dOygEOMkhxMSqK8F2S9IoX4kvJTKjMSizPii0pzUosPMWpwcAhs27X6AqMUS15+XqqSB G+ADVCdYFFqempFWmYOMKJgSiU4eJREeJeZA6V5iwsSc4sz0yFSpxgVpcR5WYFxKCQAksgozY Nrg0XxJUZZKWFeRqCjhHgKUotyM0tQ5V8xinMwKglDbOfJzCuBm/4KaDET0OIXRzxAFpckIqS kGhhdOTak1dZ5rzmT8Fr79x6W7REFIq0XP9o3Z+gF5apw8Kvtl9uYuGLDynt5dRuZd8ZctT1+ +3Dwq0jtXw97/nYxc+1/+z2jelHX8v3Fr+bWvmiM+ne08NDfSWFc2gfTX37pC9W4fGXvxnUPS vbvPczisZX1S2eEr3lHubWz1p9rjbXtX+/Mvf9diaU4I9FQi7moOBEAKqupDt0CAAA= X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-11.tower-27.messagelabs.com!1498037714!78179073!1 X-Originating-IP: [137.65.248.74] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 39977 invoked from network); 21 Jun 2017 09:35:15 -0000 Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by server-11.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 21 Jun 2017 09:35:15 -0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 21 Jun 2017 03:35:13 -0600 Message-Id: <594A59F10200007800165090@prv-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.2.2 Date: Wed, 21 Jun 2017 03:35:13 -0600 From: "Jan Beulich" To: "xen-devel" References: <594A57B10200007800165012@prv-mh.provo.novell.com> <594A57B10200007800165012@prv-mh.provo.novell.com> In-Reply-To: <594A57B10200007800165012@prv-mh.provo.novell.com> Mime-Version: 1.0 Cc: Stefano Stabellini , Wei Liu , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall Subject: [Xen-devel] [PATCH 06/11] ARM: simplify page type handling X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP There's no need to have anything here on ARM other than the distinction between writable and non-writable pages (and even that could likely be eliminated, but with a more intrusive change). Limit type to a single bit and drop pinned and validated flags altogether. Signed-off-by: Jan Beulich Reviewed-by: Stefano Stabellini --- Note: Compile tested only. ARM: simplify page type handling There's no need to have anything here on ARM other than the distinction between writable and non-writable pages (and even that could likely be eliminated, but with a more intrusive change). Limit type to a single bit and drop pinned and validated flags altogether. Signed-off-by: Jan Beulich --- Note: Compile tested only. --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -1113,8 +1113,7 @@ void share_xen_page_with_guest(struct pa spin_lock(&d->page_alloc_lock); /* The incremented type count pins as writable or read-only. */ - page->u.inuse.type_info = (readonly ? PGT_none : PGT_writable_page); - page->u.inuse.type_info |= PGT_validated | 1; + page->u.inuse.type_info = (readonly ? PGT_none : PGT_writable_page) | 1; page_set_owner(page, d); smp_wmb(); /* install valid domain ptr before updating refcnt. */ --- a/xen/common/memory.c +++ b/xen/common/memory.c @@ -354,8 +354,10 @@ int guest_remove_page(struct domain *d, rc = guest_physmap_remove_page(d, _gfn(gmfn), mfn, 0); +#ifdef _PGT_pinned if ( !rc && test_and_clear_bit(_PGT_pinned, &page->u.inuse.type_info) ) put_page_and_type(page); +#endif /* * With the lack of an IOMMU on some platforms, domains with DMA-capable --- a/xen/include/asm-arm/mm.h +++ b/xen/include/asm-arm/mm.h @@ -77,20 +77,12 @@ struct page_info #define PG_shift(idx) (BITS_PER_LONG - (idx)) #define PG_mask(x, idx) (x ## UL << PG_shift(idx)) -#define PGT_none PG_mask(0, 4) /* no special uses of this page */ -#define PGT_writable_page PG_mask(7, 4) /* has writable mappings? */ -#define PGT_type_mask PG_mask(15, 4) /* Bits 28-31 or 60-63. */ - - /* Owning guest has pinned this page to its current type? */ -#define _PGT_pinned PG_shift(5) -#define PGT_pinned PG_mask(1, 5) - - /* Has this page been validated for use as its current type? */ -#define _PGT_validated PG_shift(6) -#define PGT_validated PG_mask(1, 6) +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ /* Count of uses of this frame as its current type. */ -#define PGT_count_width PG_shift(9) +#define PGT_count_width PG_shift(2) #define PGT_count_mask ((1UL<page_alloc_lock); /* The incremented type count pins as writable or read-only. */ - page->u.inuse.type_info = (readonly ? PGT_none : PGT_writable_page); - page->u.inuse.type_info |= PGT_validated | 1; + page->u.inuse.type_info = (readonly ? PGT_none : PGT_writable_page) | 1; page_set_owner(page, d); smp_wmb(); /* install valid domain ptr before updating refcnt. */ --- a/xen/common/memory.c +++ b/xen/common/memory.c @@ -354,8 +354,10 @@ int guest_remove_page(struct domain *d, rc = guest_physmap_remove_page(d, _gfn(gmfn), mfn, 0); +#ifdef _PGT_pinned if ( !rc && test_and_clear_bit(_PGT_pinned, &page->u.inuse.type_info) ) put_page_and_type(page); +#endif /* * With the lack of an IOMMU on some platforms, domains with DMA-capable --- a/xen/include/asm-arm/mm.h +++ b/xen/include/asm-arm/mm.h @@ -77,20 +77,12 @@ struct page_info #define PG_shift(idx) (BITS_PER_LONG - (idx)) #define PG_mask(x, idx) (x ## UL << PG_shift(idx)) -#define PGT_none PG_mask(0, 4) /* no special uses of this page */ -#define PGT_writable_page PG_mask(7, 4) /* has writable mappings? */ -#define PGT_type_mask PG_mask(15, 4) /* Bits 28-31 or 60-63. */ - - /* Owning guest has pinned this page to its current type? */ -#define _PGT_pinned PG_shift(5) -#define PGT_pinned PG_mask(1, 5) - - /* Has this page been validated for use as its current type? */ -#define _PGT_validated PG_shift(6) -#define PGT_validated PG_mask(1, 6) +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ /* Count of uses of this frame as its current type. */ -#define PGT_count_width PG_shift(9) +#define PGT_count_width PG_shift(2) #define PGT_count_mask ((1UL<