| Message ID | 5963480B020000780016A1E2@prv-mh.provo.novell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/07/17 08:25, Jan Beulich wrote: > While these are latent issues only for now, correct them right away: > - EVEX.V' (called RX in our code) needs to uniformly be 1, > - EXEX.R' (called R in our code) is uniformly being ignored. > > Signed-off-by: Jan Beulich <jbeulich@suse.com> Those changes do match table 2-40 in the manual, but what about other cases? EVEX.B is uniformly ignored outside of 64bit as well. What about the opcode independent cases? We should check that the two MBZ bits (currently an anonymous bitfield) are zero, and the MBS bit (currently evex.evex) is set. ~Andrew > > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -2544,6 +2544,12 @@ x86_decode( > evex.raw[1] = vex.raw[1]; > evex.raw[2] = insn_fetch_type(uint8_t); > > + if ( !mode_64bit() ) > + { > + generate_exception_if(!evex.RX, EXC_UD); > + evex.R = 1; > + } > + > vex.opcx = evex.opcx; > break; > case 0xc4: > > >
>>> On 05.09.17 at 15:07, <andrew.cooper3@citrix.com> wrote: > On 10/07/17 08:25, Jan Beulich wrote: >> While these are latent issues only for now, correct them right away: >> - EVEX.V' (called RX in our code) needs to uniformly be 1, >> - EXEX.R' (called R in our code) is uniformly being ignored. >> >> Signed-off-by: Jan Beulich <jbeulich@suse.com> > > Those changes do match table 2-40 in the manual, but what about other cases? > > EVEX.B is uniformly ignored outside of 64bit as well. Which is being taken care of by /* Operand size fixed at 4 (no override via W bit). */ op_bytes = 4; vex.b = 1; followed a few lines later by opcode = X86EMUL_OPC_EVEX_; evex.raw[0] = vex.raw[0]; evex.raw[1] = vex.raw[1]; evex.raw[2] = insn_fetch_type(uint8_t); . > What about the opcode independent cases? We should check that the two > MBZ bits (currently an anonymous bitfield) are zero, and the MBS bit > (currently evex.evex) is set. Yes, I could add these here right away instead of deferring until later. Jan
>>> On 05.09.17 at 15:36, <JBeulich@suse.com> wrote: >>>> On 05.09.17 at 15:07, <andrew.cooper3@citrix.com> wrote: >> On 10/07/17 08:25, Jan Beulich wrote: >> What about the opcode independent cases? We should check that the two >> MBZ bits (currently an anonymous bitfield) are zero, and the MBS bit >> (currently evex.evex) is set. > > Yes, I could add these here right away instead of deferring until > later. I'll send an updated v2, but while doing the additions I've noticed that the original patch title justified why the other checks weren't being added at the same time. Jan
--- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2544,6 +2544,12 @@ x86_decode( evex.raw[1] = vex.raw[1]; evex.raw[2] = insn_fetch_type(uint8_t); + if ( !mode_64bit() ) + { + generate_exception_if(!evex.RX, EXC_UD); + evex.R = 1; + } + vex.opcx = evex.opcx; break; case 0xc4:
While these are latent issues only for now, correct them right away: - EVEX.V' (called RX in our code) needs to uniformly be 1, - EXEX.R' (called R in our code) is uniformly being ignored. Signed-off-by: Jan Beulich <jbeulich@suse.com>