diff mbox series

[v2,1/2] x86: define a few selector values

Message ID 5c94e6ba-acd0-ac20-bbf0-187a2e3d0988@suse.com (mailing list archive)
State New, archived
Headers show
Series x86/boot: cleanup | expand

Commit Message

Jan Beulich Aug. 9, 2019, 10:38 a.m. UTC
TSS, LDT, and per-CPU entries all can benefit a little from also having
their selector values defined.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: New.

Comments

Andrew Cooper Aug. 9, 2019, 11:50 a.m. UTC | #1
On 09/08/2019 11:38, Jan Beulich wrote:
> --- a/xen/include/asm-x86/desc.h
> +++ b/xen/include/asm-x86/desc.h
> @@ -36,6 +36,10 @@
>  #define LDT_ENTRY (TSS_ENTRY + 2)
>  #define PER_CPU_GDT_ENTRY (LDT_ENTRY + 2)
>  
> +#define TSS_SELECTOR         (TSS_ENTRY << 3)
> +#define LDT_SELECTOR         (LDT_ENTRY << 3)
> +#define PER_CPU_GDT_SELECTOR (PER_CPU_GDT_ENTRY << 3)

Thinking about it, now would be an excellent time to remove the GDT
infix from PER_CPU_GDT_{ENTRY,SELECTOR}.

Looking at the resulting diff, there are only 3 extra hunks on top of
this patch to perform the rename.

Preferably with this done, Reviewed-by: Andrew Cooper
<andrew.cooper3@citrix.com>
Jan Beulich Aug. 9, 2019, 12:35 p.m. UTC | #2
On 09.08.2019 13:50, Andrew Cooper wrote:
> On 09/08/2019 11:38, Jan Beulich wrote:
>> --- a/xen/include/asm-x86/desc.h
>> +++ b/xen/include/asm-x86/desc.h
>> @@ -36,6 +36,10 @@
>>   #define LDT_ENTRY (TSS_ENTRY + 2)
>>   #define PER_CPU_GDT_ENTRY (LDT_ENTRY + 2)
>>   
>> +#define TSS_SELECTOR         (TSS_ENTRY << 3)
>> +#define LDT_SELECTOR         (LDT_ENTRY << 3)
>> +#define PER_CPU_GDT_SELECTOR (PER_CPU_GDT_ENTRY << 3)
> 
> Thinking about it, now would be an excellent time to remove the GDT
> infix from PER_CPU_GDT_{ENTRY,SELECTOR}.
> 
> Looking at the resulting diff, there are only 3 extra hunks on top of
> this patch to perform the rename.
> 
> Preferably with this done, Reviewed-by: Andrew Cooper
> <andrew.cooper3@citrix.com>

I'm okay with dropping it from the new selector constant,
since "selector" can't really be mistaken. For "entry" though
I think this isn't clear enough without "GDT". (This is less
for a problem with TSS_ENTRY and LDT_ENTRY, as their prefixes
make clear these are GDT entities.)

Jan
Tian, Kevin Aug. 23, 2019, 2:38 a.m. UTC | #3
> From: Jan Beulich [mailto:jbeulich@suse.com]
> Sent: Friday, August 9, 2019 6:39 PM
> 
> TSS, LDT, and per-CPU entries all can benefit a little from also having
> their selector values defined.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Kevin Tian <kevin.tian@intel.com>
diff mbox series

Patch

--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -761,7 +761,7 @@  void load_system_tables(void)
  	per_cpu(full_gdt_loaded, cpu) = false;
  	lgdt(&gdtr);
  	lidt(&idtr);
-	ltr(TSS_ENTRY << 3);
+	ltr(TSS_SELECTOR);
  	lldt(0);
  
  	enable_each_ist(idt_tables[cpu]);
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1572,7 +1572,7 @@  bool svm_load_segs(unsigned int ldt_ents
  
          _set_tssldt_desc(desc, ldt_base, ldt_ents * 8 - 1, SYS_DESC_ldt);
  
-        vmcb->ldtr.sel = LDT_ENTRY << 3;
+        vmcb->ldtr.sel = LDT_SELECTOR;
          vmcb->ldtr.attr = SYS_DESC_ldt | (_SEGMENT_P >> 8);
          vmcb->ldtr.limit = ldt_ents * 8 - 1;
          vmcb->ldtr.base = ldt_base;
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -1128,7 +1128,7 @@  static int construct_vmcs(struct vcpu *v
      __vmwrite(HOST_GS_SELECTOR, 0);
      __vmwrite(HOST_FS_BASE, 0);
      __vmwrite(HOST_GS_BASE, 0);
-    __vmwrite(HOST_TR_SELECTOR, TSS_ENTRY << 3);
+    __vmwrite(HOST_TR_SELECTOR, TSS_SELECTOR);
  
      /* Host control registers. */
      v->arch.hvm.vmx.host_cr0 = read_cr0() & ~X86_CR0_TS;
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1917,7 +1917,7 @@  void load_TR(void)
      /* Switch to non-compat GDT (which has B bit clear) to execute LTR. */
      asm volatile (
          "sgdt %0; lgdt %2; ltr %w1; lgdt %0"
-        : "=m" (old_gdt) : "rm" (TSS_ENTRY << 3), "m" (tss_gdt) : "memory" );
+        : "=m" (old_gdt) : "rm" (TSS_SELECTOR), "m" (tss_gdt) : "memory" );
  }
  
  static unsigned int calc_ler_msr(void)
--- a/xen/arch/x86/x86_64/traps.c
+++ b/xen/arch/x86/x86_64/traps.c
@@ -251,7 +251,7 @@  void do_double_fault(struct cpu_user_reg
  
      console_force_unlock();
  
-    asm ( "lsll %1, %0" : "=r" (cpu) : "rm" (PER_CPU_GDT_ENTRY << 3) );
+    asm ( "lsll %1, %0" : "=r" (cpu) : "rm" (PER_CPU_GDT_SELECTOR) );
  
      /* Find information saved during fault and dump it to the console. */
      printk("*** DOUBLE FAULT ***\n");
--- a/xen/include/asm-x86/desc.h
+++ b/xen/include/asm-x86/desc.h
@@ -36,6 +36,10 @@ 
  #define LDT_ENTRY (TSS_ENTRY + 2)
  #define PER_CPU_GDT_ENTRY (LDT_ENTRY + 2)
  
+#define TSS_SELECTOR         (TSS_ENTRY << 3)
+#define LDT_SELECTOR         (LDT_ENTRY << 3)
+#define PER_CPU_GDT_SELECTOR (PER_CPU_GDT_ENTRY << 3)
+
  #ifndef __ASSEMBLY__
  
  #define GUEST_KERNEL_RPL(d) (is_pv_32bit_domain(d) ? 1 : 3)
--- a/xen/include/asm-x86/ldt.h
+++ b/xen/include/asm-x86/ldt.h
@@ -16,7 +16,7 @@  static inline void load_LDT(struct vcpu
          desc = (!is_pv_32bit_vcpu(v) ? this_cpu(gdt) : this_cpu(compat_gdt))
                 + LDT_ENTRY - FIRST_RESERVED_GDT_ENTRY;
          _set_tssldt_desc(desc, LDT_VIRT_START(v), ents*8-1, SYS_DESC_ldt);
-        lldt(LDT_ENTRY << 3);
+        lldt(LDT_SELECTOR);
      }
  }