| Message ID | 79b08632b74dc13b8c399003eb76d198cb73ac32.1743771654.git.teddy.astie@vates.tech (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/2] x86/amd: Add guest support for AMD TCE | expand |
On 07.04.2025 11:10, Teddy Astie wrote: > Aside exposing this flag to guests, Xen can also make use of it to reduce the cost of > some TLB flushes. Enable this flag if supported by hardware. As said before: This needs to come with (perhaps a lot of) justification as to it being safe for Xen to use without any adjustments anywhere else. This exercise may not be left to the reviewer(s). Jan
On 09.04.2025 09:11, Jan Beulich wrote: > On 07.04.2025 11:10, Teddy Astie wrote: >> Aside exposing this flag to guests, Xen can also make use of it to reduce the cost of >> some TLB flushes. Enable this flag if supported by hardware. > > As said before: This needs to come with (perhaps a lot of) justification as > to it being safe for Xen to use without any adjustments anywhere else. This > exercise may not be left to the reviewer(s). One case to consider in particular is a shadow guest (EFER.TCE clear as per patch 1) running with host EFER.TCE set. The TLB flushes we do may then simply be insufficient for the guest's expectations. Jan
diff --git a/CHANGELOG.md b/CHANGELOG.md index dbfecefbd4..375905e68a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,7 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. - - Guest support for AMD Translation Cache Extension feature. + - Guest and Xen support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 05399fb9c9..ab6d07b767 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -114,6 +114,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) #define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) +#define cpu_has_tce boot_cpu_has(X86_FEATURE_TCE) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) /* CPUID level 0x0000000D:1.eax */ diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d70abb7e0c..9b1924ad05 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -2008,6 +2008,12 @@ void asmlinkage __init noreturn __start_xen(void) if ( cpu_has_pku ) set_in_cr4(X86_CR4_PKE); + if ( cpu_has_tce ) + { + write_efer(read_efer() | EFER_TCE); + bootsym(trampoline_efer) |= EFER_TCE; + } + if ( opt_invpcid && cpu_has_invpcid ) use_invpcid = true;
Aside exposing this flag to guests, Xen can also make use of it to reduce the cost of some TLB flushes. Enable this flag if supported by hardware. Signed-off-by: Teddy Astie <teddy.astie@vates.tech> --- v2: - Add changelog entry - use trampoline_efer - use cpu_has_tce instead of opencoded boot_cpu_has(X86_FEATURE_TCE) v3: - drop message - use bootsym for modifying trampoline_efer --- CHANGELOG.md | 2 +- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/setup.c | 6 ++++++ 3 files changed, 8 insertions(+), 1 deletion(-)