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[XEN,v2,06/25] arm: new VGIC: Add GICv3 IDREGS register handler

Message ID 7c563e5745c14123c8124e765bfff1345ad73c6b.1699618395.git.mykyta_poturai@epam.com (mailing list archive)
State New, archived
Headers show
Series arm: Add GICv3 support to the New VGIC | expand

Commit Message

Mykyta Poturai Nov. 10, 2023, 12:56 p.m. UTC 
We implement the only one ID register that is required by the
architecture, also this is the one that Linux actually checks.

Based on Linux commit 54f59d2b3a0a3d by Andre Przywara

Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
 xen/arch/arm/vgic/vgic-mmio-v3.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)
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Patch

diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 707a38c727..ccdf3b9456 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -152,6 +152,19 @@  static unsigned long vgic_mmio_read_v3r_iidr(struct vcpu *vcpu, paddr_t addr,
            (IMPLEMENTER_ARM << 0);
 }
 
+static unsigned long vgic_mmio_read_v3_idregs(struct vcpu *vcpu, paddr_t addr,
+                                              unsigned int len)
+{
+    switch ( addr & 0xfff )
+    {
+    case GICD_ICPIDR2:
+        /* report a GICv3 compliant implementation */
+        return 0x3b;
+    }
+
+    return 0;
+}
+
 static const struct vgic_register_region vgic_v3_dist_registers[] = {
     REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
         vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
@@ -196,7 +209,7 @@  static const struct vgic_register_region vgic_v3_dist_registers[] = {
         vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
         VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
     REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
-        vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
+        vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
         VGIC_ACCESS_32bit),
 };
 
@@ -233,7 +246,7 @@  static const struct vgic_register_region vgic_v3_rd_registers[] = {
         vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
         VGIC_ACCESS_32bit),
     REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
-        vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
+        vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
         VGIC_ACCESS_32bit),
     /* SGI_base registers */
     REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,