@@ -3772,7 +3772,7 @@ long do_mmuext_op(
else if ( unlikely(!cache_flush_permitted(currd)) )
rc = -EACCES;
else
- wbinvd();
+ wbnoinvd();
break;
case MMUEXT_FLUSH_CACHE_GLOBAL:
@@ -3788,7 +3788,7 @@ long do_mmuext_op(
if ( !cpumask_intersects(mask,
per_cpu(cpu_sibling_mask, cpu)) )
__cpumask_set_cpu(cpu, mask);
- flush_mask(mask, FLUSH_CACHE);
+ flush_mask(mask, FLUSH_CACHE_WRITEBACK);
}
else
rc = -EINVAL;
@@ -1196,10 +1196,8 @@ static int cf_check cache_op(
* newer linux uses this in some start-of-day timing loops.
*/
;
- else if ( op == x86emul_wbnoinvd /* && cpu_has_wbnoinvd */ )
- wbnoinvd();
else
- wbinvd();
+ wbnoinvd();
return X86EMUL_OKAY;
}
@@ -238,7 +238,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /
/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */
-XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /*S WBNOINVD instruction */
+XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /*A WBNOINVD instruction */
XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */
XEN_CPUFEATURE(IBRS, 8*32+14) /*S MSR_SPEC_CTRL.IBRS */
XEN_CPUFEATURE(AMD_STIBP, 8*32+15) /*S MSR_SPEC_CTRL.STIBP */
We allow its use for writeback purposes only anyway, so let's also carry these out that way on capable hardware. We can then also expose the WBNOINVD feature, as there's no difference to WBINVD anymore. Note that respective emulation logic has already been in place since ad3abc47dd23 ("x86emul: support WBNOINVD"). Signed-off-by: Jan Beulich <jbeulich@suse.com> --- v2: FLUSH_WRITEBACK -> FLUSH_CACHE_WRITEBACK.