Message ID | a1b23ffd-6af4-a3c1-b4ac-ba7bd3ec1d70@suse.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | x86emul: correct far branch handling for 64-bit mode | expand |
--- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2519,9 +2519,16 @@ x86_decode_onebyte( case 6: /* push */ if ( mode_64bit() && op_bytes == 4 ) op_bytes = 8; - /* fall through */ + state->desc = DstNone | SrcMem | Mov; + break; + case 3: /* call (far, absolute indirect) */ case 5: /* jmp (far, absolute indirect) */ + /* REX.W ignored on a vendor-dependent basis. */ + if ( op_bytes == 8 && + (ctxt->cpuid->x86_vendor & + (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + op_bytes = 4; state->desc = DstNone | SrcMem | Mov; break; }
AMD and friends explicitly specify that 64-bit operands aren't possible for these insns. Nevertheless REX.W isn't fully ignored: It still cancels a possible operand size override (0x66). Intel otoh explicitly provides for 64-bit operands on the respective insn page of the SDM. Signed-off-by: Jan Beulich <jbeulich@suse.com>