From patchwork Tue Jun 20 23:04:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 9800387 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2B97460329 for ; Tue, 20 Jun 2017 23:06:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1848E1FF21 for ; Tue, 20 Jun 2017 23:06:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0B8B926E49; Tue, 20 Jun 2017 23:06:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 60E811FF21 for ; Tue, 20 Jun 2017 23:06:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dNSC6-0002gV-RX; Tue, 20 Jun 2017 23:04:22 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dNSC5-0002gP-Uf for xen-devel@lists.xen.org; Tue, 20 Jun 2017 23:04:22 +0000 Received: from [193.109.254.147] by server-2.bemta-6.messagelabs.com id C4/23-03058-5F9A9495; Tue, 20 Jun 2017 23:04:21 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRWlGSWpSXmKPExsVybKJssu6XlZ6 RBg9uy1gs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnL3jxjLVghUXFoQxt7A+NOkS5GLg4hgT+M EkeffGTuYuTgYBFwkFg+nRXEZBSIkXjww7qLkRPIDJOYfHkJK4jNIqAt0di8lAnEZhMwlPj7Z BMbSLkEkL3kMwdIWERAQmJTwwomkDCzgLFEc38lSFhYwFTi+erf7CA2r4C3RPvJZywgtqiArs Shf3/YIOKCEidnPgGLMwtoAd2yjWUCI98sJKlZSFILGJlWMaoXpxaVpRbpGuolFWWmZ5TkJmb m6BoamOnlphYXJ6an5iQmFesl5+duYgQGEwMQ7GDc+dzpEKMkB5OSKG9OhWekEF9SfkplRmJx RnxRaU5q8SFGGQ4OJQneLyuAcoJFqempFWmZOcCwhklLcPAoifCGzwFK8xYXJOYWZ6ZDpE4x6 nJsWL3+C5MQS15+XqqUOC8HMEqEBECKMkrz4EbAYuwSo6yUMC8j0FFCPAWpRbmZJajyrxjFOR iVhHnvgFzCk5lXArfpFdARTEBHvDjiAXJESSJCSqqBUYR/qsGb/ecOzoq1CZvOLrgm75f9l3s blMzP1i+Jci/s8b3iqWE1zytsyaliv7S6+awP9mZ+fWJv+nnqkbtdG14stVg7MWl9+h0ViyzP +k21Fed4Ut3Yt9zZuyvyweQGxkg/6/ZZbsFNfSeNbWz0U2TY2et3HZpVMj+7yPbp8x3fbmY0C GyNUWIpzkg01GIuKk4EAJiLOnasAgAA X-Env-Sender: sstabellini@kernel.org X-Msg-Ref: server-4.tower-27.messagelabs.com!1497999859!107862861!1 X-Originating-IP: [198.145.29.99] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 61366 invoked from network); 20 Jun 2017 23:04:20 -0000 Received: from mail.kernel.org (HELO mail.kernel.org) (198.145.29.99) by server-4.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 20 Jun 2017 23:04:20 -0000 Received: from [10.149.184.130] (unknown [99.165.194.18]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4DA92239F0; Tue, 20 Jun 2017 23:04:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4DA92239F0 Date: Tue, 20 Jun 2017 16:04:17 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@sstabellini-ThinkPad-X260 To: julien.grall@arm.com Message-ID: User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 Cc: sstabellini@kernel.org, xen-devel@lists.xen.org Subject: [Xen-devel] [PATCH v2] docs: improve ARM passthrough doc X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add a warning: use passthrough with care. Add a pointer to the gic device tree bindings. Add an explanation on how to calculate irq numbers from device tree. Add a brief explanation of the reg property and a pointer to the xl docs for a description of the iomem property. Add a note that in the example we are using different memory addresses for guests and host. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall --- Changes in v2: - fix typo - add more info on the interrupts property and different interrupt controllers diff --git a/docs/misc/arm/passthrough.txt b/docs/misc/arm/passthrough.txt index 082e9ab..323257d 100644 --- a/docs/misc/arm/passthrough.txt +++ b/docs/misc/arm/passthrough.txt @@ -12,7 +12,11 @@ property "xen,passthrough". The command to do it in U-Boot is: 2) Create a partial device tree describing the device. The IRQ are mapped 1:1 to the guest (i.e VIRQ == IRQ). For MMIO, you will have to find a hole in the guest memory layout (see xen/include/public/arch-arm.h, note that -the layout is not stable and can change between versions of Xen). +the layout is not stable and can change between versions of Xen). Please +be aware that passing a partial device tree to a VM is a powerful tool, +use it with care. In production, only allow assignment of devices which +have been previously tested and known to work correctly when given to +guests. /dts-v1/; @@ -48,6 +52,8 @@ Note: - #size-cells * See http://www.devicetree.org/Device_Tree_Usage for more information about device tree. + * In this example, the device MMIO region is placed at a different + address (0x10000000) compared to the host address (0xfff51000) 3) Compile the partial guest device with dtc (Device Tree Compiler). For our purpose, the compiled file will be called guest-midway.dtb and @@ -60,3 +66,20 @@ dtdev = [ "/soc/ethernet@fff51000" ] irqs = [ 112, 113, 114 ] iomem = [ "0xfff51,1@0x10000" ] +Please refer to your platform docs for the MMIO ranges and interrupts. + +They can also be calculated from the original device tree (not +recommended). You can read about the "interrupts" property format in the +device tree bindings of the interrupt controller of your platform. For +example, in the case of GICv2 see [arm,gic.txt]; in the case of GICv3 +see [arm,gic-v3.txt] in the Linux repository. For both GICv2 and GICv3 +the "interrupts" property format is the same: the first cell is the +interrupt type, and the second cell is the interrupt number. Given that +SPI numbers start from 32, in this example 80 + 32 = 112. + +See man [xl.cfg] for the iomem format. The reg property is just a pair +of address, then size numbers, each of them can occupy 1 or 2 cells. + +[arm,gic.txt]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +[arm,gic-v3.txt]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +[xl.cfg]: https://xenbits.xen.org/docs/unstable/man/xl.cfg.5.html