@@ -121,30 +121,30 @@
#define DMA_TLB_IVA_HINT(x) ((((u64)x) & 1) << 6)
/* GCMD_REG */
-#define DMA_GCMD_TE (((u64)1) << 31)
-#define DMA_GCMD_SRTP (((u64)1) << 30)
-#define DMA_GCMD_SFL (((u64)1) << 29)
-#define DMA_GCMD_EAFL (((u64)1) << 28)
-#define DMA_GCMD_WBF (((u64)1) << 27)
-#define DMA_GCMD_QIE (((u64)1) << 26)
-#define DMA_GCMD_IRE (((u64)1) << 25)
-#define DMA_GCMD_SIRTP (((u64)1) << 24)
-#define DMA_GCMD_CFI (((u64)1) << 23)
+#define DMA_GCMD_TE (1u << 31)
+#define DMA_GCMD_SRTP (1u << 30)
+#define DMA_GCMD_SFL (1u << 29)
+#define DMA_GCMD_EAFL (1u << 28)
+#define DMA_GCMD_WBF (1u << 27)
+#define DMA_GCMD_QIE (1u << 26)
+#define DMA_GCMD_IRE (1u << 25)
+#define DMA_GCMD_SIRTP (1u << 24)
+#define DMA_GCMD_CFI (1u << 23)
/* GSTS_REG */
-#define DMA_GSTS_TES (((u64)1) << 31)
-#define DMA_GSTS_RTPS (((u64)1) << 30)
-#define DMA_GSTS_FLS (((u64)1) << 29)
-#define DMA_GSTS_AFLS (((u64)1) << 28)
-#define DMA_GSTS_WBFS (((u64)1) << 27)
-#define DMA_GSTS_QIES (((u64)1) <<26)
-#define DMA_GSTS_IRES (((u64)1) <<25)
-#define DMA_GSTS_SIRTPS (((u64)1) << 24)
-#define DMA_GSTS_CFIS (((u64)1) <<23)
+#define DMA_GSTS_TES (1u << 31)
+#define DMA_GSTS_RTPS (1u << 30)
+#define DMA_GSTS_FLS (1u << 29)
+#define DMA_GSTS_AFLS (1u << 28)
+#define DMA_GSTS_WBFS (1u << 27)
+#define DMA_GSTS_QIES (1u << 26)
+#define DMA_GSTS_IRES (1u << 25)
+#define DMA_GSTS_SIRTPS (1u << 24)
+#define DMA_GSTS_CFIS (1u << 23)
/* PMEN_REG */
-#define DMA_PMEN_EPM (((u32)1) << 31)
-#define DMA_PMEN_PRS (((u32)1) << 0)
+#define DMA_PMEN_EPM (1u << 31)
+#define DMA_PMEN_PRS (1u << 0)
/* CCMD_REG */
#define DMA_CCMD_INVL_GRANU_OFFSET 61
@@ -164,21 +164,23 @@
#define DMA_CCMD_CAIG_MASK(x) (((u64)x) & ((u64) 0x3 << 59))
/* FECTL_REG */
-#define DMA_FECTL_IM (((u64)1) << 31)
+#define DMA_FECTL_IM (1u << 31)
/* FSTS_REG */
-#define DMA_FSTS_PFO ((u64)1 << 0)
-#define DMA_FSTS_PPF ((u64)1 << 1)
-#define DMA_FSTS_AFO ((u64)1 << 2)
-#define DMA_FSTS_APF ((u64)1 << 3)
-#define DMA_FSTS_IQE ((u64)1 << 4)
-#define DMA_FSTS_ICE ((u64)1 << 5)
-#define DMA_FSTS_ITE ((u64)1 << 6)
-#define DMA_FSTS_FAULTS DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_AFO | DMA_FSTS_APF | DMA_FSTS_IQE | DMA_FSTS_ICE | DMA_FSTS_ITE
+#define DMA_FSTS_PFO (1u << 0)
+#define DMA_FSTS_PPF (1u << 1)
+#define DMA_FSTS_AFO (1u << 2)
+#define DMA_FSTS_APF (1u << 3)
+#define DMA_FSTS_IQE (1u << 4)
+#define DMA_FSTS_ICE (1u << 5)
+#define DMA_FSTS_ITE (1u << 6)
+#define DMA_FSTS_FAULTS (DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_AFO | \
+ DMA_FSTS_APF | DMA_FSTS_IQE | DMA_FSTS_ICE | \
+ DMA_FSTS_ITE)
#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
/* FRCD_REG, 32 bits access */
-#define DMA_FRCD_F (((u64)1) << 31)
+#define DMA_FRCD_F (1u << 31)
#define dma_frcd_type(d) ((d >> 30) & 1)
#define dma_frcd_fault_reason(c) (c & 0xff)
#define dma_frcd_source_id(c) (c & 0xffff)
When the respective registers are just 32 bits wide there's no point in making corresponding constants 64-bit ones. Signed-off-by: Jan Beulich <jbeulich@suse.com>