diff mbox series

[RFC,4/4] amd/iommu: fully initialize array in 'flush_command_buffer'

Message ID b772842fccacc4fb108ff515bdcad6f2877b6b12.1698155925.git.nicola.vetrini@bugseng.com (mailing list archive)
State New, archived
Headers show
Series address violations of MISRA C Rule 9.3 | expand

Commit Message

Nicola Vetrini Oct. 24, 2023, 2:31 p.m. UTC 
Fully explicit initialization of the cmd array resolves a violation of
MISRA C:2012 Rule 9.3.

Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
---
 xen/drivers/passthrough/amd/iommu_cmd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

--
2.34.1

Comments

Jan Beulich Oct. 24, 2023, 2:51 p.m. UTC | #1 
On 24.10.2023 16:31, Nicola Vetrini wrote:
> Fully explicit initialization of the cmd array resolves a violation of
> MISRA C:2012 Rule 9.3.
> 
> Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>

While I'm not overly happy, we accepted the rule, so
Acked-by: Jan Beulich <jbeulich@suse.com>
diff mbox series

Patch

diff --git a/xen/drivers/passthrough/amd/iommu_cmd.c b/xen/drivers/passthrough/amd/iommu_cmd.c
index cb28b36abc38..49b9fcac9410 100644
--- a/xen/drivers/passthrough/amd/iommu_cmd.c
+++ b/xen/drivers/passthrough/amd/iommu_cmd.c
@@ -66,7 +66,8 @@  static void flush_command_buffer(struct amd_iommu *iommu,
                          IOMMU_COMP_WAIT_S_FLAG_MASK),
         (addr >> 32) | MASK_INSR(IOMMU_CMD_COMPLETION_WAIT,
                                  IOMMU_CMD_OPCODE_MASK),
-        CMD_COMPLETION_DONE
+        CMD_COMPLETION_DONE,
+        0
     };
     s_time_t start, timeout;
     static unsigned int __read_mostly threshold = 1;