From patchwork Fri Aug 16 11:14:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13766013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7A6AC3DA4A for ; Fri, 16 Aug 2024 11:15:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778555.1188611 (Exim 4.92) (envelope-from ) id 1seuvF-0007s2-P3; Fri, 16 Aug 2024 11:15:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778555.1188611; Fri, 16 Aug 2024 11:15:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuvF-0007rv-MI; Fri, 16 Aug 2024 11:15:09 +0000 Received: by outflank-mailman (input) for mailman id 778555; Fri, 16 Aug 2024 11:15:08 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuvE-0007rp-Bj for xen-devel@lists.xenproject.org; Fri, 16 Aug 2024 11:15:08 +0000 Received: from pb-smtp21.pobox.com (pb-smtp21.pobox.com [173.228.157.53]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ca007d53-5bc0-11ef-8776-851b0ebba9a2; Fri, 16 Aug 2024 13:15:06 +0200 (CEST) Received: from pb-smtp21.pobox.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 4A9DA1AE93; Fri, 16 Aug 2024 07:15:04 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp21.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 320161AE92; Fri, 16 Aug 2024 07:15:04 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp21.pobox.com (Postfix) with ESMTPSA id 85F981AE8E; Fri, 16 Aug 2024 07:15:00 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ca007d53-5bc0-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=SImZJDa/oxwFzFRYOBx72eonr TZPtSmDNOl28smcrN4=; b=W5GAoZqVvANw8VMDmkR8LKn9oLIJKvQ04wCU9ocs6 aP3eA5UnByYIn0h5IeATBNHlr510pSfxazBe/tnaFYbyXwWhwNvp7pVOnhqvxcaR ZlIve0cLYYu1UzZVofENQElpHkSXjnk58nDtshhERb/lsK9STNb4P1W8jS4u0FHv 5c= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Jan Beulich Subject: [XEN PATCH v2 3/5] x86/spec-ctrl: configurable Intlel/AMD-specific calculations Date: Fri, 16 Aug 2024 14:14:52 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: C7331240-5BC0-11EF-94DE-E92ED1CD468F-90055647!pb-smtp21.pobox.com Put platforms-specific code under #ifdef CONFIG_{AMD,INTEL} so that when corresponding CPU support is disabled by configuration less dead code will end up in the build. This includes re-ordering of calls to ibpb_calculations() & div_calculations(), but since they don't access common variables or feature bits it should be safe to do. Signed-off-by: Sergiy Kibrik CC: Jan Beulich --- xen/arch/x86/spec_ctrl.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 75a4177a75..ba6c3e80d2 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -1012,6 +1012,7 @@ static bool __init should_use_eager_fpu(void) } } +#ifdef CONFIG_AMD /* * https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf */ @@ -1110,6 +1111,7 @@ static void __init div_calculations(bool hw_smt_enabled) "enabled. Please assess your configuration and choose an\n" "explicit 'smt=' setting. See XSA-439.\n"); } +#endif /* CONFIG_AMD */ static void __init ibpb_calculations(void) { @@ -1319,6 +1321,7 @@ static __init void l1tf_calculations(void) : (3UL << (paddr_bits - 2)))); } +#ifdef CONFIG_INTEL /* Calculate whether this CPU is vulnerable to MDS. */ static __init void mds_calculations(void) { @@ -1730,6 +1733,8 @@ static void __init bhi_calculations(void) } } +#endif /* CONFIG_INTEL */ + void spec_ctrl_init_domain(struct domain *d) { bool pv = is_pv_domain(d); @@ -2025,11 +2030,13 @@ void __init init_speculation_mitigations(void) default_scf |= SCF_ist_rsb; } +#ifdef CONFIG_AMD srso_calculations(hw_smt_enabled); - ibpb_calculations(); - div_calculations(hw_smt_enabled); +#endif + + ibpb_calculations(); /* Check whether Eager FPU should be enabled by default. */ if ( opt_eager_fpu == -1 ) @@ -2136,9 +2143,10 @@ void __init init_speculation_mitigations(void) * - March 2023, for RFDS. Enumerate RFDS_CLEAR to mean that VERW now * scrubs non-architectural entries from certain register files. */ +#ifdef CONFIG_INTEL mds_calculations(); rfds_calculations(); - +#endif /* * Parts which enumerate FB_CLEAR are those with now-updated microcode * which weren't susceptible to the original MFBDS (and therefore didn't @@ -2255,7 +2263,6 @@ void __init init_speculation_mitigations(void) opt_tsx = 0; tsx_init(); } -#endif /* * On some SRBDS-affected hardware, it may be safe to relax srb-lock by @@ -2286,6 +2293,8 @@ void __init init_speculation_mitigations(void) bhi_calculations(); +#endif /* CONFIG_INTEL */ + print_details(thunk); /*