diff mbox series

[v4,07/12] AMD/IOMMU: allow enabling with IRQ not yet set up

Message ID c291ed9d-cb2c-2b63-fe8f-a6d6b778f504@suse.com (mailing list archive)
State New, archived
Headers show
Series [v4,01/12] AMD/IOMMU: use bit field for extended feature register | expand

Commit Message

Jan Beulich July 25, 2019, 1:31 p.m. UTC 
Early enabling (to enter x2APIC mode) requires deferring of the IRQ
setup. Code to actually do that setup in the x2APIC case will get added
subsequently.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Brian Woods <brian.woods@amd.com>
---
v3: Re-base.
diff mbox series

Patch

--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -813,7 +813,6 @@  static void amd_iommu_erratum_746_workar
  static void enable_iommu(struct amd_iommu *iommu)
  {
      unsigned long flags;
-    struct irq_desc *desc;
  
      spin_lock_irqsave(&iommu->lock, flags);
  
@@ -833,19 +832,27 @@  static void enable_iommu(struct amd_iomm
      if ( iommu->features.flds.ppr_sup )
          register_iommu_ppr_log_in_mmio_space(iommu);
  
-    desc = irq_to_desc(iommu->msi.irq);
-    spin_lock(&desc->lock);
-    set_msi_affinity(desc, NULL);
-    spin_unlock(&desc->lock);
+    if ( iommu->msi.irq > 0 )
+    {
+        struct irq_desc *desc = irq_to_desc(iommu->msi.irq);
+
+        spin_lock(&desc->lock);
+        set_msi_affinity(desc, NULL);
+        spin_unlock(&desc->lock);
+    }
  
      amd_iommu_msi_enable(iommu, IOMMU_CONTROL_ENABLED);
  
      set_iommu_ht_flags(iommu);
      set_iommu_command_buffer_control(iommu, IOMMU_CONTROL_ENABLED);
-    set_iommu_event_log_control(iommu, IOMMU_CONTROL_ENABLED);
  
-    if ( iommu->features.flds.ppr_sup )
-        set_iommu_ppr_log_control(iommu, IOMMU_CONTROL_ENABLED);
+    if ( iommu->msi.irq > 0 )
+    {
+        set_iommu_event_log_control(iommu, IOMMU_CONTROL_ENABLED);
+
+        if ( iommu->features.flds.ppr_sup )
+            set_iommu_ppr_log_control(iommu, IOMMU_CONTROL_ENABLED);
+    }
  
      if ( iommu->features.flds.gt_sup )
          set_iommu_guest_translation_control(iommu, IOMMU_CONTROL_ENABLED);