From patchwork Tue Jan 14 10:02:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 11331781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7CB1930 for ; Tue, 14 Jan 2020 10:03:20 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE1E424683 for ; Tue, 14 Jan 2020 10:03:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CE1E424683 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1irJ1Z-00019c-AW; Tue, 14 Jan 2020 10:02:13 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1irJ1Y-00019X-Nj for xen-devel@lists.xenproject.org; Tue, 14 Jan 2020 10:02:12 +0000 X-Inumbo-ID: e9f3bf04-36b4-11ea-a985-bc764e2007e4 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id e9f3bf04-36b4-11ea-a985-bc764e2007e4; Tue, 14 Jan 2020 10:02:04 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 19FFAACD9; Tue, 14 Jan 2020 10:02:03 +0000 (UTC) To: "xen-devel@lists.xenproject.org" From: Jan Beulich Message-ID: Date: Tue, 14 Jan 2020 11:02:02 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 Content-Language: en-US Subject: [Xen-devel] [PATCH] IRQ: u16 is too narrow for an event channel number X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , Wei Liu , Konrad Wilk , George Dunlap , Andrew Cooper , Ian Jackson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" FIFO event channels allow ports up to 2^17, so we need to use a wider field in struct pirq. Move "masked" such that it may share the 8-byte slot with struct arch_pirq on 64-bit arches, rather than leaving a 7-byte hole in all cases. Take the opportunity and also add a comment regarding "arch" placement within the structure. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- a/xen/include/xen/irq.h +++ b/xen/include/xen/irq.h @@ -127,9 +127,10 @@ struct vcpu; struct pirq { int pirq; - u16 evtchn; - bool_t masked; + evtchn_port_t evtchn; struct rcu_head rcu_head; + bool masked; + /* Architectures may require this field to be last. */ struct arch_pirq arch; };