diff mbox series

[XEN,v1,3/7] x86/MCE: guard access to Intel/AMD-specific MCA MSRs

Message ID d187db984b9b5413d73849594985e10c2c2fdc03.1713860310.git.Sergiy_Kibrik@epam.com (mailing list archive)
State Superseded
Headers show
Series x86: make Intel/AMD vPMU & MCE support configurable | expand

Commit Message

Sergiy Kibrik April 23, 2024, 8:52 a.m. UTC
Add build-time checks for newly introduced INTEL/AMD config options when
calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines.
This way a platform-specific code can be omitted in vmce code, if this
platform is disabled in config.

Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
---
 xen/arch/x86/cpu/mcheck/vmce.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

Comments

Stefano Stabellini April 26, 2024, 11:08 p.m. UTC | #1
On Tue, 23 Apr 2024, Sergiy Kibrik wrote:
> Add build-time checks for newly introduced INTEL/AMD config options when
> calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines.
> This way a platform-specific code can be omitted in vmce code, if this
> platform is disabled in config.
> 
> Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Jan Beulich April 29, 2024, 3:41 p.m. UTC | #2
On 23.04.2024 10:52, Sergiy Kibrik wrote:
> --- a/xen/arch/x86/cpu/mcheck/vmce.c
> +++ b/xen/arch/x86/cpu/mcheck/vmce.c
> @@ -141,12 +141,14 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
>          case X86_VENDOR_CENTAUR:
>          case X86_VENDOR_SHANGHAI:
>          case X86_VENDOR_INTEL:
> -            ret = vmce_intel_rdmsr(v, msr, val);
> +            ret = IS_ENABLED(CONFIG_INTEL) ?
> +                  vmce_intel_rdmsr(v, msr, val) : -ENODEV;
>              break;
>  
>          case X86_VENDOR_AMD:
>          case X86_VENDOR_HYGON:
> -            ret = vmce_amd_rdmsr(v, msr, val);
> +            ret = IS_ENABLED(CONFIG_AMD) ?
> +                  vmce_amd_rdmsr(v, msr, val) : -ENODEV;
>              break;

Why -ENODEV when ...

>          default:

... below here 0 is put into "ret"? And why not have the default case take
care of unsupported/unrecognized vendors uniformly?

Jan
diff mbox series

Patch

diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index c437f62c0a..be229684a4 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -141,12 +141,14 @@  static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
         case X86_VENDOR_CENTAUR:
         case X86_VENDOR_SHANGHAI:
         case X86_VENDOR_INTEL:
-            ret = vmce_intel_rdmsr(v, msr, val);
+            ret = IS_ENABLED(CONFIG_INTEL) ?
+                  vmce_intel_rdmsr(v, msr, val) : -ENODEV;
             break;
 
         case X86_VENDOR_AMD:
         case X86_VENDOR_HYGON:
-            ret = vmce_amd_rdmsr(v, msr, val);
+            ret = IS_ENABLED(CONFIG_AMD) ?
+                  vmce_amd_rdmsr(v, msr, val) : -ENODEV;
             break;
 
         default:
@@ -272,12 +274,14 @@  static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
         switch ( boot_cpu_data.x86_vendor )
         {
         case X86_VENDOR_INTEL:
-            ret = vmce_intel_wrmsr(v, msr, val);
+            ret = IS_ENABLED(CONFIG_INTEL) ?
+                  vmce_intel_wrmsr(v, msr, val) : -ENODEV;
             break;
 
         case X86_VENDOR_AMD:
         case X86_VENDOR_HYGON:
-            ret = vmce_amd_wrmsr(v, msr, val);
+            ret = IS_ENABLED(CONFIG_AMD) ?
+                  vmce_amd_wrmsr(v, msr, val) : -ENODEV;
             break;
 
         default: