From patchwork Wed Apr 3 03:43:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E91E51669 for ; Wed, 3 Apr 2019 03:45:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D241E289A2 for ; Wed, 3 Apr 2019 03:45:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C64FF289B9; Wed, 3 Apr 2019 03:45:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 79619289A2 for ; Wed, 3 Apr 2019 03:45:30 +0000 (UTC) Received: from localhost ([127.0.0.1]:51514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWq9-0003qZ-K5 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:45:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48452) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWoo-0002c4-P4 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWon-0007mW-SY for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:06 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWon-0007lf-Lo for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:05 -0400 Received: by mail-pl1-x644.google.com with SMTP id w23so4370461ply.4 for ; Tue, 02 Apr 2019 20:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=eEcb3jpHhBL5V4XKribm6nF4P3y4UD0GK5XfT/XCp8U=; b=B90uKOmqgF7EsJHr8jSCfUoZlwOmSDsOZZtu6n0roECm9uhF5MwZQEW/64NwI9+LU8 e0+YUXJh2N9qzqCCZEZyZXmtjw601kvBv43pZM1CiepuZAm2C2LT/QLuglE9g6r93275 pp5tsptbbK8+x5KHBosJhGSZE8IFY6Lq0tyCOQkw5DbffPsnH4JtSaJ5PMA0NzXrZ6Al F2Bmw/HCk2t9O2Kb14udtmaK1ydmxcf+9uKvjQTE7Tov2uKjgocLkNPxeV8d3sqrjuan QN1VjGYe5n0mCia7Gxa1Z/zJPt9w8gu0H36NtYc5Kl+N7yWsD5E03oUhXUBiFLbmd6pZ fHqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=eEcb3jpHhBL5V4XKribm6nF4P3y4UD0GK5XfT/XCp8U=; b=ZNoMOUXfjVT3HPQ2eEViaRA2/9wm1NR1QSKsNP3c/4rneac50td0R1KJTICAQGiRqn YyhNswATuQaXuMiYqDDgbpzG6Ty9IX/sn0f1yxL+OQ43/Sk25ubfdhPSEbOAuRbviuQf EFkD+MMmiJ5GMsUMHVCJJYZ+n1+kWUHHrhE54Q4GqCnnKma8Jdd1Dco6ywROpqREixj2 +UGI/N8h14mNRUYVDd3lJ8GFvaHIRWdF1hzcF08bTs5/u1WNA1AViBc/76Ee3T4NNdUp g1wqICkFMFCG34KeH9ToO3lJRu2ONleK/lR24oQbIY1DNdMVEn0kEbDk3Sgy5xWNt1OE KbmA== X-Gm-Message-State: APjAAAWHtveauEHGUpyGZm9q0JG17jQxsHlJDkbN6XH2h9VmI+TdsFQ/ 1rgxnxGskEffLFXglVjYf0FpPt7u8DuH1g== X-Google-Smtp-Source: APXvYqxHNoo1OGMoBga8gXSx2GmDGLfgLuUQMnJMLrRffRppt994bMDvW/iSZokYDe8ziicfnZ98iQ== X-Received: by 2002:a17:902:2bab:: with SMTP id l40mr74190163plb.273.1554263044391; Tue, 02 Apr 2019 20:44:04 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:33 +0700 Message-Id: <20190403034358.21999-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 01/26] tcg: Assert h2g_valid for 32-bit guest on 64-bit host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP For this combination, we can tell whether or not the address being accessed is within the 4GB range that is accessible by the guest. Otherwise the fault must be elsewhere in qemu, accessing qemu data structures. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0789984fe6..fa9380a380 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,6 +143,15 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, } } + /* + * For a 32-bit guest on a 64-bit host, the set of addresses that we + * access on behalf of the guest is constrained. Anything outside + * that range is a bug elsewhere in QEMU. + */ +#if TARGET_LONG_BITS == 32 && HOST_LONG_BITS == 64 + g_assert(h2g_valid(address)); +#endif + /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ address = h2g_nocheck(address); From patchwork Wed Apr 3 03:43:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882639 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F59D1390 for ; Wed, 3 Apr 2019 03:48:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 26585289B5 for ; Wed, 3 Apr 2019 03:48:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1ABCB289A2; Wed, 3 Apr 2019 03:48:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 863A9289A2 for ; Wed, 3 Apr 2019 03:48:41 +0000 (UTC) Received: from localhost ([127.0.0.1]:52273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWtE-0006aA-RN for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:48:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWor-0002cK-1w for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWop-0007sc-QD for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:08 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46015) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWop-0007ob-HH for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:07 -0400 Received: by mail-pg1-x541.google.com with SMTP id y3so7573750pgk.12 for ; Tue, 02 Apr 2019 20:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=a1RF8tzN4d+znSGg74/q0NFp8F7G9Ydq9o76y67KjZ4=; b=C9gLXxmPxjYURlpbxZK/cZU+3YqdbQmJlqUN+tCRs5VW8+hzfS0i5mLI8ZxFlbo60U Www/huG0VS5r7O8thn7/hLlrYekz493kzZUtIBxfGqjlLZQF9/63RAougs3K+NNOgpnM hexfA4PLEZHEonCJ4YkliPyksQiSS6cssUgISfosquFOiiB6s3hcGiWhoZAWvD4p/cZt Zs3BF46pFIOehsqjckPRbmekvZFPK3IzoHdRwftFmRYxCgb1ojkngVtGpCLuY0+DReSw H7Zs1CJXWw4CHFRGGsJ3MFe0nF7E910zLhKhE/ciyubGpnFMFK9Lu24pXjc/yCy/5eaN DzLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=a1RF8tzN4d+znSGg74/q0NFp8F7G9Ydq9o76y67KjZ4=; b=p+TiQM9/TsoImGgA0xv7M2zGBOACKhO2l/7jWr3ONFArvgMek/07qAzy0f+/LfIqeX lSA2EPKPnPkav4tcnxJN+bqnbMCTGY+echZNvYzhqJU9pf5FyzUvyG9VzNG+tErWIzAQ W3eTuVcUh40M/LbgvbVoMYdvEPok/6Bh65k/9eOtmG3fgrX3tZZD5TIFmXdMtR6ypJrq 7mq2Kz2hm/4nmhEYIQQqdKAp+ili0pGNI5cGUsb/8EMYsBybojjdHe9r32vUv5uTwY21 wNu2Zy4xUX4oV/iAhNV4oT++EdbfPyBIcDz/BjshNEaJO7Iw9vSUw/mMK9W5CtDEmwUr CW4A== X-Gm-Message-State: APjAAAWooWCr7pd+MfNENlatfVSU3I0oJ9X4Bf6ebkfYHHKyzFthHh1g N0LZrwAA2RLIfNxwyO1EhojVmfHReVXOYA== X-Google-Smtp-Source: APXvYqy4OxlDCc7bstbO2hHVzT8pLOVv1vsOHVhHbTpAoa93kXRa8t4vRMLItA8v9Ym5Q/vPY/0QKA== X-Received: by 2002:a62:b602:: with SMTP id j2mr59683619pff.68.1554263046136; Tue, 02 Apr 2019 20:44:06 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:34 +0700 Message-Id: <20190403034358.21999-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 02/26] tcg: Add CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This hook will replace the (user-only mode specific) handle_mmu_fault hook, and the (system mode specific) tlb_fill function. The handle_mmu_fault hook was written as if there was a valid way to recover from an mmu fault, and had 3 possible return states. In reality, the only valid action is to raise an exception, return to the main loop, and delver the SIGSEGV to the guest. Using the hook for system mode requires that all targets be converted, so for now the hook is (optionally) used only from user-only mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/qom/cpu.h | 9 +++++++++ accel/tcg/user-exec.c | 42 ++++++++++++++---------------------------- 2 files changed, 23 insertions(+), 28 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1d6099e5d4..7e96a0aed3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -119,6 +119,12 @@ struct TranslationBlock; * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). * @handle_mmu_fault: Callback for handling an MMU fault. + * @tlb_fill: Callback for handling a softmmu tlb miss or user-only + * address fault. For system mode, if the access is valid, call + * tlb_set_page and return true; if the access is invalid, and + * probe is true, return false; otherwise raise an exception and + * do not return. For user-only mode, always raise an exception + * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the * associated memory transaction attributes to use for the access. @@ -194,6 +200,9 @@ typedef struct CPUClass { void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, int mmu_index); + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fa9380a380..f13c0b2b67 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -65,6 +65,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, CPUClass *cc; int ret; unsigned long address = (unsigned long)info->si_addr; + MMUAccessType access_type; /* We must handle PC addresses from two different sources: * a call return address and a signal frame address. @@ -151,40 +152,25 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, #if TARGET_LONG_BITS == 32 && HOST_LONG_BITS == 64 g_assert(h2g_valid(address)); #endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ address = h2g_nocheck(address); - cc = CPU_GET_CLASS(cpu); - /* see if it is an MMU fault */ - g_assert(cc->handle_mmu_fault); - ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); - - if (ret == 0) { - /* The MMU fault was handled without causing real CPU fault. - * Retain helper_retaddr for a possible second fault. - */ - return 1; - } - - /* All other paths lead to cpu_exit; clear helper_retaddr - * for next execution. + /* + * There is no way the target can handle this other than raising + * an exception. Undo signal and retaddr state prior to longjmp. */ + sigprocmask(SIG_SETMASK, old_set, NULL); helper_retaddr = 0; - if (ret < 0) { - return 0; /* not an MMU fault */ + cc = CPU_GET_CLASS(cpu); + if (cc->tlb_fill) { + access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); + g_assert(ret > 0); + cpu_loop_exit_restore(cpu, pc); } - - /* Now we have a real cpu fault. */ - cpu_restore_state(cpu, pc, true); - - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit(cpu); - - /* never comes here */ - return 1; } #if defined(__i386__) From patchwork Wed Apr 3 03:43:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 664B71390 for ; Wed, 3 Apr 2019 03:48:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B367289A2 for ; Wed, 3 Apr 2019 03:48:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3F81D289B9; Wed, 3 Apr 2019 03:48:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A6F08289A2 for ; Wed, 3 Apr 2019 03:48:36 +0000 (UTC) Received: from localhost ([127.0.0.1]:52252 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWt9-0006We-UJ for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:48:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWou-0002f5-8h for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWos-0007zp-VG for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:12 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:36144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWos-0007yC-LP for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:10 -0400 Received: by mail-pl1-x643.google.com with SMTP id ck15so6123252plb.3 for ; Tue, 02 Apr 2019 20:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=T6WPmTFnuwgmwKqzFLAzjRNZe3eRbqRWr6UuIt9sYlM=; b=xFz3J8YrLOLm+tcDP5rnM6XDE8qfNRgargi75XIc16Jxmy0YKJlW49n0Ym6Rji7XnF PrNdjmsZsH/NGzAfM1+QVmTq6Md0f2iNoCz00vyccH9Tj+IiyRKFWswT4g5N4NFtgQtm X1YKyK1zNxws/befIXUlwDytyFXeJpHXo5k9g9rHF8vyXvZptOT2qSgr2H2Rmk5Wf1k3 SfHCMVxaxsxFUlaDNpnku9Nm8LleEGQmMKsP56X/mX/gWDAKgHAwixio20lvztMuF/29 +bWiHGBf+L02duOSwsdmn0psXo3TxKYMV9kZ7RQWByx7b/i7zV8T3GVtW2GXSo9dAVye OPwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=T6WPmTFnuwgmwKqzFLAzjRNZe3eRbqRWr6UuIt9sYlM=; b=lcaboa2O28EWzyU35VV1DRvSyCLe+mbUvsqC6NI03ZfQa5rcgYS73xukrho2du57Xb QRB6XhjY8xIyEUU6IG2SKe1pTWKBAzsTKiUl5VN7SF/QG8eV2oYmT9SPgGYc5UjMdjlE bdaiYsdnAwlrZA2XphAJ7HKqBgQ4WNTN+R4Fu42Zr+qo4zH2MNLvKHQOEufBn5PBKy7l Z7dYkOeO3M60JZs+ztZwj9GJd3xWb2OVDKkZ/IH3w0yW/Aj+QQnw0NdmYAlG80hwTDAT OWqUMbz/o/GDPeqJNzF+xhPBQkyNvzf5z1kx+o4ZY5J5xINoqr/m/kgLldaVnVQwRCo8 QrHA== X-Gm-Message-State: APjAAAX04r+EleQLpic6x9ciwnMe8kteWDniwENk6+h8Txax9siEKvpg lnNlUF1UB/WarLnx35XWelnf8OahAf8nQQ== X-Google-Smtp-Source: APXvYqxKMdbZEG06Gn5eBXnR1BhFmcv+hQtZzW1UH6yUaYJ91mvJfpeOmpALgLNdFOnL90Wp3zETDA== X-Received: by 2002:a17:902:8f92:: with SMTP id z18mr21924479plo.123.1554263047845; Tue, 02 Apr 2019 20:44:07 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:35 +0700 Message-Id: <20190403034358.21999-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 03/26] target/alpha: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/alpha/cpu.h | 5 ++-- target/alpha/cpu.c | 5 ++-- target/alpha/helper.c | 50 +++++++++++++++++++++++---------------- target/alpha/mem_helper.c | 16 ------------- 4 files changed, 35 insertions(+), 41 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 7b50be785d..aecf8d75c1 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -476,8 +476,9 @@ void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1fd95d6c0f..5aa4581b9f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -230,9 +230,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; cc->gdb_write_register = alpha_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault; -#else + cc->tlb_fill = alpha_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed = alpha_cpu_do_transaction_failed; cc->do_unaligned_access = alpha_cpu_do_unaligned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 57e2c212b3..e54197d5fb 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -102,17 +102,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) *cpu_alpha_addr_gr(env, reg) = val; } -#if defined(CONFIG_USER_ONLY) -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - AlphaCPU *cpu = ALPHA_CPU(cs); - - cs->exception_index = EXCP_MMFAULT; - cpu->env.trap_arg0 = address; - return 1; -} -#else +#ifndef CONFIG_USER_ONLY /* Returns the OSF/1 entMM failure indication, or -1 on success. */ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, @@ -246,29 +236,49 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); return (fail >= 0 ? -1 : phys); } +#endif /* !USER_ONLY */ -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw, - int mmu_idx) +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { AlphaCPU *cpu = ALPHA_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cs->exception_index = EXCP_MMFAULT; + cpu->env.trap_arg0 = address; + cpu_loop_exit_restore(cs, retaddr); +#else CPUAlphaState *env = &cpu->env; target_ulong phys; int prot, fail; - fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot); + fail = get_physical_address(env, address, 1 << access_type, + mmu_idx, &phys, &prot); if (unlikely(fail >= 0)) { + if (probe) { + return false; + } cs->exception_index = EXCP_MMFAULT; - env->trap_arg0 = addr; + env->trap_arg0 = address; env->trap_arg1 = fail; - env->trap_arg2 = (rw == 2 ? -1 : rw); - return 1; + env->trap_arg2 = (access_type == MMU_INST_FETCH ? -1 : access_type); + cpu_loop_exit_restore(cs, retaddr); } - tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; +#endif } -#endif /* USER_ONLY */ + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif void alpha_cpu_do_interrupt(CPUState *cs) { diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 011bc73dca..934faa1d6f 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -62,20 +62,4 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret != 0)) { - /* Exception index and error code are already set */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif /* CONFIG_USER_ONLY */ From patchwork Wed Apr 3 03:43:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882633 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA4651390 for ; Wed, 3 Apr 2019 03:45:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC206289A2 for ; Wed, 3 Apr 2019 03:45:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C0A70289B9; Wed, 3 Apr 2019 03:45:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 09A4D289A2 for ; Wed, 3 Apr 2019 03:45:53 +0000 (UTC) Received: from localhost ([127.0.0.1]:51558 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWqW-00042o-Ai for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:45:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWov-0002ff-2z for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWot-000812-IX for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:13 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:36188) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWot-0007zL-9O for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:11 -0400 Received: by mail-pg1-x544.google.com with SMTP id 85so7592852pgc.3 for ; Tue, 02 Apr 2019 20:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TcaPmSrwhcdn8wz+i6qqtqby6cFp9SRTGijL0/DhbE8=; b=GQjvsQmF3N177bJWt25YG8wSuGo+CsFWXPD1YmQiWvLOlz9elshSFJyC2zyBiK01NK fo+RncvwsVKK7mIkYKDHTCjI0IkaTZ8PBEYhds/3P+0SM3uprzi6NMwB0ZBTvUcLZ5go EmSG7wQUR1cI6ZuM2V+IxGnTKt0XAPqUsutLXetawBjink8t5nMVzeT7eVDBR0Nq7hbg FlygeNMCrcZ9x6nJhnZmy6vWuWhYNlONm5jmlh9G0eSjsrtJRp0oFvb4KuoX/dBlLkyQ 8TGy15Jh/8Nk1/5mIgDVNXPMmquBpL/gnNFUDDu2E1x3gkNCqSnJJB8pE5T/Z3NKFy2N plEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TcaPmSrwhcdn8wz+i6qqtqby6cFp9SRTGijL0/DhbE8=; b=avypSoKCUQPeXd6KKbvg2QHpMH2BsAN/YyEN8GbTCIvWD4c4EAqLBU1iMN9tE4z+aj Onby2Pq1XzQCyvb0rRZkB9Aqf1F9RsZDyvIiM+yIx2sJ1BNAtUAZ40WrH+9WIZoCGZ+8 5Czfb/HfunubVTNF6PG54X1F/Sm3UU8Rczcx+nK5kKTSV0MAhjOd1V/SpVLooxb9ZiCH sYfF47EWVkIEhVKGLH1cgLEo/k8E03/Hhg/t1HoJVwT5qd1EWA7kB1kOGVBgwQqfhBJN 6GJemlhEBM4jrQtk65va837JCVv693lyFhtx6p2rcTzvA06fxSNxdxaMxI4dCV1ES56X J2pQ== X-Gm-Message-State: APjAAAXRJLI3Jjxp8rQf7A9KhRIrSf0gE0atj/OhkDLhmQODwpoWnDVt jq8J+ZwESREpLMjg4v/GpEKrtx2drLbXZg== X-Google-Smtp-Source: APXvYqyWs/gJDVEeeE8v6AO/vwYpW6iVcoysYofK/eRLl6neRX3LQmWVoFFTxNB6zeMsjnOP3dCYKQ== X-Received: by 2002:a62:1690:: with SMTP id 138mr33373431pfw.28.1554263049840; Tue, 02 Apr 2019 20:44:09 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:36 +0700 Message-Id: <20190403034358.21999-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 04/26] target/arm: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: qemu-arm@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 10 +++-- target/arm/cpu.c | 22 +--------- target/arm/helper.c | 97 ++++++++++++++++++++++++++---------------- target/arm/op_helper.c | 29 ++----------- 4 files changed, 72 insertions(+), 86 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..5a02f458f3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -761,10 +761,12 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } -/* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi); +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN; /* Return true if the stage 1 translation regime is using LPAE format page * tables */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4155782197..3b87d897a2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2114,23 +2114,6 @@ static Property arm_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; -#ifdef CONFIG_USER_ONLY -static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - env->exception.vaddress = address; - if (rw == 2) { - cs->exception_index = EXCP_PREFETCH_ABORT; - } else { - cs->exception_index = EXCP_DATA_ABORT; - } - return 1; -} -#endif - static gchar *arm_gdb_arch_name(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); @@ -2163,9 +2146,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; cc->gdb_read_register = arm_cpu_gdb_read_register; cc->gdb_write_register = arm_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; -#else + cc->tlb_fill = arm_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_cpu_do_interrupt; cc->do_unaligned_access = arm_cpu_do_unaligned_access; cc->do_transaction_failed = arm_cpu_do_transaction_failed; diff --git a/target/arm/helper.c b/target/arm/helper.c index a36f4b3d69..0fc4abc651 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11918,43 +11918,6 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } } -/* Walk the page table and (if the mapping exists) add the page - * to the TLB. Return false on success, or true on failure. Populate - * fsr with ARM DFSR/IFSR fault register format value on failure. - */ -bool arm_tlb_fill(CPUState *cs, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - int ret; - MemTxAttrs attrs = {}; - - ret = get_phys_addr(env, address, access_type, - core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fi, NULL); - if (!ret) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >= TARGET_PAGE_SIZE) { - phys_addr &= TARGET_PAGE_MASK; - address &= TARGET_PAGE_MASK; - } - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return 0; - } - - return ret; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { @@ -12389,6 +12352,66 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) #endif +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress = address; + if (access_type == MMU_INST_FETCH) { + cs->exception_index = EXCP_PREFETCH_ABORT; + } else { + cs->exception_index = EXCP_DATA_ABORT; + } + cpu_loop_exit_restore(cs, retaddr); +#else + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs = {}; + ARMMMUFaultInfo fi = {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. Return false on success, or true on failure. Populate + * fsr with ARM DFSR/IFSR fault register format value on failure. + */ + ret = get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, &fi, NULL); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >= TARGET_PAGE_SIZE) { + phys_addr &= TARGET_PAGE_MASK; + address &= TARGET_PAGE_MASK; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +#endif +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif + void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..8ee15a4bd4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -126,8 +126,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } -static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; int target_el; @@ -179,27 +179,6 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, raise_exception(env, exc, syn, target_el); } -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - bool ret; - ARMMMUFaultInfo fi = {}; - - ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi); - if (unlikely(ret)) { - ARMCPU *cpu = ARM_CPU(cs); - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); - } -} - /* Raise a data fault alignment exception for the specified virtual address */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, @@ -212,7 +191,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, cpu_restore_state(cs, retaddr, true); fi.type = ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } /* arm_cpu_do_transaction_failed: handle a memory system error response @@ -233,7 +212,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, fi.ea = arm_extabort_type(response); fi.type = ARMFault_SyncExternal; - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } #endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Wed Apr 3 03:43:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882635 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 28F7C1390 for ; Wed, 3 Apr 2019 03:46:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CCEC289A2 for ; Wed, 3 Apr 2019 03:46:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00B4D289B9; Wed, 3 Apr 2019 03:46:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5C83E289A2 for ; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 05/26] target/cris: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/cris/cpu.h | 5 +-- target/cris/cpu.c | 5 ++- target/cris/helper.c | 67 +++++++++++++++++++++++------------------ target/cris/op_helper.c | 28 ----------------- 4 files changed, 42 insertions(+), 63 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 8bb1dbc989..f3c3b428ca 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -282,8 +282,9 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } -int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a23aba2688..145c33a85a 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -273,9 +273,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; cc->gdb_write_register = cris_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; -#else + cc->tlb_fill = cris_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; dc->vmsd = &vmstate_cris_cpu; #endif diff --git a/target/cris/helper.c b/target/cris/helper.c index b2dbb2075c..69464837c8 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -24,6 +24,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" //#define CRIS_HELPER_DEBUG @@ -53,15 +54,15 @@ void crisv10_cpu_do_interrupt(CPUState *cs) cris_cpu_do_interrupt(cs); } -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu = CRIS_CPU(cs); cs->exception_index = 0xaa; cpu->env.pregs[PR_EDA] = address; - cpu_dump_state(cs, stderr, fprintf, 0); - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else /* !CONFIG_USER_ONLY */ @@ -76,33 +77,19 @@ static void cris_shift_ccs(CPUCRISState *env) env->pregs[PR_CCS] = ccs; } -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; struct cris_mmu_result res; int prot, miss; - int r = -1; target_ulong phy; - qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n", - __func__, address, env->pc, rw); miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, - rw, mmu_idx, 0); - if (miss) { - if (cs->exception_index == EXCP_BUSFAULT) { - cpu_abort(cs, - "CRIS: Illegal recursive bus fault." - "addr=%" VADDR_PRIx " rw=%d\n", - address, rw); - } - - env->pregs[PR_EDA] = address; - cs->exception_index = EXCP_BUSFAULT; - env->fault_vector = res.bf_vec; - r = 1; - } else { + access_type, mmu_idx, 0); + if (likely(!miss)) { /* * Mask off the cache selection bit. The ETRAX busses do not * see the top bit. @@ -111,15 +98,35 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, prot = res.prot; tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - r = 0; + return true; } - if (r > 0) { - qemu_log_mask(CPU_LOG_MMU, - "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" - " pc=%x\n", __func__, r, cs->interrupt_request, address, - res.phy, res.bf_vec, env->pc); + + if (probe) { + return false; } - return r; + + if (cs->exception_index == EXCP_BUSFAULT) { + cpu_abort(cs, "CRIS: Illegal recursive bus fault." + "addr=%" VADDR_PRIx " access_type=%d\n", + address, access_type); + } + + env->pregs[PR_EDA] = address; + cs->exception_index = EXCP_BUSFAULT; + env->fault_vector = res.bf_vec; + if (retaddr) { + if (cpu_restore_state(cs, retaddr, true)) { + /* Evaluate flags after retranslation. */ + helper_top_evaluate_flags(env); + } + } + cpu_loop_exit(cs); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } void crisv10_cpu_do_interrupt(CPUState *cs) diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 0ee3a3117b..26a395b413 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -37,34 +37,6 @@ #define D_LOG(...) do { } while (0) #endif -#if !defined(CONFIG_USER_ONLY) -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; - int ret; - - D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__, - env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret = cris_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - if (cpu_restore_state(cs, retaddr, true)) { - /* Evaluate flags after retranslation. */ - helper_top_evaluate_flags(env); - } - } - cpu_loop_exit(cs); - } -} - -#endif - void helper_raise_exception(CPUCRISState *env, uint32_t index) { CPUState *cs = CPU(cris_env_get_cpu(env)); From patchwork Wed Apr 3 03:43:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882643 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F15B1390 for ; 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Tue, 02 Apr 2019 20:44:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:38 +0700 Message-Id: <20190403034358.21999-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 06/26] target/hppa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/cpu.h | 8 ++++---- target/hppa/cpu.c | 5 ++--- target/hppa/mem_helper.c | 22 +++++++++++++++++----- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c062c7969c..e0e5d879e1 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -360,10 +360,10 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); -#ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int midx); -#else +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#ifndef CONFIG_USER_ONLY int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 00bf444620..46750980f7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -167,9 +167,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; cc->gdb_read_register = hppa_cpu_gdb_read_register; cc->gdb_write_register = hppa_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; -#else + cc->tlb_fill = hppa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; dc->vmsd = &vmstate_hppa_cpu; #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c9b57d07c3..f61b0fdb9f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -25,8 +25,9 @@ #include "trace.h" #ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int size, int rw, int mmu_idx) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu = HPPA_CPU(cs); @@ -34,7 +35,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, which would affect si_code. */ cs->exception_index = EXCP_DMP; cpu->env.cr[CR_IOR] = address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) @@ -214,8 +215,9 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return excp == EXCP_DTLB_MISS ? -1 : phys; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; @@ -237,6 +239,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >= 0)) { + if (probe) { + return false; + } trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ cs->exception_index = excp; @@ -253,6 +258,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType type, int mmu_idx, uintptr_t retaddr) +{ + hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); } /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ From patchwork Wed Apr 3 03:43:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882641 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 466FA17E1 for ; Wed, 3 Apr 2019 03:48:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B7D7289A2 for ; Wed, 3 Apr 2019 03:48:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1EA55289B9; Wed, 3 Apr 2019 03:48:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 80FE3289A2 for ; Wed, 3 Apr 2019 03:48:50 +0000 (UTC) Received: from localhost ([127.0.0.1]:52317 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWtN-0006iy-T0 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:48:49 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWp0-0002lM-PU for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWoz-0008CA-FK for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:18 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:45149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWoz-0008An-5e for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:17 -0400 Received: by mail-pg1-x535.google.com with SMTP id y3so7573902pgk.12 for ; Tue, 02 Apr 2019 20:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=03y4rJUeRFEukrKOoroIoXi8bqiR++D8zkd8dBnyBJA=; b=fZfC+CaPjBIEPxmpuoAB07jDoqpFjlvqU6lkNcSZdMw7xEofoGUjEJlahQJ+phS96j t47N3NPkVycbwK+Ky7x1RPFOeu17VdsuzwoRM4fa4kH/zFX15gPckR1XZeNb85S8IUvq NdiU20k8Zl/zWFrR69fMCMtlguvWwYTK+U4RLIblVe3HPOj1hdwJb5VetT+F7vn5Ermf huqFrWeTSuOzQnadZgfNwfnvj222Th7rOU4+kcPAO1osPfKYKhlpwknsg2ZGc7Od8tPN iO1+N4sNQkUhiFPDOEoy8ayrqO+GipwQVzhHWmLBrT6WM6eyBFef2MImQJU9o10dvtU4 Y8Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=03y4rJUeRFEukrKOoroIoXi8bqiR++D8zkd8dBnyBJA=; b=RKA3wsTeym61aGbTyjKCa/ldITHL0m5KAaXlGL7UmVD5B1IvuSyqeKxgSnkyMB0oY8 8jvXyDNFoC+DPPjYn02r77m2kCi/D0lMbVwgiYYHC7TXQLJVCegQHLZbauphqNyadY+6 WMpzAUQeA/rlTy2vdeacO8iAvgPNiYZqFpTCNR8OYXXcPVhA124q0+tAxjq70eJvA9DS VrtsK4YW6qTvYrSmqQKUL8QNZBvnnxZ4zMJQRb8a5V7/O3TWemcXiKZ8ZA4Bp+i2mFbZ neCbjA8bHz6wX3L3xsYeGdp8WQDPG7jneWGHfKfKCkFqfFd+LUGGycmDtvpBJxhcit42 9BPg== X-Gm-Message-State: APjAAAU5ifJ1Aj3YeZlRI/nTEwawmngAEFZMZvSvoTdRXrlFCEgmcO1T J8j3cN1NLV+GZ0lakyt1qrCbbzTTGr3a8Q== X-Google-Smtp-Source: APXvYqyz+vCCyenHu3KdAkhWohgUEL6ZWrJJK+mPaqju1+NfG0U0PrHmZbz9VnvVwBI7JlR8RRbreg== X-Received: by 2002:a63:1003:: with SMTP id f3mr60438287pgl.227.1554263055737; Tue, 02 Apr 2019 20:44:15 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:39 +0700 Message-Id: <20190403034358.21999-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PATCH 07/26] target/i386: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP We do not support probing, but we do not need it yet either. Cc: Paolo Bonzini Cc: Eduardo Habkost Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/i386/cpu.h | 5 ++-- target/i386/cpu.c | 5 ++-- target/i386/excp_helper.c | 61 +++++++++++++++++++++++++-------------- target/i386/mem_helper.c | 21 -------------- 4 files changed, 44 insertions(+), 48 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 83fb522554..1ce070ceb9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1655,8 +1655,9 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); /* helper.c */ -int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, - int is_write, int mmu_idx); +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d6bb57d210..237bd88710 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5866,9 +5866,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = x86_cpu_gdb_write_register; cc->get_arch_id = x86_cpu_get_arch_id; cc->get_paging_enabled = x86_cpu_get_paging_enabled; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = x86_cpu_handle_mmu_fault; -#else + cc->tlb_fill = x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->asidx_from_attrs = x86_asidx_from_attrs; cc->get_memory_mapping = x86_cpu_get_memory_mapping; cc->get_phys_page_debug = x86_cpu_get_phys_page_debug; diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 49231f6b69..6f59b7bafc 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -137,26 +137,7 @@ void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } -#if defined(CONFIG_USER_ONLY) -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write, int mmu_idx) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - - /* user mode only emulation */ - is_write &= 1; - env->cr[2] = addr; - env->error_code = (is_write << PG_ERROR_W_BIT); - env->error_code |= PG_ERROR_U_MASK; - cs->exception_index = EXCP0E_PAGE; - env->exception_is_int = 0; - env->exception_next_eip = -1; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, int *prot) { @@ -365,8 +346,8 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, * 0 = nothing more to do * 1 = generate PF fault */ -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write1, int mmu_idx) +static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, + int is_write1, int mmu_idx) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; @@ -691,3 +672,39 @@ do_check_protect_pse36: return 1; } #endif + +bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + +#ifdef CONFIG_USER_ONLY + /* user mode only emulation */ + env->cr[2] = addr; + env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; + env->error_code |= PG_ERROR_U_MASK; + cs->exception_index = EXCP0E_PAGE; + env->exception_is_int = 0; + env->exception_next_eip = -1; + cpu_loop_exit_restore(cs, retaddr); +#else + env->retaddr = retaddr; + if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) { + /* FIXME: On error in get_hphys we have already jumpped out. */ + g_assert(!probe); + raise_exception_err_ra(env, cs->exception_index, + env->error_code, retaddr); + } + return true; +#endif +} + +#if !defined(CONFIG_USER_ONLY) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 6cc53bcb40..1885df29d2 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -191,24 +191,3 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) raise_exception_ra(env, EXCP05_BOUND, GETPC()); } } - -#if !defined(CONFIG_USER_ONLY) -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - int ret; - - env->retaddr = retaddr; - ret = x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); - } -} -#endif From patchwork Wed Apr 3 03:43:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D7F317E1 for ; Wed, 3 Apr 2019 03:52:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 215A7289DC for ; Wed, 3 Apr 2019 03:52:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15CAE289F9; Wed, 3 Apr 2019 03:52:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7AF49289E2 for ; Wed, 3 Apr 2019 03:52:21 +0000 (UTC) Received: from localhost ([127.0.0.1]:53181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWwm-0001LS-Np for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:52:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWp2-0002mr-AN for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWp1-0008FF-7i for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:20 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:40014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWp0-0008DM-Uq for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:19 -0400 Received: by mail-pl1-x642.google.com with SMTP id b3so4337150plr.7 for ; Tue, 02 Apr 2019 20:44:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lVkBfrW6VirLiLfiWJMR0NKgqluxD319D02OYmRqkHk=; b=iCFXyCbS1vbtRw+2CberFCqQN292mqQlg+9c56VNasnRgL2D0Ud+/Ocq18M4KSn3qY lg31cRrKIWSlxppKaKLclAE5QhQ8YV4MQgMdvF+kd2OBDIoibKLYrtIKjR99wBR6CMGg 7POC8kJX09bBfOLWL4rnyTTYP2an9FN9pRsvxjj3Dlqv25148F//gd7Y8inv+wZLXgax rxKoxEhsmZ+YGLxXr9fXwSiCZdj+4N6gwruAeutb911HX35/w4+lLDG1mbw8XDohT9tl qalTgOyfmwxv0KKRXnM4UNeReLg6+NLH4e3Ts+JvD6w8FhoEjEIUuJwWyKg6ErCCySPV vl6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lVkBfrW6VirLiLfiWJMR0NKgqluxD319D02OYmRqkHk=; b=ph6DgE7uh3zyPMYOtV1S/734m/zIDu2tur36nPjMaOtqnS2ZgLXa1whyG0UAsRAIez uANIYP4N+2g54n0CGcgqNv2622gLXs+iqUbQOt1mY0Q2fS86A1C2lrlvZVKXNt/HAir7 64ytuqtpvjaeVn1yRGnaCynx2AMfq/oHkT+t8HaklULm8KscNR4LmGlx1IoHH6joX/Ds A9Ocsx3bsMgrH9R0YWgJsVkpMMeMOGcEg9vhYKxameOf6TaFi5i1cJT3JGnaoboBqkqm 4vTjWMGLUi45XEOjTQ6XaQf5ukyRQq7cxCfXtqgTv1v548eACdPlP7jOs2I5g/6vJeQc lU4Q== X-Gm-Message-State: APjAAAVSWdhjpW0tFkVZNyRhlNsKNLPuFtKoSQv0w7sd7FiRqWha1w8m ObwDOjZyJKZMOFHtyN3vHzjtJi4rh+mByA== X-Google-Smtp-Source: APXvYqz0W/1QXfUT1K4PudTGV6lyHxvxSOt148eNg/5QqpRW4d7wijvtQQHEzJPgZOk3Qngto34iLQ== X-Received: by 2002:a17:902:a5ca:: with SMTP id t10mr26491437plq.234.1554263057638; Tue, 02 Apr 2019 20:44:17 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:40 +0700 Message-Id: <20190403034358.21999-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 08/26] target/lm32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Walle Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Michael Walle Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/lm32/cpu.h | 5 +++-- target/lm32/cpu.c | 5 ++--- target/lm32/helper.c | 12 +++++++++--- target/lm32/op_helper.c | 16 ---------------- 4 files changed, 14 insertions(+), 24 deletions(-) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 66157eefe9..7cc279bcd0 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -262,8 +262,9 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_signal_handler cpu_lm32_signal_handler -int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #include "exec/cpu-all.h" diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b7499cb627..6d2a176c87 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -235,9 +235,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; cc->gdb_write_register = lm32_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault; -#else + cc->tlb_fill = lm32_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; #endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index a039a993ff..1db9a5562e 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -25,8 +25,9 @@ #include "exec/semihost.h" #include "exec/log.h" -int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { LM32CPU *cpu = LM32_CPU(cs); CPULM32State *env = &cpu->env; @@ -40,8 +41,13 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, } else { tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); } + return true; +} - return 0; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 234d55e056..be12b11b02 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -143,21 +143,5 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) { return lm32_juart_get_jrx(env->juart_state); } - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = lm32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif From patchwork Wed Apr 3 03:43:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 01C701708 for ; Wed, 3 Apr 2019 03:55:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D7D132846C for ; Wed, 3 Apr 2019 03:55:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C82262896A; Wed, 3 Apr 2019 03:55:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1F4812846C for ; Wed, 3 Apr 2019 03:55:19 +0000 (UTC) Received: from localhost ([127.0.0.1]:53944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWze-0003eu-Cl for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:55:18 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48610) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWp4-0002oz-NJ for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWp3-0008Hq-8o for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:22 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42486) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWp2-0008Gx-T1 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:21 -0400 Received: by mail-pf1-x441.google.com with SMTP id r15so7415176pfn.9 for ; Tue, 02 Apr 2019 20:44:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cqLJBmieT/JY9FOcf60NXGKLtJWacSntKsw5Msw8hSU=; b=TgvOpAzsNZ4c53HmGWSwyFUuOlQoh+cmr5GXpoS7qzA7ZcTwwvLmlcjxb3Ckk6ZU0U 2Hcry2HICt3arfbZw1PsgrIvNoXR7LMZvIUlNnxFdZzXE9zCAU66aiPXLyxdxmPjch5G +SBnt4Ql4Z74KNYgd7w651OhDOeNNaSKrj6qxIFA6t2HDwq/yqtI+4WLNrKa2OLqoDY5 ucWwyhdLizY3QfIxQXD0iO4cnwW6cmT5hzqkGhz1la1+c3gsWnC36KJ4uUDv9jqBnn3L e9StrSBGInH/R3AmP4WeWIaLfpfvx0HieKjUbRlu4a9Lvh3BNEIzHve4idvFQQRxsokw Obxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cqLJBmieT/JY9FOcf60NXGKLtJWacSntKsw5Msw8hSU=; b=H3ReBAObSMFOzSwkHFznLkgO8sFpI7MWasqzHqLGzE5aOQ4yedWtmWPClMCgVd9pkb bY1mrm5m0alr/n8XIPvrr3fmEz59xIpXL/IIWvHMKOmzuLu2BuMW/mNabg+6CwvhLZe2 gQjRWE03ysuJ4kYmlL9Q7TOxroraYYn0YOVvNjrgYMXpb3KYDX8jxNncow1zYMZNrsR5 cpWAxNLBGgwky7ETmCkwsOgY3nQi2sDZmCG6cR7tWmSq7M4rIpoOaMXk51eW3+jNY/pp u53V+rcn8Kw1Qt9um5tycH3o9K8VS7ceUJaNqKncTOeEv5xEffKNA0z2Sw4xKrbAPhoA BX7w== X-Gm-Message-State: APjAAAVX+Y29csro/3LzlJ74ASGDcBOqosxq9GpSbZ5IuMOIfPwpuGsU KGjwCMFbLcezNcWdOUkI3LK+AuAyr/XtZg== X-Google-Smtp-Source: APXvYqxNVJAA7HnAB4QcIEYpu7F+RQGogZpmZnt1Ks8fIeLp2NxMFlKLiqeyCFxSGEeWZs8CbFwGlQ== X-Received: by 2002:a63:5466:: with SMTP id e38mr42992540pgm.340.1554263059661; Tue, 02 Apr 2019 20:44:19 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:41 +0700 Message-Id: <20190403034358.21999-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 09/26] target/m68k: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Laurent Vivier Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/m68k/cpu.h | 5 ++- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 87 ++++++++++++++++++++++------------------- target/m68k/op_helper.c | 15 ------- 4 files changed, 50 insertions(+), 59 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index f154565117..663c4c0307 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -543,8 +543,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) return (env->sr & SR_S) == 0 ? 1 : 0; } -int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 582e3a73b3..6f441bc973 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -269,7 +269,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; cc->gdb_write_register = m68k_cpu_gdb_write_register; - cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault; + cc->tlb_fill = m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_unassigned_access = m68k_cpu_unassigned_access; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 3e26d337bf..9768b4517f 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -359,20 +359,7 @@ void m68k_switch_sp(CPUM68KState *env) env->current_sp = new_sp; } -#if defined(CONFIG_USER_ONLY) - -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - M68kCPU *cpu = M68K_CPU(cs); - - cs->exception_index = EXCP_ACCESS; - cpu->env.mmu.ar = address; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) /* MMU: 68040 only */ static void print_address_zone(FILE *f, fprintf_function cpu_fprintf, @@ -804,11 +791,36 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +/* + * Notify CPU of a pending interrupt. Prioritization and vectoring should + * be handled by the interrupt controller. Real hardware only requests + * the vector when the interrupt is acknowledged by the CPU. For + * simplicitly we calculate it when the interrupt is signalled. + */ +void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +{ + CPUState *cs = CPU(cpu); + CPUM68KState *env = &cpu->env; + + env->pending_level = level; + env->pending_vector = vector; + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +#endif + +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType qemu_access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; + +#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -821,32 +833,35 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, address & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } - if (rw == 2) { + if (qemu_access_type == MMU_INST_FETCH) { access_type = ACCESS_CODE; - rw = 0; } else { access_type = ACCESS_DATA; - if (rw) { + if (qemu_access_type == MMU_DATA_STORE) { access_type |= ACCESS_STORE; } } - if (mmu_idx != MMU_USER_IDX) { access_type |= ACCESS_SUPER; } ret = get_physical_address(&cpu->env, &physical, &prot, address, access_type, &page_size); - if (ret == 0) { + if (likely(ret == 0)) { address &= TARGET_PAGE_MASK; physical += address & (page_size - 1); tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } + + if (probe) { + return false; + } + /* page fault */ env->mmu.ssw = M68K_ATC_040; switch (size) { @@ -871,29 +886,19 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |= M68K_RW_040; } - env->mmu.ar = address; +#endif + cs->exception_index = EXCP_ACCESS; - return 1; + env->mmu.ar = address; + cpu_loop_exit_restore(cs, retaddr); } -/* Notify CPU of a pending interrupt. Prioritization and vectoring should - be handled by the interrupt controller. Real hardware only requests - the vector when the interrupt is acknowledged by the CPU. For - simplicitly we calculate it when the interrupt is signalled. */ -void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUState *cs = CPU(cpu); - CPUM68KState *env = &cpu->env; - - env->pending_level = level; - env->pending_vector = vector; - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } + m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } - #endif uint32_t HELPER(bitrev)(uint32_t x) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 76f439985a..d421614727 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -36,21 +36,6 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) #else -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = m68k_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - static void cf_rte(CPUM68KState *env) { uint32_t sp; From patchwork Wed Apr 3 03:43:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A86481708 for ; Wed, 3 Apr 2019 03:51:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C15128827 for ; Wed, 3 Apr 2019 03:51:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8058A289EF; Wed, 3 Apr 2019 03:51:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CCEEC289F2 for ; Wed, 3 Apr 2019 03:51:58 +0000 (UTC) Received: from localhost ([127.0.0.1]:53107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWwQ-00015L-3U for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:51:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48622) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWp6-0002qx-Q5 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWp5-0008JO-Br for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:24 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:41862) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWp5-0008Ii-0K for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:23 -0400 Received: by mail-pf1-x442.google.com with SMTP id 188so7431706pfd.8 for ; Tue, 02 Apr 2019 20:44:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RvZL9Bk1/BL1xpfiQMAt2J0TEi4VsVh2Sx8xG9Gdt3Q=; b=la5zkhz+hbRZKlFXVn4uGAisD9zjVNxoAsDOX+FA67ZAp+IapQZqjlMex1xGd3HqaS x09HGzj6nMOx7sTCW+IV0hpX0aFpxU4CsorPqiqFslAaQhn7ULJ1fkFB62OdRzjvUpAO PLWdz2owvuctluyRdU776zNjlpy5htVFnebMqHxq4ioUzPvQ8mxsVwxiEclhP+qDHl2z ErjiwctCIYwQcfNeBQX0y4dCf0G5DlZIKdYHPU8u9mvGsDUxZVjLEeRG5eDxYTz5nniD J1f4iy+imZmPNSeV9nvcX71c4MpizIZtTTyS/0uFgXPev0AD4/DDvkY3kAt7LoUVkgm8 YHtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RvZL9Bk1/BL1xpfiQMAt2J0TEi4VsVh2Sx8xG9Gdt3Q=; b=m+clZh41QzfayJL/hm7Y3yntWvjwG2HwAN5JnBb9nImT2Gl83eDaAvoAKZyAqCcZ0p ktbLHO9TYcHz9wvAYNm/Zu5oUK1MN+pE7K76pGax8yvM8n/snjCX8S5ZM8Eoy/SKZlDo K0Nm63N1kG5OiCFvuOokJUNS3fBSX3so2bE9BtcXX8ltepYau8631KCm8Qnwj14eBYZg qCPPrb0rIhCzmS3IimowkM/Le7QhJj3amEIZgxD7KrDROxEzi5S4Ihphh1yCkFKhqqkc iL7er3wqRhIk04hubWXBXVOAVUGX8PJKfva4XCXR6bFKC0hueiFTBTd1n+e/4CleN+H/ sA1Q== X-Gm-Message-State: APjAAAXBDXa+EuZl0jv0KhP0p9UMMVQbIituEKEsLdowuHwQMdV8uDyd jVIl91xRNl4JmkrxuuRwzdJpZI1WDlxRPA== X-Google-Smtp-Source: APXvYqxinkS1bGxcCq/0fK2EgzB932KB13xMf2519K0sBfqSB1q0Ze+a3VxLRW34+hkN0DM+GQ/shg== X-Received: by 2002:a63:e051:: with SMTP id n17mr69999158pgj.19.1554263061663; Tue, 02 Apr 2019 20:44:21 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:42 +0700 Message-Id: <20190403034358.21999-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 10/26] target/microblaze: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 5 +- target/microblaze/cpu.c | 5 +- target/microblaze/helper.c | 142 +++++++++++++++++----------------- target/microblaze/op_helper.c | 19 ----- 4 files changed, 78 insertions(+), 93 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 792bbc97c7..8660c7673b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -375,8 +375,9 @@ static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } -int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #include "exec/cpu-all.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5596cd5485..0ea549910b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -304,9 +304,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register; cc->gdb_write_register = mb_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; -#else + cc->tlb_fill = mb_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed = mb_cpu_transaction_failed; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index bc753793ec..2d1d10e6cf 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -26,7 +26,78 @@ #define D(x) -#if defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + +#ifndef CONFIG_USER_ONLY + uint32_t vaddr, paddr; + struct microblaze_mmu_lookup lu; + unsigned int hit; + int prot; + + if (mmu_idx == MMU_NOMMU_IDX) { + /* MMU disabled or not available. */ + address &= TARGET_PAGE_MASK; + prot = PAGE_BITS; + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx); + if (likely(hit)) { + vaddr = address & TARGET_PAGE_MASK; + paddr = lu.paddr + vaddr - lu.vaddr; + + qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", + mmu_idx, vaddr, paddr, lu.prot); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* TLB miss. */ + if (probe) { + return false; + } + + qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", + mmu_idx, address); + + switch (lu.err) { + case ERR_PROT: + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; + env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + break; + case ERR_MISS: + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18; + env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + break; + default: + g_assert_not_reached(); + } + + if (cs->exception_index == EXCP_MMU) { + cpu_abort(cs, "recursive faults\n"); + } +#endif + + env->sregs[SR_EAR] = address; + cs->exception_index = EXCP_MMU; + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif + +#ifdef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs) { @@ -38,74 +109,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] = env->sregs[SR_PC]; } -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - cs->exception_index = 0xaa; - cpu_dump_state(cs, stderr, fprintf, 0); - return 1; -} - -#else /* !CONFIG_USER_ONLY */ - -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - unsigned int hit; - int r = 1; - int prot; - - /* Translate if the MMU is available and enabled. */ - if (mmu_idx != MMU_NOMMU_IDX) { - uint32_t vaddr, paddr; - struct microblaze_mmu_lookup lu; - - hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx); - if (hit) { - vaddr = address & TARGET_PAGE_MASK; - paddr = lu.paddr + vaddr - lu.vaddr; - - qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", - mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); - r = 0; - } else { - env->sregs[SR_EAR] = address; - qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", - mmu_idx, address); - - switch (lu.err) { - case ERR_PROT: - env->sregs[SR_ESR] = rw == 2 ? 17 : 16; - env->sregs[SR_ESR] |= (rw == 1) << 10; - break; - case ERR_MISS: - env->sregs[SR_ESR] = rw == 2 ? 19 : 18; - env->sregs[SR_ESR] |= (rw == 1) << 10; - break; - default: - abort(); - break; - } - - if (cs->exception_index == EXCP_MMU) { - cpu_abort(cs, "recursive faults\n"); - } - - /* TLB miss. */ - cs->exception_index = EXCP_MMU; - } - } else { - /* MMU disabled or not available. */ - address &= TARGET_PAGE_MASK; - prot = PAGE_BITS; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); - r = 0; - } - return r; -} +#else void mb_cpu_do_interrupt(CPUState *cs) { diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e23dcfdc20..b5dbb90d05 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -28,25 +28,6 @@ #define D(x) -#if !defined(CONFIG_USER_ONLY) - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test = ctrl & STREAM_TEST; From patchwork Wed Apr 3 03:43:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7432F17E1 for ; Wed, 3 Apr 2019 03:58:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57A172846C for ; Wed, 3 Apr 2019 03:58:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4C3D02896A; Wed, 3 Apr 2019 03:58:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9AD782846C for ; Wed, 3 Apr 2019 03:58:12 +0000 (UTC) Received: from localhost ([127.0.0.1]:54712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX2R-0006Sb-U0 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:58:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWp9-0002sd-8k for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWp7-0008MK-MX for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:27 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:43566) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWp7-0008LM-At for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:25 -0400 Received: by mail-pg1-x543.google.com with SMTP id z9so7577662pgu.10 for ; Tue, 02 Apr 2019 20:44:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hsT/4r55/BmYXvm+N7+ZWx+INVnPxar+m3RehQ8v76k=; b=QWQGkT3AtW2SLec4EL7fTVJg/0l4CDTeQoyActooDWWFhrTd3sngWxWB6gWdn5BL9y E6T53uBDdbVFxZl0Pr6Ei2aK47CaGDvH5lfyrb81hfALtqH2nYxpjnrcF1HmiWLdpDrR w+JKlXGQ92oBr8uNL/1d79RhQdDtEhWl7a3c00wgiSX6ssJRy2/bt6Na4DzLTI1maXp0 eLRYinlUPINAOQu/XMsnsa5y/TFeFflL+Zja9TNPWQ3phSavn/Z8yP7AHa7ZoBYWaaHc tj3ov5Y0LeAsX8hXK7qBxvjGx1drSVwSt6TxDVqY8upoF6Bvum46AUZYH/xFiA4RrdeT pYCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hsT/4r55/BmYXvm+N7+ZWx+INVnPxar+m3RehQ8v76k=; b=AT6eSAlHjySB3eBf1hLH4PipjG2vpr95fqk7PVurAguCTnt9+3Pcs6cxiJusW1FBDo yb4srQI668cyZuvmYsg9Q8Stt/rWn4jmGKnRsLBzDKcZA4ELzKrMrrh0aX/D65xM3X7N lpkKliPjfJUhFXe5ss83m4li1VwLwZybpeW1907mM8slvJ7jwU04lqWENnlq+A4oEYFh Gs7bmTk00n4ojRMOUaEQyXYeOvJ4P0RKUX9jf/sdN1uCdGe7qaQQ/OzpuqtsPq9zNP3c 2F2dPnEuq8WIW5sxj2S0pRIEIW08hir160Qa7+rOv2F7jkisMdQGM/f79oejLfMhZwJF 3Sig== X-Gm-Message-State: APjAAAWJxyibwYuXeD3wHFmxYswfYIaK8NzICxdstOeuPEtxPifWh08E wcQAygNmizyaaKWXsjSPn8e9Y7wstHVRmg== X-Google-Smtp-Source: APXvYqwQhhpKUE9CAuqqrJzhyDTFthxSw9uDAt7HCaPmM1eZ/T+klpxo0Vimt1/RuPh6BtbyzrPjCg== X-Received: by 2002:a63:c84c:: with SMTP id l12mr70606042pgi.287.1554263063941; Tue, 02 Apr 2019 20:44:23 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:43 +0700 Message-Id: <20190403034358.21999-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 11/26] target/mips: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Note that env->active_tc.PC is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from do_raise_exception_err. Cc: Aleksandar Markovic Cc: Aleksandar Rikalo Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 5 +- target/mips/cpu.c | 5 +- target/mips/helper.c | 115 +++++++++++++++++++--------------------- target/mips/op_helper.c | 15 ------ 4 files changed, 61 insertions(+), 79 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 8f6fc919d5..5ec9d0bd65 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -203,8 +203,9 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /* op_helper.c */ uint32_t float_class_s(uint32_t arg, float_status *fst); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e217fb3e36..ebdb834b97 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -197,9 +197,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = mips_cpu_handle_mmu_fault; -#else + cc->tlb_fill = mips_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access = mips_cpu_unassigned_access; cc->do_unaligned_access = mips_cpu_do_unaligned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; diff --git a/target/mips/helper.c b/target/mips/helper.c index c44cdca3b5..7fe0ba4754 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -874,85 +874,82 @@ refill: #endif #endif -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) + int ret = TLBRET_NOMATCH; + +#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; - int access_type; -#endif - int ret = 0; + int mips_access_type = ACCESS_INT; -#if 0 - log_cpu_state(cs, 0); -#endif qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", - __func__, env->active_tc.PC, address, rw, mmu_idx); + "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ - access_type = ACCESS_INT; - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); - switch (ret) { - case TLBRET_MATCH: + ret = get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); + if (ret == TLBRET_MATCH) { qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx " prot %d\n", __func__, address, physical, prot); - break; - default: - qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d\n", __func__, address, - ret); - break; - } - if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) -#endif - { -#if !defined(CONFIG_USER_ONLY) -#if !defined(TARGET_MIPS64) - if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { - /* - * Memory reads during hardware page table walking are performed - * as if they were kernel-mode load instructions. - */ - int mode = (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &= ~MIPS_HFLAG_KSU; - ret_walker = page_table_walk_refill(env, address, rw, mmu_idx); - env->hflags |= mode; - if (ret_walker) { - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - return ret; - } - } - } -#endif -#endif - raise_mmu_exception(env, address, rw, ret); - ret = 1; + return true; } - return ret; + qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d\n", + __func__, address, ret); + +#ifndef TARGET_MIPS64 + if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { + /* + * Memory reads during hardware page table walking are performed + * as if they were kernel-mode load instructions. + */ + int mode = (env->hflags & MIPS_HFLAG_KSU); + bool ret_walker; + + env->hflags &= ~MIPS_HFLAG_KSU; + ret_walker = page_table_walk_refill(env, address, access_type, mmu_idx); + env->hflags |= mode; + + if (ret_walker) { + ret = get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); + if (ret == TLBRET_MATCH) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + } + } +#endif + + if (probe) { + return false; + } +#endif /* !CONFIG_USER_ONLY */ + + raise_mmu_exception(env, address, access_type, ret); + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } -#if !defined(CONFIG_USER_ONLY) hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) { hwaddr physical; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5b93..6d86912958 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2669,21 +2669,6 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, do_raise_exception_err(env, excp, error_code, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} - void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int unused, unsigned size) From patchwork Wed Apr 3 03:43:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F6991708 for ; Wed, 3 Apr 2019 03:51:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D8FE289B9 for ; Wed, 3 Apr 2019 03:51:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 701A4289F4; Wed, 3 Apr 2019 03:51:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C24CA289F8 for ; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 12/26] target/moxie: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anthony Green Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Anthony Green Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/moxie/cpu.h | 5 ++-- target/moxie/cpu.c | 5 ++-- target/moxie/helper.c | 61 ++++++++++--------------------------------- 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 080df4ee6f..a82c2caf30 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -140,7 +140,8 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc, *flags = 0; } -int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif /* MOXIE_CPU_H */ diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 46434e65ba..02b2b47574 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -112,9 +112,8 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = moxie_cpu_do_interrupt; cc->dump_state = moxie_cpu_dump_state; cc->set_pc = moxie_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = moxie_cpu_handle_mmu_fault; -#else + cc->tlb_fill = moxie_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug; cc->vmsd = &vmstate_moxie_cpu; #endif diff --git a/target/moxie/helper.c b/target/moxie/helper.c index f3d8ee7d6b..216cef057e 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,18 +26,10 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret = moxie_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - cpu_loop_exit_restore(cs, retaddr); - } + moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } void helper_raise_exception(CPUMoxieState *env, int ex) @@ -85,53 +77,29 @@ void helper_debug(CPUMoxieState *env) cpu_loop_exit(cs); } -#if defined(CONFIG_USER_ONLY) - -void moxie_cpu_do_interrupt(CPUState *cs) -{ - CPUState *cs = CPU(moxie_env_get_cpu(env)); - - cs->exception_index = -1; -} - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - MoxieCPU *cpu = MOXIE_CPU(cs); - - cs->exception_index = 0xaa; - cpu->env.debug1 = address; - cpu_dump_state(cs, stderr, fprintf, 0); - return 1; -} - -#else /* !CONFIG_USER_ONLY */ - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MoxieCPU *cpu = MOXIE_CPU(cs); CPUMoxieState *env = &cpu->env; MoxieMMUResult res; int prot, miss; - target_ulong phy; - int r = 1; address &= TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx); - if (miss) { - /* handle the miss. */ - phy = 0; - cs->exception_index = MOXIE_EX_MMU_MISS; - } else { - phy = res.phy; - r = 0; + miss = moxie_mmu_translate(&res, env, address, access_type, mmu_idx); + if (likely(!miss)) { + tlb_set_page(cs, address, res.phy, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; } - tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - return r; -} + cs->exception_index = MOXIE_EX_MMU_MISS; + cpu_loop_exit_restore(cs, retaddr); +} void moxie_cpu_do_interrupt(CPUState *cs) { @@ -156,4 +124,3 @@ hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phy; } -#endif From patchwork Wed Apr 3 03:43:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882653 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9230D17E1 for ; Wed, 3 Apr 2019 03:54:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70D312846C for ; Wed, 3 Apr 2019 03:54:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F7B72881C; Wed, 3 Apr 2019 03:54:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7E6052846C for ; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 13/26] target/nios2: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Chris Wulff Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Chris Wulff Cc: Marek Vasut Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 +- target/nios2/cpu.c | 5 +- target/nios2/helper.c | 181 ++++++++++++++++++++---------------------- target/nios2/mmu.c | 12 --- 4 files changed, 92 insertions(+), 111 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 047f3764b7..b3e9595457 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -251,8 +251,9 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } -int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, int size, - int rw, int mmu_idx); +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbfaa2ce26..186af4913d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -200,9 +200,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = nios2_cpu_handle_mmu_fault; -#else + cc->tlb_fill = nios2_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = nios2_cpu_do_unaligned_access; cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug; #endif diff --git a/target/nios2/helper.c b/target/nios2/helper.c index a8b8ec662a..d075ef1965 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -36,17 +36,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] = env->regs[R_PC] + 4; } -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - cs->exception_index = 0xaa; - /* Page 0x1000 is kuser helper */ - if (address < 0x1000 || address >= 0x2000) { - cpu_dump_state(cs, stderr, fprintf, 0); - } - return 1; -} - #else /* !CONFIG_USER_ONLY */ void nios2_cpu_do_interrupt(CPUState *cs) @@ -190,89 +179,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) } } -static int cpu_nios2_handle_virtual_page( - CPUState *cs, target_ulong address, int rw, int mmu_idx) -{ - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - target_ulong vaddr, paddr; - Nios2MMULookup lu; - unsigned int hit; - hit = mmu_translate(env, &lu, address, rw, mmu_idx); - if (hit) { - vaddr = address & TARGET_PAGE_MASK; - paddr = lu.paddr + vaddr - lu.vaddr; - - if (((rw == 0) && (lu.prot & PAGE_READ)) || - ((rw == 1) && (lu.prot & PAGE_WRITE)) || - ((rw == 2) && (lu.prot & PAGE_EXEC))) { - - tlb_set_page(cs, vaddr, paddr, lu.prot, - mmu_idx, TARGET_PAGE_SIZE); - return 0; - } else { - /* Permission violation */ - cs->exception_index = (rw == 0) ? EXCP_TLBR : - ((rw == 1) ? EXCP_TLBW : - EXCP_TLBX); - } - } else { - cs->exception_index = EXCP_TLBD; - } - - if (rw == 2) { - env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D; - } else { - env->regs[CR_TLBMISC] |= CR_TLBMISC_D; - } - env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr = env->regs[CR_PTEADDR]; - env->regs[CR_BADADDR] = address; - return 1; -} - -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - if (cpu->mmu_present) { - if (MMU_SUPERVISOR_IDX == mmu_idx) { - if (address >= 0xC0000000) { - /* Kernel physical page - TLB bypassed */ - address &= TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } else if (address >= 0x80000000) { - /* Kernel virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx); - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx); - } - } else { - if (address >= 0x80000000) { - /* Illegal access from user mode */ - cs->exception_index = EXCP_SUPERA; - env->regs[CR_BADADDR] = address; - return 1; - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx); - } - } - } else { - /* No MMU */ - address &= TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } - - return 0; -} - hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -308,4 +214,91 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } +#endif /* CONFIG_USER_ONLY */ + +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + Nios2CPU *cpu = NIOS2_CPU(cs); + CPUNios2State *env = &cpu->env; + unsigned int excp = EXCP_TLBD; + +#ifndef CONFIG_USER_ONLY + target_ulong vaddr, paddr; + Nios2MMULookup lu; + unsigned int hit; + + if (!cpu->mmu_present) { + /* No MMU */ + address &= TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + if (MMU_SUPERVISOR_IDX == mmu_idx) { + if (address >= 0xC0000000) { + /* Kernel physical page - TLB bypassed */ + address &= TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + } else { + if (address >= 0x80000000) { + /* Illegal access from user mode */ + if (probe) { + return false; + } + cs->exception_index = EXCP_SUPERA; + env->regs[CR_BADADDR] = address; + cpu_loop_exit_restore(cs, retaddr); + } + } + + /* Virtual page. */ + hit = mmu_translate(env, &lu, address, access_type, mmu_idx); + if (hit) { + vaddr = address & TARGET_PAGE_MASK; + paddr = lu.paddr + vaddr - lu.vaddr; + + if (((access_type == MMU_DATA_LOAD) && (lu.prot & PAGE_READ)) || + ((access_type == MMU_DATA_STORE) && (lu.prot & PAGE_WRITE)) || + ((access_type == MMU_INST_FETCH) && (lu.prot & PAGE_EXEC))) { + tlb_set_page(cs, vaddr, paddr, lu.prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* Permission violation */ + excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR : + access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + } + + if (probe) { + return false; + } + + if (access_type == MMU_INST_FETCH) { + env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D; + } else { + env->regs[CR_TLBMISC] |= CR_TLBMISC_D; + } + env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; + env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr = env->regs[CR_PTEADDR]; #endif /* !CONFIG_USER_ONLY */ + + cs->exception_index = excp; + env->regs[CR_BADADDR] = address; + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 69b71cba4a..db85c8b7c4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -35,18 +35,6 @@ #define MMU_LOG(x) #endif -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = nios2_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - void mmu_read_debug(CPUNios2State *env, uint32_t rn) { switch (rn) { From patchwork Wed Apr 3 03:43:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69CA41708 for ; Wed, 3 Apr 2019 03:55:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D1B12846C for ; Wed, 3 Apr 2019 03:55:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E1982896A; Wed, 3 Apr 2019 03:55:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1A8342846C for ; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 14/26] target/openrisc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Stafford Horne Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/openrisc/cpu.h | 5 ++-- target/openrisc/cpu.c | 5 ++-- target/openrisc/mmu.c | 65 ++++++++++++++++++++++--------------------- 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f1b31bc24a..cbd7c97230 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -345,8 +345,9 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 541b2a66c7..d38cd24275 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -148,9 +148,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; cc->gdb_write_register = openrisc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = openrisc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index e7d5219e11..991f3fafe8 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -107,16 +107,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, cpu->env.lock_addr = -1; } -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { -#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - raise_mmu_exception(cpu, address, EXCP_DPF); - return 1; -#else - g_assert_not_reached(); + int excp = EXCP_DPF; + +#ifndef CONFIG_USER_ONLY + int prot; + hwaddr phys_addr; + + if (mmu_idx == MMU_NOMMU_IDX) { + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp = 0; + } else { + bool super = mmu_idx == MMU_SUPERVISOR_IDX; + int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC + : access_type == MMU_DATA_STORE ? PAGE_WRITE + : PAGE_READ); + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + } + + if (likely(excp == 0)) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } #endif + + raise_mmu_exception(cpu, addr, excp); + cpu_loop_exit_restore(cs, retaddr); } #ifndef CONFIG_USER_ONLY @@ -156,29 +182,6 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int prot, excp; - hwaddr phys_addr; - - if (mmu_idx == MMU_NOMMU_IDX) { - /* The mmu is disabled; lookups never fail. */ - get_phys_nommu(&phys_addr, &prot, addr); - excp = 0; - } else { - bool super = mmu_idx == MMU_SUPERVISOR_IDX; - int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC - : access_type == MMU_DATA_STORE ? PAGE_WRITE - : PAGE_READ); - excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); - } - - if (unlikely(excp)) { - raise_mmu_exception(cpu, addr, excp); - cpu_loop_exit_restore(cs, retaddr); - } - - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr); } #endif From patchwork Wed Apr 3 03:43:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EC771708 for ; Wed, 3 Apr 2019 03:51:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72077289DA for ; Wed, 3 Apr 2019 03:51:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 667A6289F2; Wed, 3 Apr 2019 03:51:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 53B80289E2 for ; Wed, 3 Apr 2019 03:51:50 +0000 (UTC) Received: from localhost ([127.0.0.1]:53065 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWwH-0000xz-Jf for patchwork-qemu-devel@patchwork.kernel.org; Tue, 02 Apr 2019 23:51:49 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpH-0002zQ-EB for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpG-0008Tp-39 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:35 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpF-0008TG-SU for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:34 -0400 Received: by mail-pl1-x644.google.com with SMTP id y6so7330692plt.1 for ; Tue, 02 Apr 2019 20:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=INYoMOC2BML1R/tNbeYBbum+91nSf0ZPyhXaQqqzn14=; b=i0hOnnr0XD1kPsdUHaDbtodSvsCiGNwpsAkSw4OqQbkQhDQtCHkT0fk7jbIZ12SrEC KbF9kHZnAL6S1db8w9VW5spGvSeuY1FxY3Z9s33VQZZGTd2oHRrwaO2J2giBwvYWqG1Z KVO6bHUtIky4he8KPNJnv5kBPvmfRyGJdnOygDaGBBY2EKFyt1hbIOoGtZGIo0drjqYM pQ08B4COyaEJah2ksvwLD9iBCOnlkTfafh4JwTIN2DkdViJZoAUGlNrlPkWLuZNqGbmE MvlOBGF02OOI4gDaAqoOCWItvy2OJqbjTquDRlHVJLXkI2P3Lh8+mUeRbKwbw6/qj01L n+UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=INYoMOC2BML1R/tNbeYBbum+91nSf0ZPyhXaQqqzn14=; b=I+9u/LU5DBH/cWNA1lKtK9mC4nNWyZ4uvxCQmqRjpmdCtfhFQXzzmSABs2Pzu7GgBI crgG2/rtYT+gi79u9dPmhm60btwaQ7+rUsbGWnbaQu6aU/1gFvGU+IkG5jwLdsU0EQJZ QWRdvg+LZyQ+L6QEznDg3cL2s6M+f+wePES5KAQUrPUste/8cy/74Pwjie7VrIZcl2fQ /qypTlbfEBuvMGCRGMHTbJMh+7s2LikT1F46u3Lsd/278/H5OMcbLMU9H/bx0kPHXfht 381fopGmIlxAiFVVqMltBTUMd81df/02LLee8Qb7IbTDL/9FfrN6/RonodFtjmOksxk1 Ug/w== X-Gm-Message-State: APjAAAV0EK9LxwlKGGsYnOjsKSJL1Y1WpQv0t8WBm7718lAuYK6A9/K2 7Gng+xfDlmEhp4zCu8Ckme7u3iZU1yO+Lw== X-Google-Smtp-Source: APXvYqwpVuiqPAOmqRIExrGPHraBuuuYlKquDa5GujCSXl7qrevd/1Zfu2oV8diqGjI5Yxk8gyVRUQ== X-Received: by 2002:a17:902:be04:: with SMTP id r4mr60799618pls.218.1554263072609; Tue, 02 Apr 2019 20:44:32 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:47 +0700 Message-Id: <20190403034358.21999-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 15/26] target/ppc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: qemu-ppc@nongnu.org Cc: David Gibson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/ppc/cpu.h | 7 +++---- target/ppc/mmu_helper.c | 19 +++++++++++++------ target/ppc/translate_init.inc.c | 5 ++--- target/ppc/user_only_helper.c | 14 ++++++++------ 4 files changed, 26 insertions(+), 19 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0707177584..da73d3ee5b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1297,10 +1297,9 @@ void ppc_translate_init(void); is returned if the signal was handled by the virtual CPU. */ int cpu_ppc_signal_handler (int host_signum, void *pinfo, void *puc); -#if defined(CONFIG_USER_ONLY) -int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); -#endif +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 4a6be4d63b..6865c0ca37 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3026,12 +3026,9 @@ void helper_check_tlb_flush_global(CPUPPCState *env) /*****************************************************************************/ -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); @@ -3044,7 +3041,17 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, ret = cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); } if (unlikely(ret != 0)) { + if (probe) { + return false; + } raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); } + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 0bd555eb19..39f37bba5b 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10545,9 +10545,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_write_register = ppc_cpu_gdb_write_register; cc->do_unaligned_access = ppc_cpu_do_unaligned_access; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = ppc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_ppc_cpu; #endif diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 2f1477f102..683c03390d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -20,21 +20,24 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" -int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) + +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int exception, error_code; - if (rw == 2) { + if (access_type == MMU_INST_FETCH) { exception = POWERPC_EXCP_ISI; error_code = 0x40000000; } else { exception = POWERPC_EXCP_DSI; error_code = 0x40000000; - if (rw) { + if (access_type == MMU_DATA_STORE) { error_code |= 0x02000000; } env->spr[SPR_DAR] = address; @@ -42,6 +45,5 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, } cs->exception_index = exception; env->error_code = error_code; - - return 1; + cpu_loop_exit_restore(cs, retaddr); } From patchwork Wed Apr 3 03:43:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B6B871708 for ; Wed, 3 Apr 2019 03:58:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C6442846C for ; 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Tue, 02 Apr 2019 20:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:48 +0700 Message-Id: <20190403034358.21999-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 16/26] target/riscv: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Cc: qemu-riscv@nongnu.org Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu.c | 5 ++--- target/riscv/cpu_helper.c | 46 ++++++++++++++++++--------------------- 3 files changed, 26 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 20bce8742e..40c1254408 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,8 +261,9 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..e9f569c665 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,9 +355,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = riscv_cpu_handle_mmu_fault; -#else + cc->tlb_fill = riscv_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..2535435260 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -379,53 +379,49 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_raise_exception(env, cs->exception_index, retaddr); } -/* called by qemu's softmmu to fill the qemu tlb */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - ret = riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret == TRANSLATE_FAIL) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - riscv_raise_exception(env, cs->exception_index, retaddr); - } + riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } - #endif -int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { +#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr pa = 0; int prot; -#endif int ret = TRANSLATE_FAIL; - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ - %d\n", __func__, env->pc, address, rw, mmu_idx); + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); -#if !defined(CONFIG_USER_ONLY) - ret = get_physical_address(env, &pa, &prot, address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx + " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) { + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - } else if (ret == TRANSLATE_FAIL) { - raise_mmu_exception(env, address, rw); + return true; + } else if (probe) { + return false; + } else { + raise_mmu_exception(env, address, access_type); + riscv_raise_exception(env, cs->exception_index, retaddr); } #else - switch (rw) { + switch (access_type) { case MMU_INST_FETCH: cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; break; @@ -436,8 +432,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; break; } + cpu_loop_exit_restore(cs, retaddr); #endif - return ret; } /* From patchwork Wed Apr 3 03:43:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882673 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8421C1708 for ; Wed, 3 Apr 2019 04:01:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6882628989 for ; Wed, 3 Apr 2019 04:01:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5C9F5289A2; Wed, 3 Apr 2019 04:01:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9D74928989 for ; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 17/26] target/s390x: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , David Hildenbrand Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: qemu-s390x@nongnu.org Cc: Cornelia Huck Cc: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 5 +- target/s390x/cpu.c | 5 +- target/s390x/excp_helper.c | 156 +++++++++++++++++++++---------------- target/s390x/mem_helper.c | 29 ------- 4 files changed, 94 insertions(+), 101 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 5f7901da5e..424e8ce406 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,8 +263,9 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 698dd9cb82..9dd94b1395 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -471,9 +471,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = s390_cpu_set_pc; cc->gdb_read_register = s390_cpu_gdb_read_register; cc->gdb_write_register = s390_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; -#else + cc->tlb_fill = s390_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; cc->vmsd = &vmstate_s390_cpu; cc->write_elf64_note = s390_cpu_write_elf64_note; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index bc781c14c3..aeeaeb523d 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -74,20 +74,14 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - S390CPU *cpu = S390_CPU(cs); - - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING, ILEN_AUTO); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. */ - cpu->env.__excp_addr = address; - return 1; -} - #else /* !CONFIG_USER_ONLY */ +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} + static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) { switch (mmu_idx) { @@ -102,61 +96,6 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, - int rw, int mmu_idx) -{ - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - target_ulong vaddr, raddr; - uint64_t asc; - int prot; - - qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", - __func__, orig_vaddr, rw, mmu_idx); - - vaddr = orig_vaddr; - - if (mmu_idx < MMU_REAL_IDX) { - asc = cpu_mmu_idx_to_asc(mmu_idx); - /* 31-Bit mode */ - if (!(env->psw.mask & PSW_MASK_64)) { - vaddr &= 0x7fffffff; - } - if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) { - return 1; - } - } else if (mmu_idx == MMU_REAL_IDX) { - /* 31-Bit mode */ - if (!(env->psw.mask & PSW_MASK_64)) { - vaddr &= 0x7fffffff; - } - if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) { - return 1; - } - } else { - abort(); - } - - /* check out of RAM access */ - if (!address_space_access_valid(&address_space_memory, raddr, - TARGET_PAGE_SIZE, rw, - MEMTXATTRS_UNSPECIFIED)) { - qemu_log_mask(CPU_LOG_MMU, - "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", - __func__, (uint64_t)raddr, (uint64_t)ram_size); - trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); - return 1; - } - - qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", - __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); - - tlb_set_page(cs, orig_vaddr & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); - - return 0; -} - static void do_program_interrupt(CPUS390XState *env) { uint64_t mask, addr; @@ -577,3 +516,86 @@ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, } #endif /* CONFIG_USER_ONLY */ + +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + S390CPU *cpu = S390_CPU(cs); + +#ifndef CONFIG_USER_ONLY + CPUS390XState *env = &cpu->env; + target_ulong vaddr, raddr; + uint64_t asc; + int prot, fail; + + qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + vaddr = address; + + if (mmu_idx < MMU_REAL_IDX) { + asc = cpu_mmu_idx_to_asc(mmu_idx); + /* 31-Bit mode */ + if (!(env->psw.mask & PSW_MASK_64)) { + vaddr &= 0x7fffffff; + } + fail = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, true); + } else if (mmu_idx == MMU_REAL_IDX) { + /* 31-Bit mode */ + if (!(env->psw.mask & PSW_MASK_64)) { + vaddr &= 0x7fffffff; + } + fail = mmu_translate_real(env, vaddr, access_type, &raddr, &prot); + } else { + g_assert_not_reached(); + } + + /* check out of RAM access */ + if (!fail && + !address_space_access_valid(&address_space_memory, raddr, + TARGET_PAGE_SIZE, access_type, + MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(CPU_LOG_MMU, + "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", + __func__, (uint64_t)raddr, (uint64_t)ram_size); + trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); + fail = 1; + } + + if (!fail) { + qemu_log_mask(CPU_LOG_MMU, + "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", + __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); + tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } +#else + trigger_pgm_exception(&cpu->env, PGM_ADDRESSING, ILEN_AUTO); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + */ + cpu->env.__excp_addr = address; +#endif + + cpu_restore_state(cs, retaddr, true); + + /* + * Note that handle_mmu_fault sets ilen to either 2 (for code) + * or AUTO (for data). We can resolve AUTO now, as if it was + * set to UNWIND -- that will have been done via assignment + * in cpu_restore_state. Otherwise re-examine access_type. + */ + if (access_type == MMU_INST_FETCH) { + CPUS390XState *env = cs->env_ptr; + env->int_pgm_ilen = 2; + } + + cpu_loop_exit(cs); +} + diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index d54907696d..0c5ca36823 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -34,35 +34,6 @@ /*****************************************************************************/ /* Softmmu support */ -#if !defined(CONFIG_USER_ONLY) - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret = s390_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret != 0)) { - cpu_restore_state(cs, retaddr, true); - - /* - * Note that handle_mmu_fault sets ilen to either 2 (for code) - * or AUTO (for data). We can resolve AUTO now, as if it was - * set to UNWIND -- that will have been done via assignment - * in cpu_restore_state. Otherwise re-examine access_type. - */ - if (access_type == MMU_INST_FETCH) { - CPUS390XState *env = cs->env_ptr; - env->int_pgm_ilen = 2; - } - - cpu_loop_exit(cs); - } -} - -#endif /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER From patchwork Wed Apr 3 03:43:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E0D01708 for ; Wed, 3 Apr 2019 04:01:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FB5828988 for ; Wed, 3 Apr 2019 04:01:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 733AA2898B; Wed, 3 Apr 2019 04:01:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C2FD28988 for ; Wed, 3 Apr 2019 04:01:09 +0000 (UTC) Received: from localhost ([127.0.0.1]:55508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX5I-0000V1-TO for patchwork-qemu-devel@patchwork.kernel.org; Wed, 03 Apr 2019 00:01:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpO-00035f-GS for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpM-0000B3-VD for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:42 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:42534) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpM-0000AM-Jd for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:40 -0400 Received: by mail-pl1-x642.google.com with SMTP id cv12so7314086plb.9 for ; Tue, 02 Apr 2019 20:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GrrfMxS6BAo/qH+fRYyxefVrmp0PI4LpRg9xyz4wD40=; b=Yrnuyk8WbimPMfb8ybRR6uZQ3aZPcQ505g7aox8yOkEWQj9IengVLgb0XIZRCaGiQe CMJ6vJmfVV0f/Bs0fuhRFxaiqom+7sp/pE87p0jn4A8fKcZBiAtkLyuPUpkLvyibic3e GxXWVxzM5QkXethBYHs6z7GxuE+UjdFTeyjIqMB9Q4BQ3WiK9YUMlOOOBUGOvt2Wcw74 3gg39l2lb6ZnSwZMfsXJy2uta7peN1z6rRMnR5rZvbq127bQVthjzom+muM6+NtEU0QP j6fCXeMFQ1ajAwhDF/vDtuEDKB7aFtVRV282E//SF5llQk+RgcNe61+5xKKOOYvZVt96 4jGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GrrfMxS6BAo/qH+fRYyxefVrmp0PI4LpRg9xyz4wD40=; b=EyLXIjURcZrvV+IbzOaeyr9sKoMgfDz0M5fNroJKMf/wcgUyzT0Tk0HncMEVKP+9w9 3Bmy1Ll03+yyr5gZv9dGuc/zMDw5ruXAUN3vK+2lZoPa+EZ9xcKm25spKEy/4YPyEW/w CFZQ0j2B/8Bsqf/qVLfADEIkp6vhzYVmpeUufvexEwLksDfiqu/I2Ktkd0+FEwJBs1nn qmVDHzcPhQSh5ilqWloNFNaRWwqCrMYO7pBQ72Oxr9mPM/wWshhey8wfjwdAm5efxF8l iIvcLUTuNDvfRp1IWVPzb/xpqylp0gmTDkcr+NT8G25VREujKGcTLmDaivFu7wpKBcPO t8fQ== X-Gm-Message-State: APjAAAUvZYYuKhuxNz0VuCfHHXWEVlbl8WxxBtuDoETbgvsfMgAI9NEa DDayaRusV5wuyfeQUelrRLhL1YCgdEpbtA== X-Google-Smtp-Source: APXvYqyWpoUP3rPcePM1bwA3x2X99Jy2X+qiz238ckANoJAKosp0E1Ht0gFetkZtDRp4mFtvSMo2jA== X-Received: by 2002:a17:902:bf07:: with SMTP id bi7mr52227958plb.87.1554263079316; Tue, 02 Apr 2019 20:44:39 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:50 +0700 Message-Id: <20190403034358.21999-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 18/26] target/sh4: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Aurelien Jarno Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/sh4/cpu.h | 5 +- target/sh4/cpu.c | 5 +- target/sh4/helper.c | 197 ++++++++++++++++++++--------------------- target/sh4/op_helper.c | 12 --- 4 files changed, 101 insertions(+), 118 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 775b5743bf..80a256e0be 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -244,8 +244,9 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); -int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index b9f393b7c7..886483caaa 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -238,9 +238,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; cc->gdb_read_register = superh_cpu_gdb_read_register; cc->gdb_write_register = superh_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = superh_cpu_handle_mmu_fault; -#else + cc->tlb_fill = superh_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = superh_cpu_do_unaligned_access; cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; #endif diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 2ff0cf4060..1df1e02a14 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -27,43 +27,6 @@ #include "hw/sh4/sh_intc.h" #endif -#if defined(CONFIG_USER_ONLY) - -void superh_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index = -1; -} - -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - - env->tea = address; - cs->exception_index = -1; - switch (rw) { - case 0: - cs->exception_index = 0x0a0; - break; - case 1: - cs->exception_index = 0x0c0; - break; - case 2: - cs->exception_index = 0x0a0; - break; - } - return 1; -} - -int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) -{ - /* For user mode, only U0 area is cacheable. */ - return !(addr & 0x80000000); -} - -#else /* !CONFIG_USER_ONLY */ - #define MMU_OK 0 #define MMU_ITLB_MISS (-1) #define MMU_ITLB_MULTIPLE (-2) @@ -79,6 +42,21 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) +#if defined(CONFIG_USER_ONLY) + +void superh_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index = -1; +} + +int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) +{ + /* For user mode, only U0 area is cacheable. */ + return !(addr & 0x80000000); +} + +#else /* !CONFIG_USER_ONLY */ + void superh_cpu_do_interrupt(CPUState *cs) { SuperHCPU *cpu = SUPERH_CPU(cs); @@ -458,69 +436,6 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - target_ulong physical; - int prot, ret, access_type; - - access_type = ACCESS_INT; - ret = - get_physical_address(env, &physical, &prot, address, rw, - access_type); - - if (ret != MMU_OK) { - env->tea = address; - if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { - env->pteh = (env->pteh & PTEH_ASID_MASK) | - (address & PTEH_VPN_MASK); - } - switch (ret) { - case MMU_ITLB_MISS: - case MMU_DTLB_MISS_READ: - cs->exception_index = 0x040; - break; - case MMU_DTLB_MULTIPLE: - case MMU_ITLB_MULTIPLE: - cs->exception_index = 0x140; - break; - case MMU_ITLB_VIOLATION: - cs->exception_index = 0x0a0; - break; - case MMU_DTLB_MISS_WRITE: - cs->exception_index = 0x060; - break; - case MMU_DTLB_INITIAL_WRITE: - cs->exception_index = 0x080; - break; - case MMU_DTLB_VIOLATION_READ: - cs->exception_index = 0x0a0; - break; - case MMU_DTLB_VIOLATION_WRITE: - cs->exception_index = 0x0c0; - break; - case MMU_IADDR_ERROR: - case MMU_DADDR_ERROR_READ: - cs->exception_index = 0x0e0; - break; - case MMU_DADDR_ERROR_WRITE: - cs->exception_index = 0x100; - break; - default: - cpu_abort(cs, "Unhandled MMU fault"); - } - return 1; - } - - address &= TARGET_PAGE_MASK; - physical &= TARGET_PAGE_MASK; - - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; -} - hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { SuperHCPU *cpu = SUPERH_CPU(cs); @@ -745,7 +660,6 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, if (needs_tlb_flush) { tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); } - } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; @@ -885,3 +799,84 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } + +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + int ret; + +#ifdef CONFIG_USER_ONLY + ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : + access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : + MMU_DTLB_VIOLATION_READ); +#else + target_ulong physical; + int prot, sh_access_type; + + sh_access_type = ACCESS_INT; + ret = get_physical_address(env, &physical, &prot, address, + access_type, sh_access_type); + + if (ret == MMU_OK) { + address &= TARGET_PAGE_MASK; + physical &= TARGET_PAGE_MASK; + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } + + if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { + env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); + } +#endif + + env->tea = address; + switch (ret) { + case MMU_ITLB_MISS: + case MMU_DTLB_MISS_READ: + cs->exception_index = 0x040; + break; + case MMU_DTLB_MULTIPLE: + case MMU_ITLB_MULTIPLE: + cs->exception_index = 0x140; + break; + case MMU_ITLB_VIOLATION: + cs->exception_index = 0x0a0; + break; + case MMU_DTLB_MISS_WRITE: + cs->exception_index = 0x060; + break; + case MMU_DTLB_INITIAL_WRITE: + cs->exception_index = 0x080; + break; + case MMU_DTLB_VIOLATION_READ: + cs->exception_index = 0x0a0; + break; + case MMU_DTLB_VIOLATION_WRITE: + cs->exception_index = 0x0c0; + break; + case MMU_IADDR_ERROR: + case MMU_DADDR_ERROR_READ: + cs->exception_index = 0x0e0; + break; + case MMU_DADDR_ERROR_WRITE: + cs->exception_index = 0x100; + break; + default: + cpu_abort(cs, "Unhandled MMU fault"); + } + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 4f825bae5a..599731966b 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -41,18 +41,6 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_loop_exit_restore(cs, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 19/26] target/sparc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 5 +- target/sparc/cpu.c | 5 +- target/sparc/ldst_helper.c | 15 ---- target/sparc/mmu_helper.c | 175 +++++++++++++++++++------------------ 4 files changed, 93 insertions(+), 107 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4972ebcfd4..44336e5899 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -580,8 +580,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4a4445bdf5..016a70717e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -880,9 +880,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->gdb_read_register = sparc_cpu_gdb_read_register; cc->gdb_write_register = sparc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = sparc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access = sparc_cpu_unassigned_access; cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 5bc090213c..88196a3ad9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1924,19 +1924,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - cpu_loop_exit_restore(cs, retaddr); - } -} #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 135a9c9d9b..b0fdabbea3 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -24,28 +24,7 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (rw & 2) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - return 1; -} - -#else +#ifndef CONFIG_USER_ONLY #ifndef TARGET_SPARC64 /* @@ -85,10 +64,10 @@ static const int perm_table[2][8] = { } }; -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address1(CPUSPARCState *env, hwaddr *physical, + int *prot, int *access_index, + target_ulong address, int rw, int mmu_idx, + target_ulong *page_size) { int access_perms = 0; hwaddr pde_ptr; @@ -206,51 +185,41 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, return error_code; } -/* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +static int get_physical_address(CPUSPARCState *env, hwaddr *physical, + int *prot, int *access_index, + target_ulong address, int rw, int mmu_idx, + target_ulong *page_size) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - hwaddr paddr; - target_ulong vaddr; - target_ulong page_size; - int error_code = 0, prot, access_index; + int error_code; + CPUState *cs = CPU(sparc_env_get_cpu(env)); - address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - vaddr = address; - if (error_code == 0) { - qemu_log_mask(CPU_LOG_MMU, - "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " - TARGET_FMT_lx "\n", address, paddr, vaddr); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + error_code = get_physical_address1(env, physical, prot, access_index, + address, rw, mmu_idx, page_size); + + if (error_code && ((env->mmuregs[0] & MMU_NF) || env->psret == 0)) { + /* + * No fault mode: if a mapping is available, just override + * permissions. If no mapping is available, redirect accesses to + * neverland. Fake/overridden mappings will be flushed when + * switching to normal mode. + */ + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } if (env->mmuregs[3]) { /* Fault status register */ env->mmuregs[3] = 1; /* overflow (not read before another fault) */ } - env->mmuregs[3] |= (access_index << 5) | error_code | 2; + env->mmuregs[3] |= (*access_index << 5) | error_code | 2; env->mmuregs[4] = address; /* Fault address register */ - if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { - /* No fault mode: if a mapping is available, just override - permissions. If no mapping is available, redirect accesses to - neverland. Fake/overridden mappings will be flushed when - switching to normal mode. */ - prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + if (rw & 2) { + cs->exception_index = TT_TFAULT; } else { - if (rw & 2) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; - } - return 1; + cs->exception_index = TT_DFAULT; } + + return error_code; } target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) @@ -711,34 +680,6 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } } -/* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - target_ulong vaddr; - hwaddr paddr; - target_ulong page_size; - int error_code = 0, prot, access_index; - - address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - if (error_code == 0) { - vaddr = address; - - trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, - env->dmmu.mmu_primary_context, - env->dmmu.mmu_secondary_context); - - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; - } - /* XXX */ - return 1; -} - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) { unsigned int i; @@ -865,3 +806,63 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } #endif + +/* Perform address translation */ +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef CONFIG_USER_ONLY + if (access_type == MMU_INST_FETCH) { + cs->exception_index = TT_TFAULT; + } else { + cs->exception_index = TT_DFAULT; + } +# ifdef TARGET_SPARC64 + env->dmmu.mmuregs[4] = address; +# else + env->mmuregs[4] = address; +# endif +#else + hwaddr paddr; + target_ulong vaddr; + target_ulong page_size; + int error_code = 0, prot, access_index; + + address &= TARGET_PAGE_MASK; + error_code = get_physical_address(env, &paddr, &prot, &access_index, + address, access_type, mmu_idx, + &page_size); + vaddr = address; + if (error_code == 0) { +# ifdef TARGET_SPARC64 + trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context); +# else + qemu_log_mask(CPU_LOG_MMU, + "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " + TARGET_FMT_lx "\n", address, paddr, vaddr); +# endif + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + return true; + } + + if (probe) { + return false; + } +#endif + + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif From patchwork Wed Apr 3 03:43:52 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 20/26] target/tilegx: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/tilegx/cpu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index bfe9be59b5..be50976c6f 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -24,6 +24,8 @@ #include "qemu-common.h" #include "hw/qdev-properties.h" #include "linux-user/syscall_defs.h" +#include "exec/exec-all.h" + static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) @@ -111,8 +113,9 @@ static void tilegx_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +static bool tilegx_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { TileGXCPU *cpu = TILEGX_CPU(cs); @@ -122,7 +125,7 @@ static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, cpu->env.signo = TARGET_SIGSEGV; cpu->env.sigcode = 0; - return 1; + cpu_loop_exit_restore(cs, retaddr); } static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -152,7 +155,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt; cc->dump_state = tilegx_cpu_dump_state; cc->set_pc = tilegx_cpu_set_pc; - cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault; + cc->tlb_fill = tilegx_cpu_tlb_fill; cc->gdb_num_core_regs = 0; cc->tcg_initialize = tilegx_tcg_init; } From patchwork Wed Apr 3 03:43:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5640D17E1 for ; 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Tue, 02 Apr 2019 20:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:53 +0700 Message-Id: <20190403034358.21999-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH 21/26] target/tricore: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Bastian Koppelmann Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/tricore/cpu.h | 6 +++--- target/tricore/cpu.c | 1 + target/tricore/helper.c | 27 +++++++++++++++++++-------- target/tricore/op_helper.c | 26 -------------------------- 4 files changed, 23 insertions(+), 37 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 00e69dc154..5c0b8cb94c 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -418,8 +418,8 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ -int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address, - int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif /* TRICORE_CPU_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e8d37e4040..ea1199d27e 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -166,6 +166,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb; cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug; cc->tcg_initialize = tricore_tcg_init; + cc->tlb_fill = tricore_cpu_tlb_fill; } #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 0769046993..3c99a8c22b 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -49,8 +49,9 @@ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, { } -int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, - int rw, int mmu_idx) +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType rw, int mmu_idx, + bool probe, uintptr_t retaddr) { TriCoreCPU *cpu = TRICORE_CPU(cs); CPUTriCoreState *env = &cpu->env; @@ -63,20 +64,30 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, address, rw, access_type); - qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, physical, prot); + + qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, (target_ulong)address, ret, physical, prot); if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) { + return true; + } else { + assert(ret < 0); + if (probe) { + return false; + } raise_mmu_exception(env, address, rw, ret); - ret = 1; + cpu_loop_exit_restore(cs, retaddr); } +} - return ret; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } static void tricore_cpu_list_entry(gpointer data, gpointer user_data) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ed9dc0c83e..601e92f92a 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2793,29 +2793,3 @@ uint32_t helper_psw_read(CPUTriCoreState *env) { return psw_read(env); } - - -static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs = CPU(tricore_env_get_cpu(env)); - cs->exception_index = exception; - env->error_code = error_code; - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, pc); -} - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - ret = cpu_tricore_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (ret) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} From patchwork Wed Apr 3 03:43:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89DE11708 for ; Wed, 3 Apr 2019 03:57:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DA112846C for ; Wed, 3 Apr 2019 03:57:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 61F442896A; Wed, 3 Apr 2019 03:57:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 862602846C for ; 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X-Received-From: 2607:f8b0:4864:20::52c Subject: [Qemu-devel] [PATCH 22/26] target/unicore32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guan Xuetao Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Guan Xuetao Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/unicore32/cpu.h | 5 +++-- target/unicore32/cpu.c | 5 +---- target/unicore32/helper.c | 23 ----------------------- target/unicore32/op_helper.c | 14 -------------- target/unicore32/softmmu.c | 19 +++++++++++++++---- 5 files changed, 19 insertions(+), 47 deletions(-) diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 735d3ae9dc..dfec908cad 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -179,8 +179,9 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc } } -int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 2b49d1ca40..3f57c508a0 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -138,11 +138,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault; -#else + cc->tlb_fill = uc32_cpu_tlb_fill; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; -#endif cc->tcg_initialize = uc32_translate_init; dc->vmsd = &vmstate_uc32_cpu; } diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..0d4914b48d 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -215,29 +215,6 @@ void helper_cp1_putc(target_ulong x) } #endif -#ifdef CONFIG_USER_ONLY -void switch_mode(CPUUniCore32State *env, int mode) -{ - UniCore32CPU *cpu = uc32_env_get_cpu(env); - - if (mode != ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); - } -} - -void uc32_cpu_do_interrupt(CPUState *cs) -{ - cpu_abort(cs, "NO interrupt in user mode\n"); -} - -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) -{ - cpu_abort(cs, "NO mmu fault in user mode\n"); - return 1; -} -#endif - bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..797ba60dc9 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -242,17 +242,3 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = uc32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..13678df4d7 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -215,8 +215,9 @@ do_fault: return code; } -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { UniCore32CPU *cpu = UNICORE32_CPU(cs); CPUUniCore32State *env = &cpu->env; @@ -257,7 +258,11 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); - return 0; + return true; + } + + if (probe) { + return false; } env->cp0.c3_faultstatus = ret; @@ -267,7 +272,13 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, } else { cs->exception_index = UC32_EXCP_DTRAP; } - return ret; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) From patchwork Wed Apr 3 03:43:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A48E813B5 for ; Wed, 3 Apr 2019 04:00:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 871F52863F for ; Wed, 3 Apr 2019 04:00:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 76E1B286D0; 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Tue, 02 Apr 2019 20:44:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:55 +0700 Message-Id: <20190403034358.21999-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 23/26] target/xtensa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 5 +-- target/xtensa/cpu.c | 5 ++- target/xtensa/helper.c | 74 +++++++++++++++++++++--------------------- 3 files changed, 42 insertions(+), 42 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4d8152682f..8ac6f8eeca 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, - int mmu_idx); +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..da1236377e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,9 +181,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = xtensa_cpu_gdb_read_register; cc->gdb_write_register = xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint = true; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault; -#else + cc->tlb_fill = xtensa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed = xtensa_cpu_do_transaction_failed; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f4867a9b56..3dcab54fbf 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -237,24 +237,49 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) } } -#ifdef CONFIG_USER_ONLY - -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; + target_ulong vaddr = address; + int ret; - qemu_log_mask(CPU_LOG_INT, - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, rw, address, size); - env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE; - cs->exception_index = EXC_USER; - return 1; +#ifdef CONFIG_USER_ONLY + ret = (access_type == MMU_DATA_STORE ? + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); +#else + uint32_t paddr; + uint32_t page_size; + unsigned access; + + ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, + &paddr, &page_size, &access); + + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", + __func__, vaddr, access_type, mmu_idx, paddr, ret); + + if (ret == 0) { + tlb_set_page(cs, vaddr & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); + return true; + } + if (probe) { + return false; + } +#endif + + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } -#else +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, retaddr); +} void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -272,31 +297,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, - &paddr, &page_size, &access); - - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); - - if (ret == 0) { - tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); - } else { - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); - } -} - void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, From patchwork Wed Apr 3 03:43:56 2019 Content-Type: text/plain; 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Tue, 02 Apr 2019 20:44:51 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:56 +0700 Message-Id: <20190403034358.21999-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 24/26] tcg: Use CPUClass::tlb_fill in cputlb.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also which also isolates the asserts implied. Remove the named tlb_fill function from all of the targets. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 9 --------- accel/tcg/cputlb.c | 19 +++++++++++++++++++ target/alpha/helper.c | 8 -------- target/arm/helper.c | 8 -------- target/cris/helper.c | 6 ------ target/hppa/mem_helper.c | 6 ------ target/i386/excp_helper.c | 8 -------- target/lm32/helper.c | 6 ------ target/m68k/helper.c | 8 -------- target/microblaze/helper.c | 8 -------- target/mips/helper.c | 6 ------ target/moxie/helper.c | 6 ------ target/nios2/helper.c | 8 -------- target/openrisc/mmu.c | 6 ------ target/ppc/mmu_helper.c | 6 ------ target/riscv/cpu_helper.c | 6 ------ target/s390x/excp_helper.c | 6 ------ target/sh4/helper.c | 8 -------- target/sparc/mmu_helper.c | 8 -------- target/tricore/helper.c | 6 ------ target/unicore32/softmmu.c | 6 ------ target/xtensa/helper.c | 6 ------ 22 files changed, 19 insertions(+), 145 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 97b90cb0db..66e67caad7 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -474,15 +474,6 @@ static inline void assert_no_pages_locked(void) */ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs); - -/* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must - * be discarded and looked up again (e.g. via tlb_entry()). - */ -void tlb_fill(CPUState *cpu, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - #endif #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 88cc8389e9..7f59d815db 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -855,6 +855,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } +/* + * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the + * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must + * be discarded and looked up again (e.g. via tlb_entry()). + */ +static void tlb_fill(CPUState *cpu, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + bool ok; + + /* + * This is not a probe, so only valid return is success; failure + * should result in exception + longjmp to the cpu loop. + */ + ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); + g_assert(ok); +} + static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index e54197d5fb..726104a308 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -272,14 +272,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #endif } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void alpha_cpu_do_interrupt(CPUState *cs) { AlphaCPU *cpu = ALPHA_CPU(cs); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0fc4abc651..db8c825a4b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12404,14 +12404,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #endif } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/cris/helper.c b/target/cris/helper.c index 69464837c8..b5159b8357 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -123,12 +123,6 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit(cs); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void crisv10_cpu_do_interrupt(CPUState *cs) { CRISCPU *cpu = CRIS_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f61b0fdb9f..75b7082e0a 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -261,12 +261,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) -{ - hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); -} - /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) { diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 6f59b7bafc..79635d7539 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -700,11 +700,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; #endif } - -#if !defined(CONFIG_USER_ONLY) -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 1db9a5562e..20ea17ba23 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -44,12 +44,6 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { LM32CPU *cpu = LM32_CPU(cs); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9768b4517f..2e34c684ba 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -893,14 +893,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - uint32_t HELPER(bitrev)(uint32_t x) { x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 2d1d10e6cf..650897a20b 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -89,14 +89,6 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - #ifdef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs) diff --git a/target/mips/helper.c b/target/mips/helper.c index 7fe0ba4754..520f89407c 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -944,12 +944,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) { hwaddr physical; diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 216cef057e..f5c1d4181c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,12 +26,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void helper_raise_exception(CPUMoxieState *env, int ex) { CPUState *cs = CPU(moxie_env_get_cpu(env)); diff --git a/target/nios2/helper.c b/target/nios2/helper.c index d075ef1965..34ad6987b7 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -294,11 +294,3 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->regs[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 991f3fafe8..4e190514ca 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,10 +178,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr); -} #endif diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 6865c0ca37..b8b44b2323 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3049,9 +3049,3 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, } return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2535435260..41d6db41c3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -378,12 +378,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; riscv_raise_exception(env, cs->exception_index, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} #endif bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index aeeaeb523d..ec03d9f7d3 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -76,12 +76,6 @@ void s390_cpu_do_interrupt(CPUState *cs) #else /* !CONFIG_USER_ONLY */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) { switch (mmu_idx) { diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 1df1e02a14..074c74f337 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -872,11 +872,3 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index b0fdabbea3..ae9b7a0eb3 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -858,11 +858,3 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 3c99a8c22b..157c8caf4b 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -84,12 +84,6 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - static void tricore_cpu_list_entry(gpointer data, gpointer user_data) { ObjectClass *oc = data; diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 13678df4d7..27f218abf0 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -275,12 +275,6 @@ bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { error_report("function uc32_cpu_get_phys_page_debug not " diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 3dcab54fbf..62d8dd1227 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -275,12 +275,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, retaddr); -} - void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Wed Apr 3 03:43:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882701 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DE6A13B5 for ; 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Tue, 02 Apr 2019 20:44:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:57 +0700 Message-Id: <20190403034358.21999-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 25/26] tcg: Remove CPUClass::handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This hook is now completely replaced by tlb_fill. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/qom/cpu.h | 3 --- accel/tcg/user-exec.c | 13 +++---------- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 7e96a0aed3..8afcf0c427 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -118,7 +118,6 @@ struct TranslationBlock; * This always includes at least the program counter; some targets * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). - * @handle_mmu_fault: Callback for handling an MMU fault. * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -198,8 +197,6 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); - int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, - int mmu_index); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f13c0b2b67..d79bed0266 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -63,7 +63,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, { CPUState *cpu = current_cpu; CPUClass *cc; - int ret; unsigned long address = (unsigned long)info->si_addr; MMUAccessType access_type; @@ -162,15 +161,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, helper_retaddr = 0; cc = CPU_GET_CLASS(cpu); - if (cc->tlb_fill) { - access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); - g_assert_not_reached(); - } else { - ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); - g_assert(ret > 0); - cpu_loop_exit_restore(cpu, pc); - } + access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + g_assert_not_reached(); } #if defined(__i386__) From patchwork Wed Apr 3 03:43:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10882705 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 14CAC1708 for ; Wed, 3 Apr 2019 04:04:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED51628721 for ; Wed, 3 Apr 2019 04:04:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E0B972873A; Wed, 3 Apr 2019 04:04:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4A08D28721 for ; Wed, 3 Apr 2019 04:04:50 +0000 (UTC) Received: from localhost ([127.0.0.1]:56508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX8r-0003U7-Lk for patchwork-qemu-devel@patchwork.kernel.org; Wed, 03 Apr 2019 00:04:49 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpe-0003Ky-2U for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpc-0000VU-Ib for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:58 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:38823) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpc-0000Uk-8H for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:56 -0400 Received: by mail-pg1-x544.google.com with SMTP id j26so7590224pgl.5 for ; Tue, 02 Apr 2019 20:44:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=eSmixxW4uQkmpintF6uPGofmBAlQammZR2m74ngSc30=; b=AgoLDyYKfXcmkyqBht0yChfxRyCqfM+thujBfEG5aQVxMroKMgJsoM9rffGJCb7675 Wl8X+h7ryvSLyI+PfGWX7W0Ey5bTWFxk/vvz77ae6l45FzPodxX4Y0D4zfvHv1telFxF cg57BW5P5Mq5hdghJxIxvp9UqYE1fqyByRmS322M22ikJRBvA++8U/yNImrq0x+ihyGK D9z/TjypT64NZrn5aSkMkLOzdd2ce8qEZPqfgPg1Mb6btHSHbKKjEkkAVQoba8yjM48w gGQbZQIE/T5FPVHYjIZWxDJ+Vmqo4WUeRP0MCQo7WheHWMTIJTXafzQjUN+/ct/6NiRc RkXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=eSmixxW4uQkmpintF6uPGofmBAlQammZR2m74ngSc30=; b=g6iMz6l3xh+QJZajdvJyB8keB0kKae0vpYXybHX1Zsh8yO+8xosfgG9RNG9aqelNnK nqFcdJi9VB7lWiVr56pRa+koEWz+sRVFrYx/9f0wrj3oha08bxu2NRBOvQjMsTfivvdB XLKkRcM6iE2jUME1xkFb0PxaEt7Z7N8qCLLzCyAZTyY8lI3d6y97nsp9qB8bvCsF511D 9JPvph/pVuaM07gQjw+jJHPargcrFN4x/n16BlAEdhRZaUK4eRmNAJnMM51/1IeSItm+ It3r9FxguMjr2TEx+aoTIBzgv47mNPBAmVAxPIm+GROZXQH+f5ExnBM30Q0QXD2Lk/1A oTog== X-Gm-Message-State: APjAAAUqgCBwS8XZ92V5m3s5wr+wqAOt/n4R5uPSctWQvYekY+P74h8x J3nGblOI1zCy4m+E0gkpnCHbi02+ev9b9Q== X-Google-Smtp-Source: APXvYqxxUGB8MklzDdqz6ByrRJ0YLCX6iomtn691jGDYW7OuQQD/o9ip0iUyXPhjQwQnq13meXz+kQ== X-Received: by 2002:a62:62c3:: with SMTP id w186mr41924483pfb.73.1554263094953; Tue, 02 Apr 2019 20:44:54 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:58 +0700 Message-Id: <20190403034358.21999-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 26/26] tcg: Use tlb_fill probe from tlb_vaddr_to_host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for SVE we have a true non-faulting case which requires the new probing form of tlb_fill. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu_ldst.h | 40 ++++-------------------- accel/tcg/cputlb.c | 69 ++++++++++++++++++++++++++++++++++++----- target/arm/sve_helper.c | 6 +--- 3 files changed, 68 insertions(+), 47 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d78041d7a0..be8c3f4da2 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -440,43 +440,15 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, * This is the equivalent of the initial fast-path code used by * TCG backends for guest load and store accesses. */ +#ifdef CONFIG_USER_ONLY static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - int access_type, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { -#if defined(CONFIG_USER_ONLY) return g2h(addr); -#else - CPUTLBEntry *tlbentry = tlb_entry(env, mmu_idx, addr); - abi_ptr tlb_addr; - uintptr_t haddr; - - switch (access_type) { - case 0: - tlb_addr = tlbentry->addr_read; - break; - case 1: - tlb_addr = tlb_addr_write(tlbentry); - break; - case 2: - tlb_addr = tlbentry->addr_code; - break; - default: - g_assert_not_reached(); - } - - if (!tlb_hit(tlb_addr, addr)) { - /* TLB entry is for a different page */ - return NULL; - } - - if (tlb_addr & ~TARGET_PAGE_MASK) { - /* IO access */ - return NULL; - } - - haddr = addr + tlbentry->addend; - return (void *)haddr; -#endif /* defined(CONFIG_USER_ONLY) */ } +#else +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); +#endif #endif /* CPU_LDST_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7f59d815db..959b6d4ded 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1006,6 +1006,16 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, } } +static inline target_ulong tlb_read_ofs(CPUTLBEntry *entry, size_t ofs) +{ +#if TCG_OVERSIZED_GUEST + return *(target_ulong *)((uintptr_t)entry + ofs); +#else + /* ofs might correspond to .addr_write, so use atomic_read */ + return atomic_read((target_ulong *)((uintptr_t)entry + ofs)); +#endif +} + /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, @@ -1016,14 +1026,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp; - - /* elt_ofs might correspond to .addr_write, so use atomic_read */ -#if TCG_OVERSIZED_GUEST - cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs); -#else - cmp = atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); -#endif + target_ulong cmp = tlb_read_ofs(vtlb, elt_ofs); if (cmp == page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1107,6 +1110,56 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, } } +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx) +{ + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + uintptr_t tlb_addr, page; + size_t elt_ofs; + + switch (access_type) { + case MMU_DATA_LOAD: + elt_ofs = offsetof(CPUTLBEntry, addr_read); + break; + case MMU_DATA_STORE: + elt_ofs = offsetof(CPUTLBEntry, addr_write); + break; + case MMU_INST_FETCH: + elt_ofs = offsetof(CPUTLBEntry, addr_code); + break; + default: + g_assert_not_reached(); + } + + page = addr & TARGET_PAGE_MASK; + tlb_addr = tlb_read_ofs(entry, elt_ofs); + + if (!tlb_hit_page(tlb_addr, page)) { + uintptr_t index = tlb_index(env, mmu_idx, addr); + + if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) { + CPUState *cs = ENV_GET_CPU(env); + CPUClass *cc = CPU_GET_CLASS(cs); + + if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) { + /* Non-faulting page table read failed. */ + return NULL; + } + + /* TLB resize via tlb_fill may have moved the entry. */ + entry = tlb_entry(env, mmu_idx, addr); + } + tlb_addr = tlb_read_ofs(entry, elt_ofs); + } + + if (tlb_addr & ~TARGET_PAGE_MASK) { + /* IO access */ + return NULL; + } + + return (void *)(addr + entry->addend); +} + /* Probe for a read-modify-write atomic operation. Do not allow unaligned * operations, or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index bc847250dd..fd434c66ea 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4598,11 +4598,7 @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr, * in the real world, obviously.) * * Then there are the annoying special cases with watchpoints... - * - * TODO: Add a form of tlb_fill that does not raise an exception, - * with a form of tlb_vaddr_to_host and a set of loads to match. - * The non_fault_vaddr_to_host would handle everything, usually, - * and the loads would handle the iomem path for watchpoints. + * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true). */ host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx); split = max_for_page(addr, mem_off, mem_max);