From patchwork Wed Apr 3 13:14:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A46D81708 for ; Wed, 3 Apr 2019 13:26:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 822C0286E3 for ; Wed, 3 Apr 2019 13:26:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75BF9286FF; Wed, 3 Apr 2019 13:26:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCB79286E3 for ; Wed, 3 Apr 2019 13:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726462AbfDCNZy (ORCPT ); Wed, 3 Apr 2019 09:25:54 -0400 Received: from de-deferred1.bosch-org.com ([139.15.180.216]:42114 "EHLO de-deferred1.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726411AbfDCNZx (ORCPT ); Wed, 3 Apr 2019 09:25:53 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by si0vms0224.rbdmz01.com (Postfix) with ESMTPS id 44Z65f3nqDz29q; Wed, 3 Apr 2019 15:15:50 +0200 (CEST) Received: from si0vm1947.rbesz01.com (unknown [139.15.230.188]) by si0vms0216.rbdmz01.com (Postfix) with ESMTPS id 44Z65c625Fz1XLG6v; Wed, 3 Apr 2019 15:15:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297348; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=X7+/TkICb4Vcmx8SPBnNJJSLxMI2dW/tRjpHz0GUXEfmaxWlpCAHypxtZZraii2YP NIGkCHxmoMJlaK/mg5hAFev2pzQxIKhX1OF2Q7meaJsgypj588Zb6QqGDLoaQIYI23 GdvyggSq850lcoVAR7IBWMf90rMmxqNaaiqxnFlo= Received: from fe0vm02900.rbesz01.com (unknown [10.58.172.176]) by si0vm1947.rbesz01.com (Postfix) with ESMTPS id 44Z65c5XlXz6CjQSS; Wed, 3 Apr 2019 15:15:48 +0200 (CEST) X-AuditID: 0a3aad0c-d01ff700000039d6-3b-5ca4b20455d2 Received: from si0vm1949.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by fe0vm02900.rbesz01.com (SMG Outbound) with SMTP id 70.BF.14806.402B4AC5; Wed, 3 Apr 2019 15:15:48 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by si0vm1949.rbesz01.com (Postfix) with ESMTPS id 44Z65c08p9z6CjZqr; Wed, 3 Apr 2019 15:15:48 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:45 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Koji Matsuoka , Tsutomu Muroya , Steve Longerbeam Subject: [PATCH 1/8] drm: Add DU CMM support functions Date: Wed, 3 Apr 2019 18:44:37 +0530 Message-ID: <1554297284-14009-2-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA22Sf0wbZRjHed+7647KkeNg8FA2nBf1D8lmmW5WWcw0/tGZTJclM5npsh1y tM0okLvSwBIMsjAzIE4Stwjr2qGNA2IdxcyxgXTrUMuPwcQtU1mKmWjKMn4X12Uq3lFY+4f/ Pc/zfT7vN+83D01wA+t0tLXULkqlQgmv0ZLaV7wbN5NdHpP+Vneywd0/QhluLs1qDFGnHxvm G0OU4afLTo3hwtQMNly7fYUwnPN+RuykjR2eKGGcaPgBG3uWapHxr+Em0rjYlbuHele7o0gs sTpE6flXD2ktoeFasrx/EVfWOXNr0OhXuB4l08C+CP7eM+vqkZbm2GYMt329VKzxI4gMzeFY cx/Bud+GSRXRsJvB7/OtIBlsO4KGmYsrWwQ7iCAwOK00NJ3ObocTXkEtSfZp6H60S2UZdh+0 LLSgmHUu/DJynFDrZPYdcAcnNWrNKTvu6AIV20+DgebJFV+CBbgaDhPqk8Bugkutmo8R25Kw 1ZKwdRbhDpRZLOodNv3Wl/X6LVKhKB/R5295r8zWhWJxp3Sj7zzmAGJpxKcwC80eE0cJDrnK FkDbaMyvZ7a/r4xSC8uKqiyCbDkoVZSIMq9jNtx408SlPx7LFYU2qyxby0oDCGiCz2CGT5w1 cUyRUHVElMpiWADl0CSfxZjpt00caxbs4mFRLBelNbWApnlgMnyKYZokmsXKYmuJfU3mNzIo KSmJy0xUEm0xnRxAL9ApijdWn2DkcsEmW82reHYM59amcXQQvaTLYvaoDKuqlorSx666DUzS Hy4Ttz5BiJP30BhScktn/jmvwCnKJcf9gMlRI0pbHcahrS6FYX8uhr62VAh5ddAzaQTX+FvQ d2w/BDurYOBONUx9WINg6vpRBJdu1CNwz7Qi+GbOg2D5c+UmXd1LCNrml5W27QMMf3cdxRD8 1Ynh7vcuDI+G2jH0/Xkfw9jlBxhOjbQSEJluJ+DhR7MEBD0PCGhrOkbCXNBHwt1PJkj4fXyS hMiZkxSEOk9T95QUsZKiocKtpmgX7P+T4uo0/i1dDfLOSPvnQ8u780/67hyvY7/1NWR/GTWO RVL/te+acBRc8H8d6T99/aFLXz8ebDp8kbgW3elgpPM7Gq801oWfoaKaocWn9kaqF+A1dvSJ MV/f9BcoI4fal525N/x67tWOXrmwjq+tznsyb+hQT9622QMFzzrDDVmVb2zq/NT64+LoKZ6U LUL+c4QkC/8Brf5tmFwEAAA= Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh This is the out-of-tree patch for DU CMM driver support from Yocto release v3.4.0. Link: https://github.com/renesas-rcar/du_cmm/commit/2d8ea2b667ad4616aa639c54ecc11f7c4b58959d.patch Following is from the patch description: du_cmm: Release for Yocto v3.4.0 This patch made the following correspondence. - Corresponds to kernel v 4.14. - Double buffer only is supported. - Fix CLU / LUT update timing. - Add CMM Channel occupation mode. - Fix Close process. Signed-off-by: Koji Matsuoka Signed-off-by: Tsutomu Muroya Signed-off-by: Steve Longerbeam - Removal of rcar specific ioctals - Resolved checkpatch errors - Resolved merge conflicts according to latest version - Included CMM drivers and included files from base patch - Removed rcar_du_drm.h include file Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/rcar-du/Makefile | 2 + drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 1200 +++++++++++++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 24 + drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 16 + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 43 +- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 +- drivers/gpu/drm/rcar-du/rcar_du_group.c | 5 + drivers/gpu/drm/rcar-du/rcar_du_regs.h | 92 +++ include/drm/drm_ioctl.h | 7 + 9 files changed, 1398 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_cmm.c diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile index 2a3b8d7..595e719 100644 --- a/drivers/gpu/drm/rcar-du/Makefile +++ b/drivers/gpu/drm/rcar-du/Makefile @@ -6,12 +6,14 @@ rcar-du-drm-y := rcar_du_crtc.o \ rcar_du_kms.o \ rcar_du_plane.o +rcar-du-drm-y += rcar_du_cmm.o rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_of.o \ rcar_du_of_lvds_r8a7790.dtb.o \ rcar_du_of_lvds_r8a7791.dtb.o \ rcar_du_of_lvds_r8a7793.dtb.o \ rcar_du_of_lvds_r8a7795.dtb.o \ rcar_du_of_lvds_r8a7796.dtb.o + rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o diff --git a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c new file mode 100644 index 0000000..ac613a6e --- /dev/null +++ b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c @@ -0,0 +1,1200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*************************************************************************/ /* + * DU CMM + * + * Copyright (C) 2018 Renesas Electronics Corporation + * + * License Dual MIT/GPLv2 + * + * The contents of this file are subject to the MIT license as set out below. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Alternatively, the contents of this file may be used under the terms of + * the GNU General Public License Version 2 ("GPL") in which case the provisions + * of GPL are applicable instead of those above. + * + * If you wish to allow use of your version of this file only under the terms of + * GPL, and not to allow others to use your version of this file under the terms + * of the MIT license, indicate your decision by deleting the provisions above + * and replace them with the notice and other provisions required by GPL as set + * out in the file called "GPL-COPYING" included in this distribution. If you do + * not delete the provisions above, a recipient may use your version of this + * file under the terms of either the MIT license or GPL. + * + * This License is also included in this distribution in the file called + * "MIT-COPYING". + * + * EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS + * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS + * OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR + * IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + * GPLv2: + * If you wish to use this file under the terms of GPL, following terms are + * effective. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /*************************************************************************/ +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "rcar_du_crtc.h" +#include "rcar_du_drv.h" +#include "rcar_du_kms.h" +#include "rcar_du_plane.h" +#include "rcar_du_regs.h" +#include + +/* #define DEBUG_PROCE_TIME 1 */ + +#define CMM_LUT_NUM 256 +#define CMM_CLU_NUM (17 * 17 * 17) +#define CMM_HGO_NUM 64 +/* rcar_du_drm.h Include */ +#define LUT_DOUBLE_BUFFER_AUTO 0 +#define LUT_DOUBLE_BUFFER_A 1 +#define LUT_DOUBLE_BUFFER_B 2 +/* DRM_RCAR_DU_CMM_WAIT_EVENT: DU-CMM done event */ +#define CMM_EVENT_CLU_DONE BIT(0) +#define CMM_EVENT_HGO_DONE BIT(1) +#define CMM_EVENT_LUT_DONE BIT(2) + +#define CLU_DOUBLE_BUFFER_AUTO 0 +#define CLU_DOUBLE_BUFFER_A 1 +#define CLU_DOUBLE_BUFFER_B 2 +enum { + QUE_STAT_PENDING, + QUE_STAT_ACTIVE, + QUE_STAT_DONE, +}; + +static const struct soc_device_attribute rcar_du_cmm_r8a7795_es1[] = { + { .soc_id = "r8a7795", .revision = "ES1.*" }, + { /* sentinel */ } +}; + +struct rcar_du_cmm; +struct rcar_du_cmm_file_priv; + +struct rcar_du_cmm_pending_event { + struct list_head link; + struct list_head fpriv_link; + unsigned int event; + unsigned int stat; + unsigned long callback_data; + struct drm_gem_object *gem_obj; + struct rcar_du_cmm *du_cmm; + struct rcar_du_cmm_file_priv *fpriv; +}; + +struct cmm_module_t { + struct list_head list; + union { + struct { + struct rcar_du_cmm_pending_event *p; + int buf_mode; + bool one_side; + }; + int reset; + }; +}; + +struct cmm_reg_save { +#ifdef CONFIG_PM_SLEEP + wait_queue_head_t wait; + + u32 *lut_table; + u32 *clu_table; +#endif /* CONFIG_PM_SLEEP */ + + u32 cm2_ctl0; /* CM2_CTL0 */ + u32 hgo_offset; /* CMM_HGO_OFFSET */ + u32 hgo_size; /* CMM_HGO_SIZE */ + u32 hgo_mode; /* CMM_HGO_MODE */ +}; + +struct rcar_du_cmm { + struct rcar_du_crtc *rcrtc; + + /* CMM base address */ + void __iomem *cmm_base; + struct clk *clock; + + struct cmm_module_t lut; + struct cmm_module_t clu; + struct cmm_module_t hgo; + + struct mutex lock; /* lock for register setting */ + struct workqueue_struct *workqueue; + struct work_struct work; + + struct cmm_reg_save reg_save; + bool active; + bool dbuf; + bool clu_dbuf; + bool init; + bool direct; + bool vsync; + bool authority; + pid_t pid; + bool soc_support; +}; + +struct rcar_du_cmm_file_priv { + wait_queue_head_t event_wait; + struct list_head list; + struct list_head active_list; + struct list_head *done_list; +}; + +static DEFINE_MUTEX(cmm_event_lock); +static DEFINE_SPINLOCK(cmm_direct_lock); + +static inline void event_prev_cancel_locked(struct cmm_module_t *module); + +static inline u32 cmm_index(struct rcar_du_cmm *_cmm) +{ + struct rcar_du_device *rcdu = _cmm->rcrtc->group->dev; + + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_R8A77965_REGS)) { + if ((_cmm)->rcrtc->index == 3) + return 2; + } + return (_cmm)->rcrtc->index; +} + +#define cmm_done_list(_cmm, _fpriv) \ + (&((_fpriv)->done_list[cmm_index(_cmm)])) + +static inline u32 rcar_du_cmm_read(struct rcar_du_cmm *du_cmm, u32 reg) +{ + return ioread32(du_cmm->cmm_base + reg); +} + +static inline void rcar_du_cmm_write(struct rcar_du_cmm *du_cmm, + u32 reg, u32 data) +{ + iowrite32(data, du_cmm->cmm_base + reg); +} + +/* create default CLU table data */ +static inline u32 index_to_clu_data(int index) +{ + int r, g, b; + + r = index % 17; + index /= 17; + g = index % 17; + index /= 17; + b = index % 17; + + r = (r << 20); + if (r > (255 << 16)) + r = (255 << 16); + g = (g << 12); + if (g > (255 << 8)) + g = (255 << 8); + b = (b << 4); + if (b > (255 << 0)) + b = (255 << 0); + + return r | g | b; +} + +#ifdef DEBUG_PROCE_TIME +static long long diff_timevals(struct timeval *start, struct timeval *end) +{ + return (end->tv_sec * 1000000LL + end->tv_usec) - + (start->tv_sec * 1000000LL + start->tv_usec); +} +#endif + +static void du_cmm_clk(struct rcar_du_cmm *du_cmm, bool on) +{ + if (on) + clk_prepare_enable(du_cmm->clock); + else + clk_disable_unprepare(du_cmm->clock); +} + +int rcar_du_cmm_start_stop(struct rcar_du_crtc *rcrtc, bool on) +{ + struct rcar_du_cmm *du_cmm = rcrtc->cmm_handle; + int i; + u32 table_data; + const struct drm_display_mode *mode; + int w, h, x, y; + + if (!du_cmm) + return -EINVAL; + + mutex_lock(&du_cmm->lock); + + if (!on) { + du_cmm->active = false; + + rcar_du_cmm_write(du_cmm, CMM_LUT_CTRL, 0x00000000); + rcar_du_cmm_write(du_cmm, CMM_CLU_CTRL, 0x00000000); + + du_cmm_clk(du_cmm, false); + + goto end; + } + + du_cmm_clk(du_cmm, true); + + if (du_cmm->init) + goto init_done; + + du_cmm->init = true; + + mode = &du_cmm->rcrtc->crtc.mode; + + x = (du_cmm->reg_save.hgo_offset >> 16) & 0xFFFF; + y = (du_cmm->reg_save.hgo_offset >> 0) & 0xFFFF; + w = (du_cmm->reg_save.hgo_size >> 16) & 0xFFFF; + h = (du_cmm->reg_save.hgo_size >> 0) & 0xFFFF; + if ((mode->hdisplay < (w + x)) || w == 0) { + x = 0; + w = mode->hdisplay; + } + if ((mode->vdisplay < (h + y)) || h == 0) { + y = 0; + h = mode->vdisplay; + } + du_cmm->reg_save.hgo_offset = (x << 16) | y; + du_cmm->reg_save.hgo_size = (w << 16) | h; + + if (mode->flags & DRM_MODE_FLAG_PVSYNC) + du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_VPOL; + else + du_cmm->reg_save.cm2_ctl0 &= ~CMM_CTL0_VPOL; + + rcar_du_cmm_write(du_cmm, CM2_CTL0, du_cmm->reg_save.cm2_ctl0); + rcar_du_cmm_write(du_cmm, CMM_HGO_OFFSET, du_cmm->reg_save.hgo_offset); + rcar_du_cmm_write(du_cmm, CMM_HGO_SIZE, du_cmm->reg_save.hgo_size); + rcar_du_cmm_write(du_cmm, CMM_HGO_MODE, du_cmm->reg_save.hgo_mode); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB_TH, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB0_H, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB0_V, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB1_H, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB1_V, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB2_H, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB2_V, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB3_H, 0); + rcar_du_cmm_write(du_cmm, CMM_HGO_LB3_V, 0); + + /* init color table */ + for (i = 0; i < CMM_LUT_NUM; i++) { + #ifdef CONFIG_PM_SLEEP + table_data = du_cmm->reg_save.lut_table[i]; + #else + table_data = ((i << 16) | (i << 8) | (i << 0)); + #endif /* CONFIG_PM_SLEEP */ + rcar_du_cmm_write(du_cmm, CMM_LUT_TBLA(i), table_data); + + if (du_cmm->dbuf) + rcar_du_cmm_write(du_cmm, CMM_LUT_TBLB(i), + table_data); + } + + rcar_du_cmm_write(du_cmm, CMM_CLU_CTRL, + CMM_CLU_CTRL_AAI | CMM_CLU_CTRL_MVS); + + rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR, 0); + if (du_cmm->clu_dbuf) + rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR2, 0); + + for (i = 0; i < CMM_CLU_NUM; i++) { + #ifdef CONFIG_PM_SLEEP + table_data = du_cmm->reg_save.clu_table[i]; + #else + table_data = index_to_clu_data(i); + #endif /* CONFIG_PM_SLEEP */ + rcar_du_cmm_write(du_cmm, CMM_CLU_DATA, table_data); + + if (du_cmm->dbuf) + rcar_du_cmm_write(du_cmm, CMM_CLU_DATA2, + table_data); + } + +init_done: + /* enable color table */ + rcar_du_cmm_write(du_cmm, CMM_LUT_CTRL, CMM_LUT_CTRL_EN); + rcar_du_cmm_write(du_cmm, CMM_CLU_CTRL, CMM_CLU_CTRL_AAI | + CMM_CLU_CTRL_MVS | CMM_CLU_CTRL_EN); + + du_cmm->active = true; +end: + mutex_unlock(&du_cmm->lock); + + return 0; +} + +#define gem_to_vaddr(gem_obj) \ + (container_of((gem_obj), struct drm_gem_cma_object, base)->vaddr) + +static inline void cmm_vblank_put(struct rcar_du_cmm_pending_event *p) +{ + if (p->du_cmm) + drm_crtc_vblank_put(&p->du_cmm->rcrtc->crtc); +} + +static inline void +cmm_gem_object_unreference(struct rcar_du_cmm_pending_event *p) +{ + if (p->gem_obj) + drm_gem_object_unreference_unlocked(p->gem_obj); +} + +static inline void _event_done_locked(struct rcar_du_cmm_pending_event *p) +{ + cmm_gem_object_unreference(p); + + if (p->fpriv) { + p->stat = QUE_STAT_DONE; + list_del(&p->link); /* delete from p->fpriv->active_list */ + list_add_tail(&p->link, cmm_done_list(p->du_cmm, p->fpriv)); + wake_up_interruptible(&p->fpriv->event_wait); + } else { + /* link deleted by rcar_du_cmm_postclose */ + kfree(p); + } +} + +/* cancel from active_list (case of LUT/CLU double buffer mode) */ +static inline void event_prev_cancel_locked(struct cmm_module_t *module) +{ + struct rcar_du_cmm_pending_event *p = module->p; + + if (!p) + return; + + module->p = NULL; + + _event_done_locked(p); +} + +static inline void event_done(struct rcar_du_cmm_pending_event *p) +{ + /* vblank is put */ + + mutex_lock(&cmm_event_lock); + + _event_done_locked(p); + + mutex_unlock(&cmm_event_lock); +} + +static inline void lc_event_done(struct cmm_module_t *module, + struct rcar_du_cmm_pending_event *p, + bool done) +{ + /* vblank is put */ + + mutex_lock(&cmm_event_lock); + + if (!done && list_empty(&module->list)) + module->p = p; + else + _event_done_locked(p); + + mutex_unlock(&cmm_event_lock); +} + +static inline struct rcar_du_cmm_pending_event * +event_pop_locked(struct cmm_module_t *module) +{ + struct rcar_du_cmm_pending_event *p = + list_first_entry(&module->list, + struct rcar_du_cmm_pending_event, + link); + + p->stat = QUE_STAT_ACTIVE; + list_del(&p->link); /* delete from du_cmm->[lut|clu|hgo].list */ + list_add_tail(&p->link, &p->fpriv->active_list); + cmm_vblank_put(p); + + return p; +} + +struct rcar_du_cmm_work_stat { + union { + struct { + struct rcar_du_cmm_pending_event *p; + bool done; + bool table_copy; + }; + struct { + struct rcar_du_cmm_pending_event *p2; + bool reset; + }; + }; +}; + +static inline void one_side(struct rcar_du_cmm *du_cmm, + struct cmm_module_t *module, + bool on) +{ + if (on && !module->one_side) { + module->one_side = true; + drm_crtc_vblank_get(&du_cmm->rcrtc->crtc); + } else if (!on && module->one_side) { + module->one_side = false; + drm_crtc_vblank_put(&du_cmm->rcrtc->crtc); + } +} + +/* pop LUT que */ +static int lut_pop_locked(struct rcar_du_cmm *du_cmm, + struct rcar_du_cmm_work_stat *stat) +{ + bool is_one_side = false; + + stat->done = true; + stat->table_copy = false; + + if (!list_empty(&du_cmm->lut.list)) { + stat->p = event_pop_locked(&du_cmm->lut); + + /* prev lut table */ + event_prev_cancel_locked(&du_cmm->lut); + + if (du_cmm->lut.buf_mode == LUT_DOUBLE_BUFFER_AUTO) { + is_one_side = true; + if (list_empty(&du_cmm->lut.list)) + stat->done = false; + } + + } else if (du_cmm->lut.p) { + /* prev lut table */ + stat->p = du_cmm->lut.p; + du_cmm->lut.p = NULL; + } else { + stat->done = false; + stat->p = NULL; + stat->table_copy = du_cmm->lut.one_side; + } + + one_side(du_cmm, &du_cmm->lut, is_one_side); + + return 0; +} + +static int lut_table_copy(struct rcar_du_cmm *du_cmm) +{ + int i; + u32 src, dst; + + if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { + dst = CMM_LUT_TBLA(0); + src = CMM_LUT_TBLB(0); + } else { + dst = CMM_LUT_TBLB(0); + src = CMM_LUT_TBLA(0); + } + + for (i = 0; i < CMM_LUT_NUM; i++) { + rcar_du_cmm_write(du_cmm, dst, rcar_du_cmm_read(du_cmm, src)); + dst += 4; + src += 4; + } + + return 0; +} + +/* set 1D look up table */ +static int lut_set(struct rcar_du_cmm *du_cmm, + struct rcar_du_cmm_work_stat *stat) +{ + int i; + u32 lut_base; + u32 *lut_buf; + + if (!stat->p) { + if (stat->table_copy) + lut_table_copy(du_cmm); + return 0; /* skip */ + } + + /* set LUT */ + switch (du_cmm->lut.buf_mode) { + case LUT_DOUBLE_BUFFER_A: + lut_base = CMM_LUT_TBLA(0); + break; + + case LUT_DOUBLE_BUFFER_AUTO: + if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { + lut_base = CMM_LUT_TBLA(0); + break; + } + lut_base = CMM_LUT_TBLB(0); + break; + case LUT_DOUBLE_BUFFER_B: + lut_base = CMM_LUT_TBLB(0); + break; + + default: + return -EINVAL; + } + + lut_buf = gem_to_vaddr(stat->p->gem_obj); + for (i = 0; i < CMM_LUT_NUM; i++) + rcar_du_cmm_write(du_cmm, lut_base + i * 4, lut_buf[i]); + + lc_event_done(&du_cmm->lut, stat->p, stat->done); + + return 0; +} + +/* pop CLU que */ +static int clu_pop_locked(struct rcar_du_cmm *du_cmm, + struct rcar_du_cmm_work_stat *stat) +{ + bool is_one_side = false; + + stat->done = true; + stat->table_copy = false; + + if (!list_empty(&du_cmm->clu.list)) { + stat->p = event_pop_locked(&du_cmm->clu); + + /* prev clu table */ + event_prev_cancel_locked(&du_cmm->clu); + + if (du_cmm->clu.buf_mode == CLU_DOUBLE_BUFFER_AUTO) { + is_one_side = true; + if (list_empty(&du_cmm->clu.list)) + stat->done = false; + } + + } else if (du_cmm->clu.p) { + /* prev clu table */ + stat->p = du_cmm->clu.p; + du_cmm->clu.p = NULL; + } else { + stat->done = false; + stat->p = NULL; + stat->table_copy = du_cmm->clu.one_side; + } + + one_side(du_cmm, &du_cmm->clu, is_one_side); + + return 0; +} + +static int clu_table_copy(struct rcar_du_cmm *du_cmm) +{ + int i, j, k; + u32 src_addr, src_data, dst_addr, dst_data; + + if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { + dst_addr = CMM_CLU_ADDR; + dst_data = CMM_CLU_DATA; + src_addr = CMM_CLU_ADDR2; + src_data = CMM_CLU_DATA2; + } else { + dst_addr = CMM_CLU_ADDR2; + dst_data = CMM_CLU_DATA2; + src_addr = CMM_CLU_ADDR; + src_data = CMM_CLU_DATA; + } + + rcar_du_cmm_write(du_cmm, dst_addr, 0); + for (i = 0; i < 17; i++) { + for (j = 0; j < 17; j++) { + for (k = 0; k < 17; k++) { + rcar_du_cmm_write(du_cmm, src_addr, + (k << 16) | (j << 8) | + (i << 0)); + rcar_du_cmm_write(du_cmm, dst_data, + rcar_du_cmm_read(du_cmm, + src_data)); + } + } + } + + return 0; +} + +/* set 3D look up table */ +static int clu_set(struct rcar_du_cmm *du_cmm, + struct rcar_du_cmm_work_stat *stat) +{ + int i; + u32 addr_reg, data_reg; + u32 *clu_buf; + + if (!stat->p) { + if (stat->table_copy) + clu_table_copy(du_cmm); + return 0; /* skip */ + } + + /* set CLU */ + switch (du_cmm->clu.buf_mode) { + case CLU_DOUBLE_BUFFER_A: + addr_reg = CMM_CLU_ADDR; + data_reg = CMM_CLU_DATA; + break; + + case CLU_DOUBLE_BUFFER_AUTO: + if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { + addr_reg = CMM_CLU_ADDR; + data_reg = CMM_CLU_DATA; + break; + } + addr_reg = CMM_CLU_ADDR2; + data_reg = CMM_CLU_DATA2; + break; + case CLU_DOUBLE_BUFFER_B: + addr_reg = CMM_CLU_ADDR2; + data_reg = CMM_CLU_DATA2; + break; + + default: + return -EINVAL; + } + + clu_buf = gem_to_vaddr(stat->p->gem_obj); + rcar_du_cmm_write(du_cmm, addr_reg, 0); + for (i = 0; i < CMM_CLU_NUM; i++) + rcar_du_cmm_write(du_cmm, data_reg, clu_buf[i]); + + lc_event_done(&du_cmm->clu, stat->p, stat->done); + + return 0; +} + +/* pop HGO que */ +static int hgo_pop_locked(struct rcar_du_cmm *du_cmm, + struct rcar_du_cmm_work_stat *stat) +{ + struct rcar_du_cmm_pending_event *_p = NULL; + + if (!list_empty(&du_cmm->hgo.list)) + _p = event_pop_locked(&du_cmm->hgo); + + if (du_cmm->hgo.reset) { + drm_crtc_vblank_put(&du_cmm->rcrtc->crtc); + du_cmm->hgo.reset = 0; + stat->reset = true; + } else { + stat->reset = false; + } + + stat->p2 = _p; + + return 0; +} + +/* get histogram */ +static int hgo_get(struct rcar_du_cmm *du_cmm, + struct rcar_du_cmm_work_stat *stat) +{ + int i, j; + const u32 histo_offset[3] = { + CMM_HGO_R_HISTO(0), + CMM_HGO_G_HISTO(0), + CMM_HGO_B_HISTO(0), + }; + void *vaddr; + + if (!stat->p2) { + if (stat->reset) + goto hgo_reset; + + return 0; /* skip */ + } + + vaddr = gem_to_vaddr(stat->p2->gem_obj); + for (i = 0; i < 3; i++) { + u32 *hgo_buf = vaddr + CMM_HGO_NUM * 4 * i; + + for (j = 0; j < CMM_HGO_NUM; j++) + hgo_buf[j] = rcar_du_cmm_read(du_cmm, + histo_offset[i] + j * 4); + } + + event_done(stat->p2); + +hgo_reset: + rcar_du_cmm_write(du_cmm, CMM_HGO_REGRST, CMM_HGO_REGRST_RCLEA); + + return 0; +} + +static bool du_cmm_vsync_get(struct rcar_du_cmm *du_cmm) +{ + unsigned long flags; + bool vsync; + + spin_lock_irqsave(&cmm_direct_lock, flags); + vsync = du_cmm->vsync; + du_cmm->vsync = false; + spin_unlock_irqrestore(&cmm_direct_lock, flags); + + return vsync; +} + +static void du_cmm_vsync_set(struct rcar_du_cmm *du_cmm, bool vsync) +{ + unsigned long flags; + + spin_lock_irqsave(&cmm_direct_lock, flags); + du_cmm->vsync = vsync; + spin_unlock_irqrestore(&cmm_direct_lock, flags); +} + +static void du_cmm_work(struct work_struct *work) +{ + struct rcar_du_cmm *du_cmm = + container_of(work, struct rcar_du_cmm, work); + struct rcar_du_cmm_work_stat s_lut; + struct rcar_du_cmm_work_stat s_clu; + struct rcar_du_cmm_work_stat s_hgo; +#ifdef DEBUG_PROCE_TIME + struct timeval start_time, end_time; + unsigned long lut_time, clu_time, hgo_time; +#endif + bool vsync_status = false; + + memset(&s_lut, 0, sizeof(struct rcar_du_cmm_work_stat)); + memset(&s_clu, 0, sizeof(struct rcar_du_cmm_work_stat)); + memset(&s_hgo, 0, sizeof(struct rcar_du_cmm_work_stat)); + + vsync_status = du_cmm_vsync_get(du_cmm); + + mutex_lock(&cmm_event_lock); + + lut_pop_locked(du_cmm, &s_lut); + clu_pop_locked(du_cmm, &s_clu); + if (vsync_status) + hgo_pop_locked(du_cmm, &s_hgo); + + mutex_unlock(&cmm_event_lock); + + /* set LUT */ +#ifdef DEBUG_PROCE_TIME + do_gettimeofday(&start_time); +#endif + lut_set(du_cmm, &s_lut); +#ifdef DEBUG_PROCE_TIME + do_gettimeofday(&end_time); + lut_time = (long)diff_timevals(&start_time, &end_time); +#endif + + /* set CLU */ +#ifdef DEBUG_PROCE_TIME + do_gettimeofday(&start_time); +#endif + clu_set(du_cmm, &s_clu); +#ifdef DEBUG_PROCE_TIME + do_gettimeofday(&end_time); + clu_time = (long)diff_timevals(&start_time, &end_time); +#endif + + /* get HGO */ +#ifdef DEBUG_PROCE_TIME + do_gettimeofday(&start_time); +#endif + if (vsync_status) + hgo_get(du_cmm, &s_hgo); +#ifdef DEBUG_PROCE_TIME + do_gettimeofday(&end_time); + hgo_time = (long)diff_timevals(&start_time, &end_time); +#endif + +#ifdef CONFIG_PM_SLEEP + wake_up_interruptible(&du_cmm->reg_save.wait); +#endif /* CONFIG_PM_SLEEP */ + +#ifdef DEBUG_PROCE_TIME + { + struct rcar_du_device *rcdu = du_cmm->rcrtc->group->dev; + + if (s_lut.p) + dev_info(rcdu->dev, "LUT %ld usec.\n", lut_time); + if (s_clu.p) + dev_info(rcdu->dev, "LUT %ld usec.\n", clu_time); + if (s_hgo.p2) + dev_info(rcdu->dev, "HGO %ld usec.\n", hgo_time); + } +#endif +} + +static int du_cmm_que_empty(struct rcar_du_cmm *du_cmm) +{ + if (list_empty(&du_cmm->lut.list) && !du_cmm->lut.p && + !du_cmm->lut.one_side && + list_empty(&du_cmm->clu.list) && !du_cmm->clu.p && + !du_cmm->clu.one_side && + list_empty(&du_cmm->hgo.list) && !du_cmm->hgo.reset) + return 1; + + return 0; +} + +void rcar_du_cmm_kick(struct rcar_du_crtc *rcrtc) +{ + struct rcar_du_cmm *du_cmm = rcrtc->cmm_handle; + + if (!du_cmm) + return; + + if (!du_cmm->active) + return; + + if (!du_cmm_que_empty(du_cmm)) { + du_cmm_vsync_set(du_cmm, true); + queue_work(du_cmm->workqueue, &du_cmm->work); + } +} + +#ifdef CONFIG_PM_SLEEP +int rcar_du_cmm_pm_suspend(struct rcar_du_crtc *rcrtc) +{ + struct rcar_du_cmm *du_cmm = rcrtc->cmm_handle; + struct rcar_du_device *rcdu = rcrtc->group->dev; + int i, j, k, index; + int ret; + + if (!du_cmm) + return 0; + + ret = wait_event_timeout(du_cmm->reg_save.wait, + du_cmm_que_empty(du_cmm), + msecs_to_jiffies(500)); + if (ret == 0) + dev_err(rcdu->dev, "rcar-du cmm suspend : timeout\n"); + + if (!du_cmm->init) + return 0; + + du_cmm->init = false; + + if (!du_cmm->active) + du_cmm_clk(du_cmm, true); + + /* table save */ + for (i = 0; i < CMM_LUT_NUM; i++) { + du_cmm->reg_save.lut_table[i] = + rcar_du_cmm_read(du_cmm, CMM_LUT_TBLA(i)); + } + + index = 0; + for (i = 0; i < 17; i++) { + for (j = 0; j < 17; j++) { + for (k = 0; k < 17; k++) { + rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR, + (k << 16) | (j << 8) | + (i << 0)); + du_cmm->reg_save.clu_table[index++] = + rcar_du_cmm_read(du_cmm, CMM_CLU_DATA); + } + } + } + + if (!du_cmm->active) + du_cmm_clk(du_cmm, false); + + return 0; +} + +int rcar_du_cmm_pm_resume(struct rcar_du_crtc *rcrtc) +{ + /* none */ + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + +int rcar_du_cmm_driver_open(struct drm_device *dev, struct drm_file *file_priv) +{ + struct rcar_du_device *rcdu = dev->dev_private; + struct rcar_du_cmm_file_priv *fpriv; + int i; + + if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) + return 0; + + file_priv->driver_priv = NULL; + + fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); + if (unlikely(!fpriv)) + return -ENOMEM; + + fpriv->done_list = kcalloc(rcdu->info->num_crtcs, + sizeof(*fpriv->done_list), + GFP_KERNEL); + if (unlikely(!fpriv->done_list)) { + kfree(fpriv); + return -ENOMEM; + } + + init_waitqueue_head(&fpriv->event_wait); + INIT_LIST_HEAD(&fpriv->list); + INIT_LIST_HEAD(&fpriv->active_list); + for (i = 0; i < rcdu->info->num_crtcs; i++) + INIT_LIST_HEAD(&fpriv->done_list[i]); + + file_priv->driver_priv = fpriv; + + return 0; +} + +void rcar_du_cmm_postclose(struct drm_device *dev, struct drm_file *file_priv) +{ + struct rcar_du_device *rcdu = dev->dev_private; + struct rcar_du_cmm_file_priv *fpriv = file_priv->driver_priv; + struct rcar_du_cmm_pending_event *p, *pt; + struct rcar_du_crtc *rcrtc; + struct rcar_du_cmm *du_cmm; + int i, crtcs_cnt, ret; + u32 table_data; + + if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) + return; + + mutex_lock(&cmm_event_lock); + + /* Unlink file priv events */ + list_for_each_entry_safe(p, pt, &fpriv->list, fpriv_link) { + list_del(&p->fpriv_link); + list_del(&p->link); + switch (p->stat) { + case QUE_STAT_PENDING: + cmm_vblank_put(p); + cmm_gem_object_unreference(p); + kfree(p); + break; + case QUE_STAT_DONE: + kfree(p); + break; + case QUE_STAT_ACTIVE: + p->fpriv = NULL; + break; + } + } + + mutex_unlock(&cmm_event_lock); + + kfree(fpriv->done_list); + kfree(fpriv); + file_priv->driver_priv = NULL; + + for (crtcs_cnt = 0; crtcs_cnt < rcdu->num_crtcs; crtcs_cnt++) { + rcrtc = &rcdu->crtcs[crtcs_cnt]; + du_cmm = rcrtc->cmm_handle; + if (du_cmm->authority && du_cmm->pid == task_pid_nr(current)) { + du_cmm->authority = false; + du_cmm->pid = 0; + ret = wait_event_timeout(du_cmm->reg_save.wait, + du_cmm_que_empty(du_cmm), + msecs_to_jiffies(500)); + if (ret == 0) + dev_err(rcdu->dev, "rcar-du cmm close : timeout\n"); + + for (i = 0; i < CMM_LUT_NUM; i++) + du_cmm->reg_save.lut_table[i] = (i << 16) | + (i << 8) | + (i << 0); + + for (i = 0; i < CMM_CLU_NUM; i++) { + du_cmm->reg_save.clu_table[i] = + index_to_clu_data(i); + } + + for (i = 0; i < CMM_LUT_NUM; i++) { +#ifdef CONFIG_PM_SLEEP + table_data = du_cmm->reg_save.lut_table[i]; +#else + table_data = ((i << 16) | (i << 8) | (i << 0)); +#endif /* CONFIG_PM_SLEEP */ + rcar_du_cmm_write(du_cmm, CMM_LUT_TBLA(i), + table_data); + if (du_cmm->dbuf) { + rcar_du_cmm_write(du_cmm, + CMM_LUT_TBLB(i), + table_data); + } + } + + for (i = 0; i < CMM_CLU_NUM; i++) { +#ifdef CONFIG_PM_SLEEP + table_data = du_cmm->reg_save.clu_table[i]; +#else + table_data = index_to_clu_data(i); +#endif /* CONFIG_PM_SLEEP */ + rcar_du_cmm_write(du_cmm, CMM_CLU_DATA, + table_data); + + if (du_cmm->dbuf) { + rcar_du_cmm_write(du_cmm, CMM_CLU_DATA2, + table_data); + } + } + } + } +} + +int rcar_du_cmm_init(struct rcar_du_crtc *rcrtc) +{ + struct rcar_du_cmm *du_cmm; + int ret; + int i; + struct rcar_du_device *rcdu = rcrtc->group->dev; + char name[64]; + struct resource *mem; + + if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) + return 0; + + du_cmm = devm_kzalloc(rcdu->dev, sizeof(*du_cmm), GFP_KERNEL); + if (!du_cmm) { + ret = -ENOMEM; + goto error_alloc; + } + + /* DU-CMM mapping */ + sprintf(name, "cmm.%u", rcrtc->index); + mem = platform_get_resource_byname(to_platform_device(rcdu->dev), + IORESOURCE_MEM, name); + if (!mem) { + dev_err(rcdu->dev, "rcar-du cmm init : failed to get memory resource\n"); + ret = -EINVAL; + goto error_mapping_cmm; + } + du_cmm->cmm_base = devm_ioremap_nocache(rcdu->dev, mem->start, + resource_size(mem)); + if (!du_cmm->cmm_base) { + dev_err(rcdu->dev, "rcar-du cmm init : failed to map iomem\n"); + ret = -EINVAL; + goto error_mapping_cmm; + } + du_cmm->clock = devm_clk_get(rcdu->dev, name); + if (IS_ERR(du_cmm->clock)) { + dev_err(rcdu->dev, "failed to get clock\n"); + ret = PTR_ERR(du_cmm->clock); + goto error_clock_cmm; + } + + du_cmm->rcrtc = rcrtc; + + du_cmm->reg_save.cm2_ctl0 = 0; + du_cmm->reg_save.hgo_offset = 0; + du_cmm->reg_save.hgo_size = 0; + du_cmm->reg_save.hgo_mode = 0; + + du_cmm->dbuf = rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM_LUT_DBUF); + if (du_cmm->dbuf) { + du_cmm->lut.buf_mode = LUT_DOUBLE_BUFFER_AUTO; + du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_DBUF; + } else { + dev_err(rcdu->dev, "single buffer is not supported.\n"); + du_cmm->dbuf = true; + du_cmm->lut.buf_mode = LUT_DOUBLE_BUFFER_AUTO; + du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_DBUF; + } + + du_cmm->clu_dbuf = rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM_CLU_DBUF); + if (du_cmm->clu_dbuf) { + du_cmm->clu.buf_mode = CLU_DOUBLE_BUFFER_AUTO; + du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_CLUDB; + } else { + dev_err(rcdu->dev, "single buffer is not supported.\n"); + du_cmm->clu_dbuf = true; + du_cmm->clu.buf_mode = CLU_DOUBLE_BUFFER_AUTO; + du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_CLUDB; + } + +#ifdef CONFIG_PM_SLEEP + du_cmm->reg_save.lut_table = + devm_kzalloc(rcdu->dev, CMM_LUT_NUM * 4, GFP_KERNEL); + if (!du_cmm->reg_save.lut_table) { + ret = -ENOMEM; + goto error_lut_reg_save_buf; + } + for (i = 0; i < CMM_LUT_NUM; i++) + du_cmm->reg_save.lut_table[i] = (i << 16) | (i << 8) | (i << 0); + + du_cmm->reg_save.clu_table = + devm_kzalloc(rcdu->dev, CMM_CLU_NUM * 4, GFP_KERNEL); + if (!du_cmm->reg_save.clu_table) { + ret = -ENOMEM; + goto error_clu_reg_save_buf; + } + for (i = 0; i < CMM_CLU_NUM; i++) + du_cmm->reg_save.clu_table[i] = index_to_clu_data(i); + + init_waitqueue_head(&du_cmm->reg_save.wait); +#endif /* CONFIG_PM_SLEEP */ + if (soc_device_match(rcar_du_cmm_r8a7795_es1)) + du_cmm->soc_support = false; + else + du_cmm->soc_support = true; + + du_cmm->active = false; + du_cmm->init = false; + du_cmm->direct = true; + + mutex_init(&du_cmm->lock); + INIT_LIST_HEAD(&du_cmm->lut.list); + du_cmm->lut.p = NULL; + du_cmm->lut.one_side = false; + INIT_LIST_HEAD(&du_cmm->clu.list); + du_cmm->clu.p = NULL; + du_cmm->clu.one_side = false; + INIT_LIST_HEAD(&du_cmm->hgo.list); + du_cmm->hgo.reset = 0; + + sprintf(name, "du-cmm%d", rcrtc->index); + du_cmm->workqueue = create_singlethread_workqueue(name); + INIT_WORK(&du_cmm->work, du_cmm_work); + + rcrtc->cmm_handle = du_cmm; + + dev_info(rcdu->dev, "DU%d use CMM(%s buffer)\n", + rcrtc->index, du_cmm->dbuf ? "Double" : "Single"); + + return 0; + +#ifdef CONFIG_PM_SLEEP +error_clu_reg_save_buf: +error_lut_reg_save_buf: +#endif /* CONFIG_PM_SLEEP */ +error_clock_cmm: + devm_iounmap(rcdu->dev, du_cmm->cmm_base); +error_mapping_cmm: + devm_kfree(rcdu->dev, du_cmm); +error_alloc: + return ret; +} diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 15dc9ca..864fb94 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -296,6 +296,19 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19); rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + mode->hdisplay - 19); + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM)) { + rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - + mode->hsync_start - 19 - 25); + rcar_du_crtc_write(rcrtc, HDER, mode->htotal - + mode->hsync_start + + mode->hdisplay - 19 - 25); + } else { + rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - + mode->hsync_start - 19); + rcar_du_crtc_write(rcrtc, HDER, mode->htotal - + mode->hsync_start + + mode->hdisplay - 19); + } rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end - mode->hsync_start - 1); rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); @@ -530,6 +543,9 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc) DSYSR_TVM_MASTER); rcar_du_group_start_stop(rcrtc->group, true); + + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM)) + rcar_du_cmm_start_stop(rcrtc, true); } static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc) @@ -565,6 +581,9 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) { struct drm_crtc *crtc = &rcrtc->crtc; + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM)) + rcar_du_cmm_start_stop(rcrtc, false); + /* * Disable all planes and wait for the change to take effect. This is * required as the plane enable registers are updated on vblank, and no @@ -899,6 +918,9 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg) rcar_du_crtc_finish_page_flip(rcrtc); } + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM)) + rcar_du_cmm_kick(rcrtc); + ret = IRQ_HANDLED; } @@ -999,5 +1021,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, return ret; } + rcar_du_cmm_init(rcrtc); + return 0; } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h index 7680cb2..74e0a22 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h @@ -67,6 +67,10 @@ struct rcar_du_crtc { struct rcar_du_group *group; struct rcar_du_vsp *vsp; unsigned int vsp_pipe; + int lvds_ch; + + void *cmm_handle; + }; #define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc) @@ -104,4 +108,16 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc, enum rcar_du_output output); void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc); +/* DU-CMM functions */ +int rcar_du_cmm_init(struct rcar_du_crtc *rcrtc); +int rcar_du_cmm_driver_open(struct drm_device *dev, struct drm_file *file_priv); +void rcar_du_cmm_postclose(struct drm_device *dev, struct drm_file *file_priv); +int rcar_du_cmm_start_stop(struct rcar_du_crtc *rcrtc, bool on); +void rcar_du_cmm_kick(struct rcar_du_crtc *rcrtc); + +#ifdef CONFIG_PM_SLEEP +int rcar_du_cmm_pm_suspend(struct rcar_du_crtc *rcrtc); +int rcar_du_cmm_pm_resume(struct rcar_du_crtc *rcrtc); +#endif /* CONFIG_PM_SLEEP */ + #endif /* __RCAR_DU_CRTC_H__ */ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 02aee6c..838b7c9 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -26,8 +26,8 @@ #include #include #include - #include "rcar_du_drv.h" +#include "rcar_du_encoder.h" #include "rcar_du_kms.h" #include "rcar_du_of.h" #include "rcar_du_regs.h" @@ -128,7 +128,9 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { static const struct rcar_du_device_info rcar_du_r8a7791_info = { .gen = 2, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK - | RCAR_DU_FEATURE_EXT_CTRL_REGS, + | RCAR_DU_FEATURE_EXT_CTRL_REGS + | RCAR_DU_FEATURE_CMM, + .num_crtcs = 2, .channels_mask = BIT(1) | BIT(0), .routes = { /* @@ -190,7 +192,10 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { .gen = 3, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_VSP1_SOURCE, + | RCAR_DU_FEATURE_VSP1_SOURCE + | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, + .num_crtcs = 4, .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), .routes = { /* @@ -222,7 +227,10 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { .gen = 3, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_VSP1_SOURCE, + | RCAR_DU_FEATURE_VSP1_SOURCE + | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, + .num_crtcs = 3, .channels_mask = BIT(2) | BIT(1) | BIT(0), .routes = { /* @@ -250,7 +258,11 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = { .gen = 3, .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS - | RCAR_DU_FEATURE_VSP1_SOURCE, + | RCAR_DU_FEATURE_VSP1_SOURCE + | RCAR_DU_FEATURE_R8A77965_REGS + | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, + .num_crtcs = 3, .channels_mask = BIT(3) | BIT(1) | BIT(0), .routes = { /* @@ -328,6 +340,8 @@ DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops); static struct drm_driver rcar_du_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC, + .open = rcar_du_cmm_driver_open, + .postclose = rcar_du_cmm_postclose, .lastclose = rcar_du_lastclose, .gem_free_object_unlocked = drm_gem_cma_free_object, .gem_vm_ops = &drm_gem_cma_vm_ops, @@ -358,6 +372,12 @@ static int rcar_du_pm_suspend(struct device *dev) { struct rcar_du_device *rcdu = dev_get_drvdata(dev); struct drm_atomic_state *state; + int i; + + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) { + for (i = 0; i < rcdu->num_crtcs; ++i) + rcar_du_cmm_pm_suspend(&rcdu->crtcs[i]); + } drm_kms_helper_poll_disable(rcdu->ddev); drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true); @@ -377,7 +397,20 @@ static int rcar_du_pm_suspend(struct device *dev) static int rcar_du_pm_resume(struct device *dev) { struct rcar_du_device *rcdu = dev_get_drvdata(dev); +#if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI) + struct drm_encoder *encoder; + int i; + + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) { + for (i = 0; (i < rcdu->num_crtcs); ++i) + rcar_du_cmm_pm_resume(&rcdu->crtcs[i]); + } + list_for_each_entry(encoder, &rcdu->ddev->mode_config.encoder_list, + head) { + to_rcar_encoder(encoder); + } +#endif drm_atomic_helper_resume(rcdu->ddev, rcdu->suspend_state); drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false); drm_kms_helper_poll_enable(rcdu->ddev); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index b3a25e8..f2afe36 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -30,8 +30,19 @@ struct rcar_du_device; #define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK (1 << 0) /* Per-CRTC IRQ and clock */ #define RCAR_DU_FEATURE_EXT_CTRL_REGS (1 << 1) /* Has extended control registers */ #define RCAR_DU_FEATURE_VSP1_SOURCE (1 << 2) /* Has inputs from VSP1 */ - -#define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */ +/* Use R8A77965 registers */ +#define RCAR_DU_FEATURE_R8A77965_REGS BIT(3) + +/* Has DEF7R register & CMM */ +#define RCAR_DU_FEATURE_CMM BIT(10) +/* Has CMM LUT Double buffer */ +#define RCAR_DU_FEATURE_CMM_LUT_DBUF BIT(11) +/* Has CMM CLU Double buffer */ +#define RCAR_DU_FEATURE_CMM_CLU_DBUF BIT(12) +/* Align pitches to 128 bytes */ +#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) +/* LVDS lanes 1 and 3 inverted */ +#define RCAR_DU_QUIRK_LVDS_LANES BIT(1) /* * struct rcar_du_output_routing - Output routing specification @@ -61,6 +72,7 @@ struct rcar_du_device_info { unsigned int features; unsigned int quirks; unsigned int channels_mask; + unsigned int num_crtcs; struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX]; unsigned int num_lvds; unsigned int dpll_ch; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index d539cb2..83a2836 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -130,6 +130,11 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) if (rcdu->info->gen >= 3) rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); + if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_CMM)) { + rcar_du_group_write(rgrp, DEF7R, DEF7R_CODE | + DEF7R_CMME1 | DEF7R_CMME0); + } + /* * Use DS1PR and DS2PR to configure planes priorities and connects the * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index 9dfd220..b20e783 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -200,6 +200,11 @@ #define DEFR6_MLOS1 (1 << 2) #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) +#define DEF7R 0x000ec +#define DEF7R_CODE (0x7779 << 16) +#define DEF7R_CMME1 BIT(6) +#define DEF7R_CMME0 BIT(4) + /* ----------------------------------------------------------------------------- * R8A7790-only Control Registers */ @@ -552,4 +557,91 @@ #define GCBCR 0x11098 #define BCBCR 0x1109c +/* ----------------------------------------------------------------------------- + * DU Color Management Module Registers + */ + +#define CMM_LUT_CTRL 0x0000 +#define CMM_LUT_CTRL_EN BIT(0) + +#define CMM_CLU_CTRL 0x0100 +#define CMM_CLU_CTRL_EN BIT(0) +#define CMM_CLU_CTRL_MVS BIT(24) +#define CMM_CLU_CTRL_AAI BIT(28) + +#define CMM_CTL0 0x0180 +#define CM2_CTL0 CMM_CTL0 +#define CMM_CTL0_CLUDB BIT(24) +#define CMM_CTL0_HISTS BIT(20) +#define CMM_CTL0_TM1_MASK (3 << 16) +#define CMM_CTL0_TM1_BT601_YC240 (0 << 16) +#define CMM_CTL0_TM1_BT601_YC255 BIT(16) +#define CMM_CTL0_TM1_BT709_RG255 (2 << 16) +#define CMM_CTL0_TM1_BT709_RG235 (3 << 16) +#define CMM_CTL0_TM0_MASK (3 << 12) +#define CMM_CTL0_TM0_BT601_YC240 (0 << 12) +#define CMM_CTL0_TM0_BT601_YC255 BIT(12) +#define CMM_CTL0_TM0_BT709_RG255 (2 << 12) +#define CMM_CTL0_TM0_BT709_RG235 (3 << 12) +#define CMM_CTL0_TM_BT601_YC240 (CMM_CTL0_TM1_BT601_YC240 |\ + CMM_CTL0_TM0_BT601_YC240) +#define CMM_CTL0_TM_BT601_YC255 (CMM_CTL0_TM1_BT601_YC255 |\ + CMM_CTL0_TM0_BT601_YC255) +#define CMM_CTL0_TM_BT709_RG255 (CMM_CTL0_TM1_BT709_RG255 |\ + CMM_CTL0_TM0_BT709_RG255) +#define CMM_CTL0_TM_BT709_RG235 (CMM_CTL0_TM1_BT709_RG235 |\ + CMM_CTL0_TM0_BT709_RG235) +#define CMM_CTL0_YC BIT(8) +#define CMM_CTL0_VPOL BIT(4) +#define CMM_CTL0_DBUF BIT(0) + +#define CMM_CTL1 0x0184 +#define CM2_CTL1 CMM_CTL1 +#define CMM_CTL1_BFS BIT(0) + +#define CMM_CTL2 0x0188 +#define CMM_HGO_OFFSET 0x0200 +#define CMM_HGO_SIZE 0x0204 +#define CMM_HGO_MODE 0x0208 +#define CMM_HGO_MODE_MASK (0xFF) +#define CMM_HGO_MODE_MAXRGB BIT(7) +#define CMM_HGO_MODE_OFSB_R BIT(6) +#define CMM_HGO_MODE_OFSB_G BIT(5) +#define CMM_HGO_MODE_OFSB_B BIT(4) +#define CMM_HGO_MODE_HRATIO_NO_SKIPP (0 << 2) +#define CMM_HGO_MODE_HRATIO_HALF_SKIPP BIT(2) +#define CMM_HGO_MODE_HRATIO_QUARTER_SKIPP (2 << 2) +#define CMM_HGO_MODE_VRATIO_NO_SKIPP (0 << 0) +#define CMM_HGO_MODE_VRATIO_HALF_SKIPP BIT(0) +#define CMM_HGO_MODE_VRATIO_QUARTER_SKIPP (2 << 0) +#define CMM_HGO_LB_TH 0x020C +#define CMM_HGO_LB0_H 0x0210 +#define CMM_HGO_LB0_V 0x0214 +#define CMM_HGO_LB1_H 0x0218 +#define CMM_HGO_LB1_V 0x021C +#define CMM_HGO_LB2_H 0x0220 +#define CMM_HGO_LB2_V 0x0224 +#define CMM_HGO_LB3_H 0x0228 +#define CMM_HGO_LB3_V 0x022C +#define CMM_HGO_R_HISTO(n) (0x0230 + ((n) * 4)) +#define CMM_HGO_R_MAXMIN 0x0330 +#define CMM_HGO_R_SUM 0x0334 +#define CMM_HGO_R_LB_DET 0x0338 +#define CMM_HGO_G_HISTO(n) (0x0340 + ((n) * 4)) +#define CMM_HGO_G_MAXMIN 0x0440 +#define CMM_HGO_G_SUM 0x0444 +#define CMM_HGO_G_LB_DET 0x0448 +#define CMM_HGO_B_HISTO(n) (0x0450 + ((n) * 4)) +#define CMM_HGO_B_MAXMIN 0x0550 +#define CMM_HGO_B_SUM 0x0554 +#define CMM_HGO_B_LB_DET 0x0558 +#define CMM_HGO_REGRST 0x05FC +#define CMM_HGO_REGRST_RCLEA BIT(0) +#define CMM_LUT_TBLA(n) (0x0600 + ((n) * 4)) +#define CMM_CLU_ADDR 0x0A00 +#define CMM_CLU_DATA 0x0A04 +#define CMM_LUT_TBLB(n) (0x0B00 + ((n) * 4)) +#define CMM_CLU_ADDR2 0x0F00 +#define CMM_CLU_DATA2 0x0F04 + #endif /* __RCAR_DU_REGS_H__ */ diff --git a/include/drm/drm_ioctl.h b/include/drm/drm_ioctl.h index fafb6f5..add4280 100644 --- a/include/drm/drm_ioctl.h +++ b/include/drm/drm_ioctl.h @@ -109,6 +109,13 @@ enum drm_ioctl_flags { */ DRM_ROOT_ONLY = BIT(2), /** + * @DRM_CONTROL_ALLOW: + * + * Deprecated, do not use. Control nodes are in the process of getting + * removed. + */ + DRM_CONTROL_ALLOW = BIT(3), + /** * @DRM_UNLOCKED: * * Whether &drm_ioctl_desc.func should be called with the DRM BKL held From patchwork Wed Apr 3 13:14:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C64F1708 for ; Wed, 3 Apr 2019 13:27:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01C3C28712 for ; Wed, 3 Apr 2019 13:27:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E827D28714; Wed, 3 Apr 2019 13:27:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9FF19286E3 for ; Wed, 3 Apr 2019 13:27:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727025AbfDCN07 (ORCPT ); Wed, 3 Apr 2019 09:26:59 -0400 Received: from de-deferred2.bosch-org.com ([139.15.180.217]:46532 "EHLO de-deferred2.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726157AbfDCNZo (ORCPT ); Wed, 3 Apr 2019 09:25:44 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by fe0vms0193.rbdmz01.com (Postfix) with ESMTPS id 44Z65h0k8vz1s1; Wed, 3 Apr 2019 15:15:52 +0200 (CEST) Received: from fe0vm1650.rbesz01.com (unknown [139.15.230.188]) by si0vms0217.rbdmz01.com (Postfix) with ESMTPS id 44Z65f32sNz4f3kZ4; Wed, 3 Apr 2019 15:15:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297350; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=Op6myLgVUAzrSJMoEUG0D5+DvuGhwI5MTkDjm2q8dehDOiV5/f61aNuIHtydvYswV /ylYlFs/81u1nYJqPCQxspSyTwXZDgzwKr15qajDwFS/5JMomqzKr8ZhpdHx6vLo4g fhTcp+rlmJTE+heIJbPFh/VOWOC/Kd2oTouSaA28= Received: from si0vm2083.rbesz01.com (unknown [10.58.172.176]) by fe0vm1650.rbesz01.com (Postfix) with ESMTPS id 44Z65f2Zjxz1Ck; Wed, 3 Apr 2019 15:15:50 +0200 (CEST) X-AuditID: 0a3aad17-5bfff70000001fa9-2f-5ca4b206dc34 Received: from fe0vm1652.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by si0vm2083.rbesz01.com (SMG Outbound) with SMTP id D9.36.08105.602B4AC5; Wed, 3 Apr 2019 15:15:50 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by fe0vm1652.rbesz01.com (Postfix) with ESMTPS id 44Z65d6zB2zVv5; Wed, 3 Apr 2019 15:15:49 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:48 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Koji Matsuoka , Tsutomu Muroya , Steve Longerbeam Subject: [PATCH 2/8] drm: Add DU CMM support boot and clk changes Date: Wed, 3 Apr 2019 18:44:38 +0530 Message-ID: <1554297284-14009-3-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA21Sb0wbZRzue9c/16Y3joPSn6Uj5rJlcWZbN1QuaszUmDR+mJC4JTNNXFlv bbUFctciTF0QjIkwg5VNaSUUJtkmZmw0w9HJAqs1my3BwRYZ6MBMlkykDDDdYCziHYW1H/z2 e58/v+d9n7wETg+qDISzzMPxZVYXo9TINc+f2bhNGeqwmKaGFWwwOqRgbyTvKdnFln6MnT86 oWCvX2xRsj1/zWLsj6MDOHvqzAl8N2Hu7FjEzZMNVzDzD8laZL4/6JOb/wkVFCve0rxo41zO So7f8dIBjeOOv6Qi+QWqmuzLq0EL3npEEEA9A0NXPqxHaoKmmjG4P6qrRxpx7kNwLvC7KnWY QXC9/TgmqZTUNujv7l4lcqlvETTMXsCkA07FEERiiVVVDvUyfJyow6VZTm2Cc40jSmkmqb0Q n7mBpBmoAhgb+nRVo6b2QfDqlDJ1j70QXFxQpPTZ8LN/Si7NOAVw+e5dPHXtJyHcrvwcUYEM VSBD1YawTqQTnKZK9y4TW7idL+WEw6ad2w+Wu0Mo1bW+F5369VAEUQRitGTTlx0WWmGtFKrd EfQsgTE68rkjIrShtNxW7bAKjrd5r4sTGANpvPa6hc55DAveUrdTEJzlZREEBM7kkoONbRaa tFmrD3N8ecoWQfmEnNGTduINC03ZrR7uXY6r4Ph19gWCYIDM7RYDs3nOzlUdcro86zSzkUQy mYzOy2QyYzFCHUGFhFbMxqQVpFBhdQtO+5r9iZSdXkfT1hgqMujJYslDSazDW/Y41WAkZXda LbQug0g7p9FNJPaWQ74nmbXiN07nAZkvVZS9BqZNuzpED9VAQ7+vBM431iFo7U0iGLn4AINo 4hscJppGcWg52aUQsYAKloa7VPBo7LwaJse+V4P/WK8GPrlVq4W56DUtLB+PkRAfv7wBVv4M Z8HSpeEsaO38joLm5AoF841tNFydukTD6bk4DX//9lEO3A4M6GBiOqSH2XBPPtSO9OWLW04a 4d9fokYIxZaM0vqCabFLTOyS9QalLj1Wz/90uYamH2eoQWcf7Gnbuvvr2nce1um7Dow2JQbw zaeP7A/tMy2ftdF/bCqaWJkpeLqwJOuVN+c/8PvYRw9teT9tTvSwhN83fqt4vwOxy6724FO6 5aKvFi54su+RUVd4C1l1s+bo/PsjzTQfvx2use/47NhCe3xysGF8+jXZHvLViGpO8G3hDg73 MHLBYd25FecF63/G7S6TXwQAAA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh This is the out-of-tree patch for DU CMM driver support from Yocto release v3.4.0. Link: https://github.com/renesas-rcar/du_cmm/commit/2d8ea2b667ad4616aa639c54ecc11f7c4b58959d.patch Following is from the patch description: du_cmm: Release for Yocto v3.4.0 This patch made the following correspondence. - Corresponds to kernel v 4.14. - Double buffer only is supported. - Fix CLU / LUT update timing. - Add CMM Channel occupation mode. - Fix Close process. Signed-off-by: Koji Matsuoka Signed-off-by: Tsutomu Muroya Signed-off-by: Steve Longerbeam - Resolved checkpatch errors - Resolved merge conflicts according to latest version - In patch included boot and clock files from base patch Signed-off-by: kalakodima venkata rajesh --- .../boot/dts/renesas/r8a7795-es1-salvator-x.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 5 + .../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 29 +++++- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 6 +- .../arm64/boot/dts/renesas/r8a7796-salvator-xs.dts | 4 + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 25 ++++- .../arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 7 +- .../boot/dts/renesas/r8a77965-salvator-xs.dts | 7 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 27 +++++- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 + drivers/clk/renesas/r8a7796-cpg-mssr.c | 3 + drivers/clk/renesas/r8a77965-cpg-mssr.c | 106 ++++++++++++++++++++- 13 files changed, 217 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts index 6b5fa91..45c1f8a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts @@ -41,11 +41,16 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, + <&cpg CPG_MOD 708>, <&versaclock5 1>, <&x21_clk>, <&x22_clk>, <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 446822f..67b64e7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -41,11 +41,16 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, + <&cpg CPG_MOD 708>, <&versaclock5 1>, <&x21_clk>, <&x22_clk>, <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index 8ded64d0..adcacea 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -41,11 +41,16 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, + <&cpg CPG_MOD 708>, <&versaclock6 1>, <&x21_clk>, <&x22_clk>, <&versaclock6 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index fb9d08a..aa5fc3c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2783,8 +2783,13 @@ du: display@feb00000 { compatible = "renesas,du-r8a7795"; reg = <0 0xfeb00000 0 0x80000>, - <0 0xfeb90000 0 0x14>; - reg-names = "du", "lvds.0"; + <0 0xfeb90000 0 0x14>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>, + <0 0xfea60000 0 0x00001000>, + <0 0xfea70000 0 0x00001000>; + reg-names = "du", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "cmm.3"; interrupts = , , , @@ -2793,8 +2798,24 @@ <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, - <&cpg CPG_MOD 727>; - clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; + <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, + <&cpg CPG_MOD 708>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "cmm.3"; + resets = <&cpg 724>, + <&cpg 724>, + <&cpg 722>, + <&cpg 722>, + <&cpg 727>, + <&cpg 711>, + <&cpg 710>, + <&cpg 709>, + <&cpg 708>; + reset-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "cmm.3"; vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 052d72a..abe24e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -30,18 +30,22 @@ <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, <&versaclock5 1>, <&x21_clk>, <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "dclkin.0", "dclkin.1", "dclkin.2"; + }; &sound_card { dais = <&rsnd_port0 /* ak4613 */ &rsnd_port1>; /* HDMI0 */ }; - &hdmi0 { status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts index 8860be6..6c3af11 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts @@ -30,10 +30,14 @@ <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, <&versaclock6 1>, <&x21_clk>, <&versaclock6 2>; clock-names = "du.0", "du.1", "du.2", "lvds.0", + "cmm.0", "cmm.1", "cmm.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index cbd35c0..729b2b6 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -2438,16 +2438,33 @@ du: display@feb00000 { compatible = "renesas,du-r8a7796"; reg = <0 0xfeb00000 0 0x70000>, - <0 0xfeb90000 0 0x14>; - reg-names = "du", "lvds.0"; + <0 0xfeb90000 0 0x14>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>, + <0 0xfea60000 0 0x00001000>; + reg-names = "du", "lvds.0", + "cmm.0", "cmm.1", "cmm.2"; interrupts = , , ; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 727>; - clock-names = "du.0", "du.1", "du.2", "lvds.0"; + <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", + "cmm.0", "cmm.1", "cmm.2"; + resets = <&cpg 724>, + <&cpg 724>, + <&cpg 722>, + <&cpg 727>, + <&cpg 711>, + <&cpg 710>, + <&cpg 709>; + reset-names = "du.0", "du.1", "du.2", "lvds.0", + "cmm.0", "cmm.1", "cmm.2"; status = "disabled"; vsps = <&vspd0 &vspd1 &vspd2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts index 340a3c7..20992e2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts @@ -24,10 +24,15 @@ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 708>, <&versaclock5 1>, <&x21_clk>, <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", + clock-names = "du.0", "du.1", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index 9de4e3d..eb02075 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -24,10 +24,15 @@ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 708>, <&versaclock6 1>, <&x21_clk>, <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.3", + clock-names = "du.0", "du.1", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0cd4446..37382b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1801,15 +1801,34 @@ du: display@feb00000 { compatible = "renesas,du-r8a77965"; - reg = <0 0xfeb00000 0 0x80000>; - reg-names = "du"; + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>, + <0 0xfea70000 0 0x00001000>; + reg-names = "du", "lvds.0", + "cmm.0", "cmm.1", "cmm.3"; interrupts = , , ; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 708>; + clock-names = "du.0", "du.1", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.3"; + resets = <&cpg 724>, + <&cpg 724>, + <&cpg 722>, + <&cpg 727>, + <&cpg 711>, + <&cpg 710>, + <&cpg 708>; + reset-names = "du.0", "du.1", "du.3", "lvds.0", + "cmm.0", "cmm.1", "cmm.3"; status = "disabled"; vsps = <&vspd0 0 &vspd1 0 &vspd0 1>; diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index a85dd50..ba9e595 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -201,6 +201,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), + DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1), + DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1), DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index dfb267a..9f01fda 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -180,6 +180,9 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), + DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1), DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), DEF_MOD("du2", 722, R8A7796_CLK_S2D1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 8fae5e9..cac4570 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -123,7 +123,6 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), - DEF_MOD("cmt3", 300, R8A77965_CLK_R), DEF_MOD("cmt2", 301, R8A77965_CLK_R), DEF_MOD("cmt1", 302, R8A77965_CLK_R), @@ -215,6 +214,111 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2), DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2), + DEF_MOD("3dge", 112, R8A77965_CLK_ZG), + DEF_MOD("fdp0", 119, R8A77965_CLK_S0D1), + DEF_MOD("vcplf", 130, R8A77965_CLK_S0D2), + DEF_MOD("vdpb", 131, R8A77965_CLK_S0D2), + DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), + DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), + DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), + DEF_MOD("scif1", 206, R8A77965_CLK_S3D4), + DEF_MOD("scif0", 207, R8A77965_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A77965_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77965_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77965_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77965_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), + DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), + DEF_MOD("cmt3", 300, R8A77965_CLK_R), + DEF_MOD("cmt2", 301, R8A77965_CLK_R), + DEF_MOD("cmt1", 302, R8A77965_CLK_R), + DEF_MOD("cmt0", 303, R8A77965_CLK_R), + DEF_MOD("scif2", 310, R8A77965_CLK_S3D4), + DEF_MOD("sdif3", 311, R8A77965_CLK_SD3), + DEF_MOD("sdif2", 312, R8A77965_CLK_SD2), + DEF_MOD("sdif1", 313, R8A77965_CLK_SD1), + DEF_MOD("sdif0", 314, R8A77965_CLK_SD0), + DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1), + DEF_MOD("rwdt0", 402, R8A77965_CLK_R), + DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77965_CLK_S3D1), + DEF_MOD("audmac0", 502, R8A77965_CLK_S3D4), + DEF_MOD("audmac1", 501, R8A77965_CLK_S3D4), + DEF_MOD("adsp", 506, R8A77965_CLK_S1D1), + DEF_MOD("drif7", 508, R8A77965_CLK_S3D2), + DEF_MOD("drif6", 509, R8A77965_CLK_S3D2), + DEF_MOD("drif5", 510, R8A77965_CLK_S3D2), + DEF_MOD("drif4", 511, R8A77965_CLK_S3D2), + DEF_MOD("drif3", 512, R8A77965_CLK_S3D2), + DEF_MOD("drif2", 513, R8A77965_CLK_S3D2), + DEF_MOD("drif1", 514, R8A77965_CLK_S3D2), + DEF_MOD("drif0", 515, R8A77965_CLK_S3D2), + DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1), + DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1), + DEF_MOD("thermal", 522, R8A77965_CLK_CP), + DEF_MOD("pwm", 523, R8A77965_CLK_S3D4), + DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2), + DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2), + DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1), + DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2), + DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2), + DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2), + DEF_MOD("vspb", 626, R8A77965_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1), + DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4), + DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1), + DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), + DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), + DEF_MOD("du3", 721, R8A77965_CLK_S2D1), + DEF_MOD("du1", 723, R8A77965_CLK_S2D1), + DEF_MOD("du0", 724, R8A77965_CLK_S2D1), + DEF_MOD("lvds", 727, R8A77965_CLK_S2D1), + DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI), + DEF_MOD("vin7", 804, R8A77965_CLK_S0D2), + DEF_MOD("vin6", 805, R8A77965_CLK_S0D2), + DEF_MOD("vin5", 806, R8A77965_CLK_S0D2), + DEF_MOD("vin4", 807, R8A77965_CLK_S0D2), + DEF_MOD("vin3", 808, R8A77965_CLK_S0D2), + DEF_MOD("vin2", 809, R8A77965_CLK_S0D2), + DEF_MOD("vin1", 810, R8A77965_CLK_S0D2), + DEF_MOD("vin0", 811, R8A77965_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6), + DEF_MOD("sata0", 815, R8A77965_CLK_S3D2), + DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6), + DEF_MOD("adg", 922, R8A77965_CLK_S0D1), + DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP), + DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2), + DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), From patchwork Wed Apr 3 13:14:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE373139A for ; Wed, 3 Apr 2019 13:27:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95DC328714 for ; Wed, 3 Apr 2019 13:27:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A5E128712; Wed, 3 Apr 2019 13:27:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25FD4286EE for ; Wed, 3 Apr 2019 13:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726157AbfDCN1H (ORCPT ); Wed, 3 Apr 2019 09:27:07 -0400 Received: from de-deferred1.bosch-org.com ([139.15.180.216]:41828 "EHLO de-deferred1.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726099AbfDCNZo (ORCPT ); Wed, 3 Apr 2019 09:25:44 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by si0vms0224.rbdmz01.com (Postfix) with ESMTPS id 44Z65j5x4qz2B7; Wed, 3 Apr 2019 15:15:53 +0200 (CEST) Received: from fe0vm1650.rbesz01.com (unknown [139.15.230.188]) by si0vms0216.rbdmz01.com (Postfix) with ESMTPS id 44Z65h17Xnz1XLG6y; Wed, 3 Apr 2019 15:15:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297352; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=wIn5Vtavye/rf6cEcqrKUWBXG6QzQvdITVPu2UguBBmN0tQsihMGnLaUYvzryY2gF 4XT0P7LoWKe7Exf+PV+x61b73KTU9wcHNRGGMbl300N7y8//M1WL5M8FzSaEqXPwqn Mb+ukwLv4jKT1UkuUAp7wXtZqvVfXNldR7R0FAgQ= Received: from si0vm4642.rbesz01.com (unknown [10.58.172.176]) by fe0vm1650.rbesz01.com (Postfix) with ESMTPS id 44Z65h0m1wz1Cj; Wed, 3 Apr 2019 15:15:52 +0200 (CEST) X-AuditID: 0a3aad12-be3ff70000006e39-4a-5ca4b207a31e Received: from si0vm1949.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by si0vm4642.rbesz01.com (SMG Outbound) with SMTP id B2.3D.28217.702B4AC5; Wed, 3 Apr 2019 15:15:51 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by si0vm1949.rbesz01.com (Postfix) with ESMTPS id 44Z65g6KBpz6CjZqr; Wed, 3 Apr 2019 15:15:51 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:50 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Harsha M M , Eugeniu Rosca Subject: [PATCH 3/8] drm: rcar-du: Give a name to clu table samples Date: Wed, 3 Apr 2019 18:44:39 +0530 Message-ID: <1554297284-14009-4-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA22SfUxTVxjGObdfl64XDheKry1VcyPZYoJDR1mjxrnsH7JswWRjC1udu4xr 29gPcm8hgsYwMcLaiRqJE0KoLJgAus02ouVjw5VOkDmVQszYcGyJSyhRURhTXMa8l4LtH/vv Pc/z/s6T8+SQMrpXpSNtTjfHO1k7o1TL1Vu+MuSoAm3m3IHFrSZf+IbCNDY/ozR1/neYMD36 /DeFabSnWWnqij4gdigLmmrPqQomvYNEwVxgzU7ZB+ptpZzdVsHxL2//WG2dGBgiyjz6fS0d w/JqdFTrQckk4DwYuzCn9CA1SePTBPxz/4pCMmjcj+BKHxsz7iGI1HjkkqHEOdDv96skIwN3 IPA+uExIBxk+i6CmK7SEp+M3oCbwF5JmOV4P11tnl2YKF0Hw1O8olr0Gxm98JpPmZPwe+Ibu KmPRReB7MquI7afBtca7S8kyDPD91JS4T4rsOuhuVR5HuClhqylh6wwiOpFWsOVWOPLy8zZv 5Es4oSp308ZPXI4AijVLB5H/9p4QwiRiNNRIY5uZVrAVQqUjhIwkwWip/IOilFLiKq20soJ1 N19u5wRGR2XdetNMpz+XhfISh00QbC5nCAEpYzKo68fOmGmqlK2s4nhXDAshPSlnVlEWstBM Ywvr5vZyXBnHr7hbSZIBKsMvBqbxnIXbt8dmd6/YjIFCSUlJdGaikxhLkMkh9AqpEbMJ6QpK KGMdgs2yjK+O4fSKGkeH0au6VdROicGSay13Pk/VZVFJf7aYaW2CESen0TgSe0un/v1GhDXi p43nAaWXKkpbFuPQ5rMigz0aiNZWI2gJziNoP3FEDr6rDQr47tSMAnrbvCqI9DSpYHL8UjI0 NgTV0NzZp4FrtXc08LD9KAXRwboUmPsinAIL346kQnc4mgonvo5oYWLoQibU1x1aDcd+Devg XjSoh8Wb4SwIDC9kwZO2HwxwfubLtTA2V78OTv50kYGTfQMMjNSPMrB427MegpEfs+HiHe+L 02KZhFimqdwnlelm3f9T5rIaf52uGjnUs3Xz9k8naco+pevKsU728JYDC+Oz5OHUtwoN54tz posm8jsiu97J3PFLT3ro6uNA9uBoY/VUw0tVwQN/GN6ffqG49fWqR8dl+4sWFU+PpBTv3p+t b7/Z/dHAudc+3NDv7zb+7Xy713m6sDD3Z2zk9M58Yy2qbyjuMI6FLrve9TJywcpu2iDjBfYZ vQA+Uk4EAAA= Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh Replace the hardcoded value of clu table sample count with a meaningful name. Signed-off-by: Harsha M M This is the out-of-tree patch for DU CMM driver support from Yocto release v3.6.0. The part of this patch adding CMM support to the new Rcar E3 (R8A77990) SoC was filtered out due to lack of Yocto v3.6.0 (i.e. rcar-3.6.2) kernel updates on staging-414. Link: https://github.com/renesas-rcar/du_cmm/commit/53973b806881ed8f54500b0d42bdc40aaca60476.patch Following is from the patch description: Subject: [PATCH] du_cmm: Release for Yocto v3.6.0 This patch made the following correspondence. - R-Car E3(R8A77990) device support. - Fix rewritting of parameter procedure in rcar_du_cmm_postclose Signed-off-by: Eugeniu Rosca - Resolved checkpatch errors - Resolved merge conflicts according to latest version Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c index ac613a6e..d380dd9 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c @@ -75,9 +75,9 @@ #include /* #define DEBUG_PROCE_TIME 1 */ - +#define CMM_CLU_SAMPLES 17 #define CMM_LUT_NUM 256 -#define CMM_CLU_NUM (17 * 17 * 17) +#define CMM_CLU_NUM (CMM_CLU_SAMPLES * CMM_CLU_SAMPLES * CMM_CLU_SAMPLES) #define CMM_HGO_NUM 64 /* rcar_du_drm.h Include */ #define LUT_DOUBLE_BUFFER_AUTO 0 @@ -211,11 +211,11 @@ static inline u32 index_to_clu_data(int index) { int r, g, b; - r = index % 17; - index /= 17; - g = index % 17; - index /= 17; - b = index % 17; + r = index % CMM_CLU_SAMPLES; + index /= CMM_CLU_SAMPLES; + g = index % CMM_CLU_SAMPLES; + index /= CMM_CLU_SAMPLES; + b = index % CMM_CLU_SAMPLES; r = (r << 20); if (r > (255 << 16)) @@ -630,9 +630,9 @@ static int clu_table_copy(struct rcar_du_cmm *du_cmm) } rcar_du_cmm_write(du_cmm, dst_addr, 0); - for (i = 0; i < 17; i++) { - for (j = 0; j < 17; j++) { - for (k = 0; k < 17; k++) { + for (i = 0; i < CMM_CLU_SAMPLES; i++) { + for (j = 0; j < CMM_CLU_SAMPLES; j++) { + for (k = 0; k < CMM_CLU_SAMPLES; k++) { rcar_du_cmm_write(du_cmm, src_addr, (k << 16) | (j << 8) | (i << 0)); @@ -912,9 +912,9 @@ int rcar_du_cmm_pm_suspend(struct rcar_du_crtc *rcrtc) } index = 0; - for (i = 0; i < 17; i++) { - for (j = 0; j < 17; j++) { - for (k = 0; k < 17; k++) { + for (i = 0; i < CMM_CLU_SAMPLES; i++) { + for (j = 0; j < CMM_CLU_SAMPLES; j++) { + for (k = 0; k < CMM_CLU_SAMPLES; k++) { rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR, (k << 16) | (j << 8) | (i << 0)); @@ -1014,6 +1014,8 @@ void rcar_du_cmm_postclose(struct drm_device *dev, struct drm_file *file_priv) for (crtcs_cnt = 0; crtcs_cnt < rcdu->num_crtcs; crtcs_cnt++) { rcrtc = &rcdu->crtcs[crtcs_cnt]; du_cmm = rcrtc->cmm_handle; + if (!du_cmm) + continue; if (du_cmm->authority && du_cmm->pid == task_pid_nr(current)) { du_cmm->authority = false; du_cmm->pid = 0; From patchwork Wed Apr 3 13:14:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883787 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AFFEA1708 for ; Wed, 3 Apr 2019 13:27:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98FE028712 for ; Wed, 3 Apr 2019 13:27:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8CC8F2871A; Wed, 3 Apr 2019 13:27:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C96328712 for ; Wed, 3 Apr 2019 13:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726412AbfDCNZn (ORCPT ); Wed, 3 Apr 2019 09:25:43 -0400 Received: from de-deferred2.bosch-org.com ([139.15.180.217]:46226 "EHLO de-deferred2.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725959AbfDCNZm (ORCPT ); Wed, 3 Apr 2019 09:25:42 -0400 X-Greylist: delayed 590 seconds by postgrey-1.27 at vger.kernel.org; Wed, 03 Apr 2019 09:25:39 EDT Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by fe0vms0193.rbdmz01.com (Postfix) with ESMTPS id 44Z65l3CvMz1rb; Wed, 3 Apr 2019 15:15:55 +0200 (CEST) Received: from fe0vm1650.rbesz01.com (unknown [139.15.230.188]) by si0vms0216.rbdmz01.com (Postfix) with ESMTPS id 44Z65j5SmHz1XLG78; Wed, 3 Apr 2019 15:15:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297353; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=C6U+4ig9Ag3M8aIOEaX8p3mPVvZt9bLkdnmEFGOnF9EjeUrHyxLS9SQA0slyp4a6t jM82o2sm5jjQiozHRP4jes9xwHYTf9BXozVKeig1Jy6E92CYlSdBM9AujaCX++RU/t Mbzm9oi8Qh+5QE84Dxar9m9PacWtOvT+wpgw9LFU= Received: from fe0vm1741.rbesz01.com (unknown [10.58.172.176]) by fe0vm1650.rbesz01.com (Postfix) with ESMTPS id 44Z65j53Jjz1Ct; Wed, 3 Apr 2019 15:15:53 +0200 (CEST) X-AuditID: 0a3aad15-c71ff70000001b94-1a-5ca4b209b20b Received: from fe0vm1652.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by fe0vm1741.rbesz01.com (SMG Outbound) with SMTP id 91.A7.07060.902B4AC5; Wed, 3 Apr 2019 15:15:53 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by fe0vm1652.rbesz01.com (Postfix) with ESMTPS id 44Z65j3gKvzVv7; Wed, 3 Apr 2019 15:15:53 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:51 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Harsha M M Subject: [PATCH 4/8] drm: rcar-du: Refactor the code with new functions Date: Wed, 3 Apr 2019 18:44:40 +0530 Message-ID: <1554297284-14009-5-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA21Sa0xTZxjmO71wWjnzcCjzXQXmTjBLzOioq9KI8fbDGX4ocZEtpiiHcaAN bSE9bQN4SZfIDGCVWDUbYmGmghqm0A2sKMganeUSN4VFIUQdwyjEotycJDN6DgXbH/v3fs/l e77vyYuLqEvRStxgtrIWM2OkpXKxfN3PiSkyr0eXOn55pbbu5h2JdmD2hVQ7eeShRNvfXivV to5NYJsk2x5V3ca2TXuTMrHd8vV5rNFgZy2fb8iR6385Xi4pHlla8vL3QZED3SIqEY4DqYHO 8zmVSIZT5A8YVJaLKpGcn68j+Oc/BxY6PEfQ/OuoVFBJyRS40dISLRAK8gKCqokrmECIyP3g dHmihTmO/BI6W/+dx8VkMrh6ZuZngtwFrSNN8xogk2DwToVImGVkFtQFQgEUr6l7PSUJ6WOh +8dRceh+gN+ePROFXr0Crv4krUZkTYSqJkJVj7CLKD6fTbWb1GkatcqSy3JlqWrVt0UmLwq1 Ge9DL8fy/YjEER1DuE55dJSEsXOlJj9ag2N0PLH2IA99kFuUV6pnOP1ei83IcrSSSPgzQ0fF vYc5W67JwHGGIrMfAS6iFUTfsXodReQxpWWspShk86PluJheRhTgO3QUWcBY2UKWLWYti2w6 jtNAKFr4wFgLW8CW5BuM1kWaTiRQVFQU9WEkExmL4TI/+gKP4bMx4QqCK2ZMnKFgwf5RyE4t omFrD0pTLiMyBQ8psHqb+X2qMoGIeuLWUfERRNg5jh4gvrc44s1l3hzDL2o4D4jlQkWxC2DY tNrDe8gmCQSaS2HssAOB2zeL4Oa1UxJ4NNgmg4GKtiXQNO2kwHXyqQK8PXMJMNHm/RhGhh2f gK/WTYO7/RYNd4/20+C717sSAo+n1TB391Ia/H1tKB0mpwY2wPSF9o0w3BLcCAMu32aYCc5t 5lfWnQE1zqfb4cREcAec7Ti7E44GDmdB90yDDo4732SDd/JQDvQ97GLG+S4xvkutrU7o0spY /6fLBTT8OaUDHeiocL4lTAc3/VVYXfj4nOJF8u2s/G/2XByqrb7yZGirJrivK3F4/ZY/gp3Z p+mq5Krxeo9CZWg2vhWvKinO7k83lwS/03xdNvtqqkFlf92bdLV5r/Wzr4x+3+q+6N33s9Ia PSpVh6a8MdCtsduYdWfM91wnRo9M7vk+09lbP+b+lBZzeka9SmThmHcOimVFQQQAAA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh - Introduce new functions for queueing clu and lut events. - Functionality remains same, only some code is moved to new functions. Signed-off-by: Harsha M M - Resolved checkpatch errors - Resolved merge conflicts according to latest version Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c index d380dd9..7983039 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c @@ -246,6 +246,44 @@ static void du_cmm_clk(struct rcar_du_cmm *du_cmm, bool on) clk_disable_unprepare(du_cmm->clock); } +static void rcar_du_cmm_queue_lut_update(struct rcar_du_cmm_pending_event *p) +{ + mutex_lock(&cmm_event_lock); + + list_add_tail(&p->link, &p->du_cmm->lut.list); + + if (p->fpriv) + list_add_tail(&p->fpriv_link, &p->fpriv->list); + + event_prev_cancel_locked(&p->du_cmm->lut); + + if (p->du_cmm->direct) + queue_work(p->du_cmm->workqueue, &p->du_cmm->work); + + mutex_unlock(&cmm_event_lock); + + drm_crtc_vblank_get(&p->du_cmm->rcrtc->crtc); +} + +static void rcar_du_cmm_queue_clu_update(struct rcar_du_cmm_pending_event *p) +{ + mutex_lock(&cmm_event_lock); + + list_add_tail(&p->link, &p->du_cmm->clu.list); + + if (p->fpriv) + list_add_tail(&p->fpriv_link, &p->fpriv->list); + + event_prev_cancel_locked(&p->du_cmm->clu); + + if (p->du_cmm->direct) + queue_work(p->du_cmm->workqueue, &p->du_cmm->work); + + mutex_unlock(&cmm_event_lock); + + drm_crtc_vblank_get(&p->du_cmm->rcrtc->crtc); +} + int rcar_du_cmm_start_stop(struct rcar_du_crtc *rcrtc, bool on) { struct rcar_du_cmm *du_cmm = rcrtc->cmm_handle; From patchwork Wed Apr 3 13:14:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 71DCF139A for ; Wed, 3 Apr 2019 13:26:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60E8D286E3 for ; Wed, 3 Apr 2019 13:26:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 55813286E5; Wed, 3 Apr 2019 13:26:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 956FA286E3 for ; Wed, 3 Apr 2019 13:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726105AbfDCN0C (ORCPT ); Wed, 3 Apr 2019 09:26:02 -0400 Received: from de-deferred1.bosch-org.com ([139.15.180.216]:41966 "EHLO de-deferred1.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726396AbfDCNZq (ORCPT ); Wed, 3 Apr 2019 09:25:46 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by si0vms0224.rbdmz01.com (Postfix) with ESMTPS id 44Z65n1lNKz2Ds; Wed, 3 Apr 2019 15:15:57 +0200 (CEST) Received: from fe0vm1650.rbesz01.com (unknown [139.15.230.188]) by si0vms0216.rbdmz01.com (Postfix) with ESMTPS id 44Z65l46hPz1XLG70; Wed, 3 Apr 2019 15:15:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297355; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=M2jU7Og1ZG8Gdo5PJ/y7h07M7tj3Rlvhi92DMIejYLlRT63V2aryyraRz11473yCg 5PG9nf7n+zm5uOtZU4pFqCI5J25T2KtP60g3t9MTGEiIRgXHKBW3M9ZBRWBsCtV722 RbbTnH5zK0iP+pVbiySB7o6cT+ZsmSeSLwQzLX/w= Received: from si0vm4642.rbesz01.com (unknown [10.58.172.176]) by fe0vm1650.rbesz01.com (Postfix) with ESMTPS id 44Z65l3pzdz1Cj; Wed, 3 Apr 2019 15:15:55 +0200 (CEST) X-AuditID: 0a3aad12-be3ff70000006e39-60-5ca4b20b87e7 Received: from fe0vm1652.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by si0vm4642.rbesz01.com (SMG Outbound) with SMTP id E5.3D.28217.B02B4AC5; Wed, 3 Apr 2019 15:15:55 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by fe0vm1652.rbesz01.com (Postfix) with ESMTPS id 44Z65l29NyzVv5; Wed, 3 Apr 2019 15:15:55 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:53 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Harsha M M Subject: [PATCH 5/8] drm: rcar-du: Implement interfaces to set clu and lut using drm data structures Date: Wed, 3 Apr 2019 18:44:41 +0530 Message-ID: <1554297284-14009-6-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA21SbUwTZxzvc3dtj9Ibx0Hhv4Jku5moMzhERjpnzJLtg9tiJEs0hnRZD3vS ur6wXsuE+ULcFlmhKHHZZqdUBBNngElhKkwlNDpXJQzrhjZBS5GRwhasbGbMaPRuBdsP+/Y8 v9fnfjkSZ/qVWtJsc/IOG2dhFSpCtbZzSWG6v11fdPki6HyXhuW6Xx/cU+juN96R6270H1Ho fpiexd6Qb4g0XME2/OUvKMPKVeuMvMVczTteWW9QmRoueImq6Y07IxemsDo0td6N0kigS+DI L5cJN1KRDP0NBpG503jich7B5MgQlrj8iaBn/HO5ZFHQhTDQ3a2UiGz6OwQNs2cxicDpXeA5 1K6Uzlm0EfyN58VckiTopRCa3SjBFL0ZJs48ViSqCyA8/AUundPoLeD7efI/nBE1vvk5eUKf CcHDk0QiHmAwFsOlSKBfgL5WxUFEe1NU3hTVMYSdQhrBXFRtLSktKV7lqOCF2qLVq7bZrX6U mJM5h7pHtwcQTSJWTV0/3K5n5Fy1UGMNoFdJjNVQpXtE6LkKu7HGxAmmDxwuCy+wWip/5B09 k/UMFlwVVrMgmO22AAISZ7OpoQPH9Axl5GpqeYc9YQugPJJgc6lKcpOeoSs5J/8hz1fxjkX2 dZJkgcruFgszHXwlv3O72eJcpNklFJLJZExOKpNai5FpAbSGVIvdmBRBCVWcVTBXLtifT9iZ RTRpvYreJAf/iR7FGcJmt/HaXKpM8tOS0uSyPXuBNp+S/d6iZzQpRDJlBt1E4oZZ1OPvRbNa /GuT3UDlSXNlLoBJU3Gb6KHj2dAzsQWCY7then8dAu/1FgQt5x4geOT/FIMvI1EM4rGf5HB/ sF4Bsc+uKiDU71VCJHwmDToiB9RwY+ahGuInPRT0zlyhwHdrnoLY/L4MaJm/mQH/eo5mQl8w xMCTtqBGlAxpoLkrpIGBr8MacHvuaKCprSkHet1dOeD9Y18ufHVqIhfGGm/lwdhIKH9GnBUT Z9W5fNKsTs75P7MuoMlv09aht47PfRvbvPbi1mjBu8teNDwcd+lal1bv7agKD/dG40rD3a35 60aNhrsrrpWX3espdaf3lIfff+30o7/r9wY7Px612vp+/OQl1a6PNvVFdwh4K9l0Qra7uXm8 sKPj7YFOg2UyIx6OCqb3hoj9x9NH6j3LbtcOT+05WFbctfzQb232lTaWEEzc6pdxh8A9BZg+ VqFNBAAA Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh Impelement interfaces in cmm to set clu and lut tables using standard drm data structures as input. Signed-off-by: Harsha M M - Resolved checkpatch errors - Resolved merge conflicts according to latest version Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 256 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 11 ++ 2 files changed, 254 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c index 7983039..af4668f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c @@ -114,6 +114,8 @@ struct rcar_du_cmm_pending_event { struct drm_gem_object *gem_obj; struct rcar_du_cmm *du_cmm; struct rcar_du_cmm_file_priv *fpriv; + unsigned int *lut_buf; + unsigned int *clu_buf; }; struct cmm_module_t { @@ -238,14 +240,6 @@ static long long diff_timevals(struct timeval *start, struct timeval *end) } #endif -static void du_cmm_clk(struct rcar_du_cmm *du_cmm, bool on) -{ - if (on) - clk_prepare_enable(du_cmm->clock); - else - clk_disable_unprepare(du_cmm->clock); -} - static void rcar_du_cmm_queue_lut_update(struct rcar_du_cmm_pending_event *p) { mutex_lock(&cmm_event_lock); @@ -284,6 +278,223 @@ static void rcar_du_cmm_queue_clu_update(struct rcar_du_cmm_pending_event *p) drm_crtc_vblank_get(&p->du_cmm->rcrtc->crtc); } +static s64 rcar_du_cmm_multiply_coeff(unsigned int color, s64 coeff) +{ + s64 r_val; + bool is_neg = false; + + if (coeff & BIT_ULL(63)) { + is_neg = true; + coeff &= ~BIT_ULL(63); + } + + r_val = DIV_ROUND_CLOSEST(((s64)(color * coeff)), BIT_ULL(32)); + + if (is_neg) + return -r_val; + + return r_val; +} + +static unsigned int rcar_du_cmm_scalar_product(unsigned int r, unsigned int g, + unsigned int b, s64 coeff1, + s64 coeff2, s64 coeff3) +{ + s64 product; + + product = rcar_du_cmm_multiply_coeff(r, coeff1) + + rcar_du_cmm_multiply_coeff(g, coeff2) + + rcar_du_cmm_multiply_coeff(b, coeff3); + + return (unsigned int)clamp_val(product, 0, U8_MAX); +} + +#ifdef DEBUG_PROCE_TIME +static long long diff_timevals(struct timeval *start, struct timeval *end) +{ + return (end->tv_sec * 1000000LL + end->tv_usec) - + (start->tv_sec * 1000000LL + start->tv_usec); +} +#endif + +void *rcar_du_cmm_alloc_lut(void *cmm_handle) +{ + struct rcar_du_cmm_pending_event *p; + + if (!cmm_handle) + return NULL; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return NULL; + + p->gem_obj = NULL; + p->event = CMM_EVENT_LUT_DONE; + p->stat = QUE_STAT_PENDING; + p->callback_data = 0; + p->du_cmm = cmm_handle; + p->fpriv = NULL; + p->lut_buf = kmalloc(CMM_LUT_NUM * 4, GFP_KERNEL); + if (!p->lut_buf) { + kfree(p); + return NULL; + } + + return p; +} + +void rcar_du_cmm_free_lut(void *lut_handle) +{ + struct rcar_du_cmm_pending_event *p = + (struct rcar_du_cmm_pending_event *)lut_handle; + + kfree(p->lut_buf); + kfree(p); +} + +int rcar_du_cmm_lut_valid(unsigned int lut_length) +{ + return (lut_length == CMM_LUT_NUM) ? 0 : -EINVAL; +} + +void rcar_du_cmm_update_lut_and_free(void *lut_handle, + struct drm_color_lut *lut, + unsigned int lut_length) +{ + struct rcar_du_cmm_pending_event *p = + (struct rcar_du_cmm_pending_event *)lut_handle; + unsigned int color; + + if (!p) + return; + + if (rcar_du_cmm_lut_valid(lut_length)) + return; + + /* Convert drm_color_lut to the format handled by hardware */ + for (color = 0; color < lut_length; color++) { + p->lut_buf[color] = 0; + p->lut_buf[color] |= drm_color_lut_extract(lut[color].red, 8) + << 16; + p->lut_buf[color] |= drm_color_lut_extract(lut[color].green, 8) + << 8; + p->lut_buf[color] |= drm_color_lut_extract(lut[color].blue, 8); + } + rcar_du_cmm_queue_lut_update(p); +} + +void *rcar_du_cmm_alloc_clu(void *cmm_handle) +{ + struct rcar_du_cmm_pending_event *p; + + if (!cmm_handle) + return NULL; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return NULL; + + p->gem_obj = NULL; + p->event = CMM_EVENT_CLU_DONE; + p->stat = QUE_STAT_PENDING; + p->callback_data = 0; + p->du_cmm = cmm_handle; + p->fpriv = NULL; + p->clu_buf = kmalloc(CMM_CLU_NUM * 4, GFP_KERNEL); + if (!p->clu_buf) { + kfree(p); + return NULL; + } + + return p; +} + +void rcar_du_cmm_free_clu(void *clu_handle) +{ + struct rcar_du_cmm_pending_event *p = + (struct rcar_du_cmm_pending_event *)clu_handle; + + kfree(p->clu_buf); + kfree(p); +} + +void rcar_du_cmm_update_clu_and_free(void *clu_handle, + struct drm_color_ctm *ctm) +{ + struct rcar_du_cmm_pending_event *p = + (struct rcar_du_cmm_pending_event *)clu_handle; + unsigned int r_loop; + unsigned int g_loop; + unsigned int b_loop; + unsigned int step_size; + unsigned int step_fraction; + unsigned int clu_index = 0; + + if (!p) + return; + + step_size = U8_MAX / (CMM_CLU_SAMPLES - 1); + step_fraction = U8_MAX % (CMM_CLU_SAMPLES - 1); + + /*Update clu table*/ + for (b_loop = 0; b_loop < CMM_CLU_SAMPLES; b_loop++) { + unsigned int b; + + b = (b_loop * step_size) + + DIV_ROUND_CLOSEST((b_loop * step_fraction), + (CMM_CLU_SAMPLES - 1)); + + for (g_loop = 0; g_loop < CMM_CLU_SAMPLES; g_loop++) { + unsigned int g; + + g = (g_loop * step_size) + + DIV_ROUND_CLOSEST((g_loop * step_fraction), + (CMM_CLU_SAMPLES - 1)); + + for (r_loop = 0; r_loop < CMM_CLU_SAMPLES; r_loop++) { + unsigned int r; + unsigned int r_val; + unsigned int g_val; + unsigned int b_val; + + r = (r_loop * step_size) + + DIV_ROUND_CLOSEST((r_loop * step_fraction), + (CMM_CLU_SAMPLES - 1)); + + p->clu_buf[clu_index] = 0; + + r_val = rcar_du_cmm_scalar_product + (r, g, b, + ctm->matrix[0], ctm->matrix[1], + ctm->matrix[2]); + + g_val = rcar_du_cmm_scalar_product + (r, g, b, + ctm->matrix[3], ctm->matrix[4], + ctm->matrix[5]); + + b_val = rcar_du_cmm_scalar_product + (r, g, b, + ctm->matrix[6], ctm->matrix[7], + ctm->matrix[8]); + + p->clu_buf[clu_index++] = (r_val << 16) | + (g_val << 8) | b_val; + } + } + } + + rcar_du_cmm_queue_clu_update(p); +} + +static void du_cmm_clk(struct rcar_du_cmm *du_cmm, bool on) +{ + if (on) + clk_prepare_enable(du_cmm->clock); + else + clk_disable_unprepare(du_cmm->clock); +} + int rcar_du_cmm_start_stop(struct rcar_du_crtc *rcrtc, bool on) { struct rcar_du_cmm *du_cmm = rcrtc->cmm_handle; @@ -424,8 +635,16 @@ static inline void _event_done_locked(struct rcar_du_cmm_pending_event *p) list_add_tail(&p->link, cmm_done_list(p->du_cmm, p->fpriv)); wake_up_interruptible(&p->fpriv->event_wait); } else { - /* link deleted by rcar_du_cmm_postclose */ - kfree(p); + /* link deleted by rcar_du_cmm_postclose + * OR it could also be due to set of ctm and gamma + * properties through drm APIs. + */ + if (p->event == CMM_EVENT_LUT_DONE) + rcar_du_cmm_free_lut(p); + else if (p->event == CMM_EVENT_CLU_DONE) + rcar_du_cmm_free_clu(p); + else + kfree(p); } } @@ -479,7 +698,8 @@ event_pop_locked(struct cmm_module_t *module) p->stat = QUE_STAT_ACTIVE; list_del(&p->link); /* delete from du_cmm->[lut|clu|hgo].list */ - list_add_tail(&p->link, &p->fpriv->active_list); + if (p->fpriv) + list_add_tail(&p->link, &p->fpriv->active_list); cmm_vblank_put(p); return p; @@ -605,7 +825,11 @@ static int lut_set(struct rcar_du_cmm *du_cmm, return -EINVAL; } - lut_buf = gem_to_vaddr(stat->p->gem_obj); + if (stat->p->gem_obj) + lut_buf = gem_to_vaddr(stat->p->gem_obj); + else + lut_buf = stat->p->lut_buf; + for (i = 0; i < CMM_LUT_NUM; i++) rcar_du_cmm_write(du_cmm, lut_base + i * 4, lut_buf[i]); @@ -723,7 +947,11 @@ static int clu_set(struct rcar_du_cmm *du_cmm, return -EINVAL; } - clu_buf = gem_to_vaddr(stat->p->gem_obj); + if (stat->p->gem_obj) + clu_buf = gem_to_vaddr(stat->p->gem_obj); + else + clu_buf = stat->p->clu_buf; + rcar_du_cmm_write(du_cmm, addr_reg, 0); for (i = 0; i < CMM_CLU_NUM; i++) rcar_du_cmm_write(du_cmm, data_reg, clu_buf[i]); @@ -1222,6 +1450,8 @@ int rcar_du_cmm_init(struct rcar_du_crtc *rcrtc) rcrtc->cmm_handle = du_cmm; + drm_crtc_enable_color_mgmt(&rcrtc->crtc, 0, true, CMM_LUT_NUM); + dev_info(rcdu->dev, "DU%d use CMM(%s buffer)\n", rcrtc->index, du_cmm->dbuf ? "Double" : "Single"); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h index 74e0a22..5b85de4 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h @@ -115,6 +115,17 @@ void rcar_du_cmm_postclose(struct drm_device *dev, struct drm_file *file_priv); int rcar_du_cmm_start_stop(struct rcar_du_crtc *rcrtc, bool on); void rcar_du_cmm_kick(struct rcar_du_crtc *rcrtc); +void *rcar_du_cmm_alloc_lut(void *cmm_handle); +void rcar_du_cmm_free_lut(void *lut_handle); +int rcar_du_cmm_lut_valid(unsigned int lut_length); +void rcar_du_cmm_update_lut_and_free(void *lut_handle, + struct drm_color_lut *lut, + unsigned int lut_length); + +void *rcar_du_cmm_alloc_clu(void *cmm_handle); +void rcar_du_cmm_free_clu(void *clu_handle); +void rcar_du_cmm_update_clu_and_free(void *clu_handle, + struct drm_color_ctm *ctm); #ifdef CONFIG_PM_SLEEP int rcar_du_cmm_pm_suspend(struct rcar_du_crtc *rcrtc); int rcar_du_cmm_pm_resume(struct rcar_du_crtc *rcrtc); From patchwork Wed Apr 3 13:14:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81FF91708 for ; Wed, 3 Apr 2019 13:27:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70F9F286E3 for ; Wed, 3 Apr 2019 13:27:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 655B8286FF; Wed, 3 Apr 2019 13:27:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3A0E286E3 for ; Wed, 3 Apr 2019 13:27:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726168AbfDCNZl (ORCPT ); Wed, 3 Apr 2019 09:25:41 -0400 Received: from de-deferred2.bosch-org.com ([139.15.180.217]:46288 "EHLO de-deferred2.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726099AbfDCNZl (ORCPT ); Wed, 3 Apr 2019 09:25:41 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by fe0vms0193.rbdmz01.com (Postfix) with ESMTPS id 44Z65q10h0z2Zt; Wed, 3 Apr 2019 15:15:59 +0200 (CEST) Received: from si0vm1947.rbesz01.com (unknown [139.15.230.188]) by fe0vms0187.rbdmz01.com (Postfix) with ESMTPS id 44Z65n3R47z1XLDQt; Wed, 3 Apr 2019 15:15:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297357; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=KsSr5mfZkWC84xy343neKHvYjnHU2ZDc0SrPG3doa1ZabNcvuZ6zwN+afLtGaTfO0 HUCBcfrjmBLT+dMMaxG/+5u37sztMO4g5rJL0x0gT2H/UHLVwTol6W3apedsquw822 ZH05RnQPtngcH3/QeSgbm/Z/LsbpT3kjj2FElSwk= Received: from fe0vm7918.rbesz01.com (unknown [10.58.172.176]) by si0vm1947.rbesz01.com (Postfix) with ESMTPS id 44Z65n2q3fz6CjQSN; Wed, 3 Apr 2019 15:15:57 +0200 (CEST) X-AuditID: 0a3aad10-03fff70000007f88-86-5ca4b20d2a59 Received: from fe0vm1652.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by fe0vm7918.rbesz01.com (SMG Outbound) with SMTP id C1.BF.32648.D02B4AC5; Wed, 3 Apr 2019 15:15:57 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by fe0vm1652.rbesz01.com (Postfix) with ESMTPS id 44Z65n0R74zVv1; Wed, 3 Apr 2019 15:15:57 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:55 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Harsha M M Subject: [PATCH 6/8] drm: rcar-du: Implement atomic_check to check for gamma and ctm properties Date: Wed, 3 Apr 2019 18:44:42 +0530 Message-ID: <1554297284-14009-7-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA22Sb0xTVxjGObf/bjuOOVwovBZqzA2OZBEHDMfdnyzbPqhZtmkyXRbThd3C hXZSSnpbIsyYus2RYakuZkYqaYGx+ScYoHNCcYHQKU7sCKIfwCywISaFMdQBCS4Bd68F2w/7 9ub5ned9znlyaAXToTHQ1kqn4KjkK1i1Tql79aIxFwfbTHm9D3Vc4Oqwiruz9EDNPfJMqLjb vU1q7qeZeepN1a7JY9epXQvBTXuo/brXS4UKa7XgePGNT3SWxSYvqvom82BPw4rKjfrT65GW BlIIRwO/oHqkoxlymoL2kRWFDBjyM4I+z6cxMIcgWOdXykBNcqG/q0sjgzRyHsGx+W5KBgpy CBpOtmnkOZUUQ4unRS3PSpINkbN3pK00jck+GDtSGEveBOPDXz8N05IPIfDrtDoWvA8Cy/+o 5BmTFLjROK2MrQcYiEafrgGyGUIt6hOI+BJO+RJONSPqAtKXCXnVtqJX8rltDrMg1ublbyux 24Io1ibpQaGhsjAiNGKT8URjm4lR8dVijS2MttMUq8cvH5akDWZ7aY2FFy3FDleFILIGnDXy jolJfSaLLrPNKopWe2UYAa1g03DkeLOJwaV8Ta3gsMdsYZRJK9kMXE7vNjGknHcKBwShSnCs 09domgWc1iUFpjiEcuFgmbXCuY5ZI0ZJSUlMeiJJjKVobRi9RCdL2aEOaQUWq3ibaC1fs2+M 2Zl1NW4dQkWGDPxcp+QhMrW4Kp+lGrJw0n2/idEngLhzFo0jqbdUvCIHJksfNZ4HOFOuKGVN jJsKvpc85LwWZurcCBY8Ywj8PUsIlqe+pGB1epYC/93PlTDa69PAwsUlDXhb/TRMjl/WwsNz DRguzV7H0H92joHTS0/SoO+rBj0Ehx5nwfyNR0bw915j4Zb3NgvRPk829Ize3ALewboc6Dh5 LgciPw7mQHRxPgd+H/FvhcblK1sh9GQ0FyYenMmDK981F8DqqfZC6Qa+olmpTEoqk3MF5DKd vPN/ylxT468zuNF2pTFzgGwuee/jel/y4cvRqx+8u3Pli8BMRmtZcMO/5v3dd4883/hXraeE DhVX7XyMplbv2Rdr9kx1csY/WgcK718am9vtm/7MPKz3uE/s/XsyZUdJtDb6NlX354DG2546 Gck+dO/9Ld0fcQU/HP3t2qmbM+4db7k6jx/41tp0azCSvpFVihY+/wWFQ+T/A3Fq90ZCBAAA Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh Implement atomic helper check and allocate memory necessary for lut and clu tables Signed-off-by: Harsha M M - Resolved checkpatch errors - Resolved merge conflicts according to latest version Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 58 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 3 +- 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 864fb94..a00b7a7 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -622,6 +622,63 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) * CRTC Functions */ +static bool rcar_du_crtc_is_ctm_updated(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + return (state->color_mgmt_changed && state->ctm && + crtc->state->ctm && + (crtc->state->ctm->base.id != state->ctm->base.id)); +} + +static bool rcar_du_crtc_is_gamma_updated(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + return (state->color_mgmt_changed && state->gamma_lut && + crtc->state->gamma_lut && + (crtc->state->gamma_lut->base.id != state->gamma_lut->base.id)); +} + +static int rcar_du_crtc_cmm_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + int ret = 0; + struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); + + /*Check gamma update and allocate memory*/ + if (rcar_du_crtc_is_gamma_updated(crtc, state) && + !rcrtc->lut_handle) { + ret = rcar_du_cmm_lut_valid((crtc->state->gamma_lut->length / + sizeof(struct drm_color_lut))); + if (ret >= 0) { + rcrtc->lut_handle = + rcar_du_cmm_alloc_lut(rcrtc->cmm_handle); + if (!rcrtc->lut_handle) + ret = -ENOMEM; + } + } + + /*Check update of ctm and allocate memory*/ + if (ret >= 0 && rcar_du_crtc_is_ctm_updated(crtc, state) && + !rcrtc->clu_handle) { + rcrtc->clu_handle = rcar_du_cmm_alloc_clu(rcrtc->cmm_handle); + if (!rcrtc->clu_handle) { + if (!rcrtc->lut_handle) { + rcar_du_cmm_free_lut(rcrtc->lut_handle); + rcrtc->lut_handle = NULL; + } + ret = -ENOMEM; + } + } + + return ret; +} + +static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + return rcar_du_crtc_cmm_atomic_check(crtc, state); +} + static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -708,6 +765,7 @@ static const struct drm_crtc_helper_funcs crtc_helper_funcs = { .atomic_flush = rcar_du_crtc_atomic_flush, .atomic_enable = rcar_du_crtc_atomic_enable, .atomic_disable = rcar_du_crtc_atomic_disable, + .atomic_check = rcar_du_crtc_atomic_check, }; static struct drm_crtc_state * diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h index 5b85de4..b79080e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h @@ -70,7 +70,8 @@ struct rcar_du_crtc { int lvds_ch; void *cmm_handle; - + void *lut_handle; + void *clu_handle; }; #define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc) From patchwork Wed Apr 3 13:14:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883799 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B726F139A for ; Wed, 3 Apr 2019 13:27:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7447286E3 for ; Wed, 3 Apr 2019 13:27:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9B7F028714; Wed, 3 Apr 2019 13:27:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA309286FF for ; Wed, 3 Apr 2019 13:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726404AbfDCNZn (ORCPT ); Wed, 3 Apr 2019 09:25:43 -0400 Received: from de-deferred2.bosch-org.com ([139.15.180.217]:46410 "EHLO de-deferred2.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726155AbfDCNZm (ORCPT ); Wed, 3 Apr 2019 09:25:42 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by fe0vms0193.rbdmz01.com (Postfix) with ESMTPS id 44Z65r5cNcz2fv; Wed, 3 Apr 2019 15:16:00 +0200 (CEST) Received: from si0vm1947.rbesz01.com (unknown [139.15.230.188]) by fe0vms0186.rbdmz01.com (Postfix) with ESMTPS id 44Z65q0xPHz1XLFjd; Wed, 3 Apr 2019 15:15:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297359; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=jzX7NuqJMBk8PMsDXzF7/KfgdultFLhbko0eRKJqDweUF61wQyyj+2lGOiIRY6AO0 HTuswTWVRbqZw150FPIJvjr/54SHZ6o0j01jo9FCLjFztHk0bmM1SB4gQiE8OzX5B5 7DeiIbXPqD4xvhWyvbSt3hO/4vwby+dQl0JrZWE8= Received: from fe0vm7918.rbesz01.com (unknown [10.58.172.176]) by si0vm1947.rbesz01.com (Postfix) with ESMTPS id 44Z65q0nCDz6CjQSh; Wed, 3 Apr 2019 15:15:59 +0200 (CEST) X-AuditID: 0a3aad10-03fff70000007f88-9a-5ca4b20ecfd8 Received: from si0vm1950.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by fe0vm7918.rbesz01.com (SMG Outbound) with SMTP id 64.BF.32648.E02B4AC5; Wed, 3 Apr 2019 15:15:58 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by si0vm1950.rbesz01.com (Postfix) with ESMTPS id 44Z65p5P4Fz525; Wed, 3 Apr 2019 15:15:58 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:57 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Harsha M M Subject: [PATCH 7/8] drm: rcar-du: update gamma and ctm properties in commit tail Date: Wed, 3 Apr 2019 18:44:43 +0530 Message-ID: <1554297284-14009-8-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA21SbUxbVRjuuf3gtuvF01vKXltgesecokNgbruKMfsxE6KJ0+g0MY3zIhfa QCm5t5CxGCTMrPJVUdwHZGlZZFNJVOiyrXxskzoYK2STQQzVZUzZHCOIDFwyIqD3Ulj7wz8n 532e93menCeHVNLtcWbSXuzihWKuiNHoVLoXvk3eEu9vtWYExraxvotX1Ozo/b807L26G2p2 pOuYhj19d4bYqc4Zr71E5Mz7U14n3tW9mMcX2ct44dmX3tfZ7ixNo5I/kvf98t2QqhJdghqk JQE/B3/3jqIapCNpfJSAmuMeIjL0IPjsUE9cZJhG4L65oJElGrwFLnR0rBAJ+BsEtTNnCZlQ 4g+hvrFVIkjSiN+A6sAuGVbhVLg60a+U7xTeA1UnG1WR6BQIX6lewbX4bfAN3Frxp6Ud34M5 dWTfAJebbqki9gC9k5NK2R7wY9B5XNOAcHPMVnPMVgsi2pApn88oc+x4PpNNF3J5cX9GZvoH TocfRerEAdQZyg8iTCJGT91oarXSaq5MLHcE0TaSYEzU9goJis915pXbONG2Vygt4kXGTCX9 9IqVNj6ExdJch10U7c7iIAJSySRQQ5+2WGkqjyvfzwvOiCyILKSKWU8VkLutNC7gXHwhz5fw whqbTZIMUAkdUqBB4Av4ffn2ItcazSRTSKFQ0ImxTGwsQWqDaCupl7I7v5csKLGEc4j2glX5 oxE5vYZGpSG0w7yeWtcuabDM2kqLH6aakyjFba+VNsUQUeUUCiOpNyO1JAfqpZ8azQPKIldk WAWjoqwTkgYfWAd33ZUI5vtOIRirm0LgDdxHcLH7sBoeTE7GwXj4jBYG2kJauD7cpofRO716 mP26noKFc8OPgKffjWHuZtAIg2dCRjh/sN4E3pkuE5zyngVoXJq1gD+0kARe74kUWByf2wBj 15elY/nHx8Hb1cfAsGeEAc/nExvB39SQCkf7+zZB4NrgJhi45nlCtt88JZVJSGWypT65TBfn +p8yV9Ho68yVyPHOxPmhf04fOXwPFrO+2EU9mRVXe8z5Z0XOfMbHtt+5GbZyg+GZ+decn2T/ JhguHNmcuGyp2pNmie85qPhy8Slwn/v35fea09KTfwg34L6tO9lXR9zd7W8eSE0MWzxXt/9a 99ZXuwfrK+xV4Y2zppbLYUt158nC2x9Nl/uyme6fC/c+zahEG5eZphRE7j/+11aAQwQAAA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh Update gamma and ctm properties if there is a change. Signed-off-by: Harsha M M - Fix compilation issues when for_each_crtc_in_state is not defined - Resolved checkpatch errors - Resolved merge conflicts according to latest version Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/rcar-du/rcar_du_kms.c | 25 +++++++++++++++++++++++++ include/drm/drm_atomic.h | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index f0bc7cc..4d9a19c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -246,6 +246,10 @@ static int rcar_du_atomic_check(struct drm_device *dev, static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *dev = old_state->dev; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + struct rcar_du_crtc *rcrtc; + int i; /* Apply the atomic update. */ drm_atomic_helper_commit_modeset_disables(dev, old_state); @@ -253,6 +257,27 @@ static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state) DRM_PLANE_COMMIT_ACTIVE_ONLY); drm_atomic_helper_commit_modeset_enables(dev, old_state); + /* Update gamma and ctm properties for all crtc in present + * state. Update is done only if there is a change + */ + for_each_crtc_in_state(old_state, crtc, crtc_state, i) { + rcrtc = to_rcar_crtc(crtc); + + if (rcrtc->lut_handle) { + rcar_du_cmm_update_lut_and_free + (rcrtc->lut_handle, + (struct drm_color_lut *)crtc->state->gamma_lut->data, + (crtc->state->gamma_lut->length / + sizeof(struct drm_color_lut))); + rcrtc->lut_handle = NULL; + } + if (rcrtc->clu_handle) { + rcar_du_cmm_update_clu_and_free + (rcrtc->clu_handle, + (struct drm_color_ctm *)crtc->state->ctm->data); + rcrtc->clu_handle = NULL; + } + } drm_atomic_helper_commit_hw_done(old_state); drm_atomic_helper_wait_for_flip_done(dev, old_state); diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 1e71315..d22ccd8 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -693,6 +693,31 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); (new_connector_state) = (__state)->connectors[__i].new_state, 1)) /** + * for_each_crtc_in_state - iterate over all connectors in an atomic update + * @__state: &struct drm_atomic_state pointer + * @crtc: &struct drm_crtc iteration cursor + * @crtc_state: &struct drm_crtc_state iteration cursor + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all CRTCs in an atomic update. Note that before the + * software state is committed (by calling drm_atomic_helper_swap_state(), this + * points to the new state, while afterwards it points to the old state. Due to + * this tricky confusion this macro is deprecated. + * + * FIXME: + * + * Replace all usage of this with one of the explicit iterators below and then + * remove this macro. + */ +#define for_each_crtc_in_state(__state, crtc, crtc_state, __i) \ + for ((__i) = 0; \ + ((__i) < ((__state)->dev->mode_config.num_crtc)) && \ + ((crtc) = ((__state)->crtcs[__i].ptr), \ + (crtc_state) = ((__state)->crtcs[__i].state), 1); \ + (__i)++) \ + for_each_if(crtc_state) + +/** * for_each_oldnew_crtc_in_state - iterate over all CRTCs in an atomic update * @__state: &struct drm_atomic_state pointer * @crtc: &struct drm_crtc iteration cursor From patchwork Wed Apr 3 13:14:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalakodima Venkata Rajesh (RBEI/ECF3)" X-Patchwork-Id: 10883801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BDDA81708 for ; Wed, 3 Apr 2019 13:27:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A748D286E3 for ; Wed, 3 Apr 2019 13:27:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A578286FF; Wed, 3 Apr 2019 13:27:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D1E7286EE for ; Wed, 3 Apr 2019 13:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726099AbfDCN1O (ORCPT ); Wed, 3 Apr 2019 09:27:14 -0400 Received: from de-deferred2.bosch-org.com ([139.15.180.217]:46272 "EHLO de-deferred2.bosch-org.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726064AbfDCNZn (ORCPT ); Wed, 3 Apr 2019 09:25:43 -0400 Received: from de-out1.bosch-org.com (unknown [139.15.180.215]) by fe0vms0193.rbdmz01.com (Postfix) with ESMTPS id 44Z65v1f8dz2gZ; Wed, 3 Apr 2019 15:16:03 +0200 (CEST) Received: from si0vm1947.rbesz01.com (unknown [139.15.230.188]) by fe0vms0186.rbdmz01.com (Postfix) with ESMTPS id 44Z65s43Qlz1XLFjh; Wed, 3 Apr 2019 15:16:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=in.bosch.com; s=2015-01-21; t=1554297361; bh=5JmXTCA8402bhLcSZ4Bm03a+Df0e1eFcN7hmyjl8vSI=; l=10; h=From:From:Reply-To:Sender; b=cDXEzRiXZWXt4NEpGOX9n0UvvQ8r4Tcqe4wfAYX8cOsTzz7I4iGZGna4NBoAmobZf aR4in5ZaqUBYPNJRXa+wHcQrZPiKUCPJfuIqoTBCbzioLW9p4qyII9QiEmHN3rt0n5 TQPflzTQcg6yWVg5P3pDR5jPnfGT/ZwyRGBR1UPY= Received: from fe0vm7918.rbesz01.com (unknown [10.58.172.176]) by si0vm1947.rbesz01.com (Postfix) with ESMTPS id 44Z65s3XX0z6CjQSh; Wed, 3 Apr 2019 15:16:01 +0200 (CEST) X-AuditID: 0a3aad10-03fff70000007f88-c0-5ca4b210ba23 Received: from fe0vm1651.rbesz01.com ( [10.58.173.29]) (using TLS with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by fe0vm7918.rbesz01.com (SMG Outbound) with SMTP id 19.BF.32648.012B4AC5; Wed, 3 Apr 2019 15:16:00 +0200 (CEST) Received: from SI-HUB2000.de.bosch.com (si-hub2000.de.bosch.com [10.4.103.108]) by fe0vm1651.rbesz01.com (Postfix) with ESMTPS id 44Z65r5c14zR6h; Wed, 3 Apr 2019 15:16:00 +0200 (CEST) Received: from localhost.localdomain (10.47.103.88) by SI-HUB2000.de.bosch.com (10.4.103.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5; Wed, 3 Apr 2019 15:15:58 +0200 From: To: , , , , CC: kalakodima venkata rajesh , Koji Matsuoka , Steve Longerbeam , Balasubramani Vivekanandan Subject: [PATCH 8/8] drm: rcar-du: Add shutdown callback function in platform_driver Date: Wed, 3 Apr 2019 18:44:44 +0530 Message-ID: <1554297284-14009-9-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> References: <1554297284-14009-1-git-send-email-VenkataRajesh.Kalakodima@in.bosch.com> MIME-Version: 1.0 X-Originating-IP: [10.47.103.88] X-Brightmail-Tracker: H4sIAAAAAAAAA21Sf0wbZRjud9derx1nr1dgr223mMb4B8kmqHOnEreQmHRG4zLHNKSZFjja xv7AXsvGEifBLZMf0m0KCtvoVsHJJhktbtChQ5sllAUJbGSGGYFtaGi30QnDweLUOwtr//Cf y/c97/Pj/Z4ciTNX5VrS5vRwbqfZbiCUUuWLnWvWqUNtptxwDLGNRwYQ6784LGPHFhIEu3i0 H2P/qJ+QsVfOHyXYs7FZjD3ZGcA3k8bJugHM2LdQjYx/Dh2SGudDa7dKi5T5pZzdVsG5n375 XaU1MXSYKO/etDsa/rAKndhQixQk0M/BV4NHiFqkJBn6CwxuLfrw5OU7BPM3euUii6FvC5e7 evFM0OugPxiUi6RMugNB3WwPJg5w+g6C+HVdLSJJDb0dDoaLRFhKPwmNiTP/+VB0IVz+aRxL Jq+F8eEaXDwr6B3gj04TyaxC8C/OyZJ8NQw2T0uT9gA/zszgoj3QT0D4BHEQ0S1prJY01nGE nUJZZVxuhWPjC3nsencxx+/JzVtf4nKEULJluheFL5VFEE0iQwY10dxmYmTmCr7SEUEbSMyQ RT2/V4AeK3aVVlrNvPUdt9fO8QYtpR951cRoHsG8t9hh43mbyxlBQOKGTGrId9zEUKXmyj2c 25WURZCOlBpWUxbyDRNDW8we7j2OK+fcK9OXSNIAVGZQCFS7OQu3u8xm96yMDWsoJJFImOz0 SXosRioi6FkyQ8gOnxEsKL7c7OBtlmX540k5s4KmpJfQFrIh+PsxnOy+LnwZqdPl5LSrqVVd ggst8q1e56M9tHpK8luriclKG6S84ugqEprUUA/FFTKEXzq1AVA6sTT1MpgSPRMQNPRf2TCR 0EH02mvQ12qC2IEqBK29Cwii82EcGgKzUrh3rFEGF5oSMlhsuknAD/duERDoXiLg8vkWOcx3 LsgF7DQJk+PnFDB2JaKA0Y8TCojVdCvhcN2UEu5+/QkFn/5SpYK+fSEVjMf7VLD0/agKvhm7 oYL+9hY1NMycZODQSFQDbQ/uZEPHtwNaWPL7dHGhW0zolvX6xW49Zs//dLuMpp6mrULtu/zB 9z8vqb6ZNafcvyr0wcMaryd/OOOC0fJlbdAzSk7JewpuP6Wpe/ufkoIuf/62qZGeV3wXmYm5 2Eebx/IKTr1lP7dJf99Zv9H368436z/L2b+3K6g3xaerD/zdvD3SuWtf+4OBjsEcV9fpudeb t2y7X3it6OfhnQFJeHIm5+yOgiaDlLea83JwN2/+F4/5t6FpBAAA Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: kalakodima venkata rajesh When rebooting, the Display driver is accessing H/W (reading DDR). Therefore, there is a problem of hanging when setting DDR to self refresh mode. This patch implement the shutdown function and solve this problem by stopping H/W access. In addtion, on the ulcb board, since initial values of versaclock are used as they are, signals are not output when initializing to 0 with shutdown, so this patch excludes processing to initialize versaclock to 0. drm: rcar-du: Add HDMI control clock when S2RAM Signed-off-by: Koji Matsuoka (cherry picked from horms/renesas-bsp commit 3cfda6331c4069800dd4434427284aba8e6f1ed6) [slongerbeam: keep integer i in rcar_du_pm_shutdown(), needed because of 050e54d87f ("drm: rcar-du: drm: rcar-du: Add DU CMM support")] Signed-off-by: Steve Longerbeam drm: rcar-du: cmm: lut and clu backup not required during shutdown rcar_du_cmm_pm_suspend function copies LUT and CLU hardare register values to memory. In the patch which adds DU CMM support (https://github.com/renesas-rcar/du_cmm/commit/ 9a65d02119e4ae405a89a850463a6a0d0f2c1ecb), the intention of the author was to backup the registers during suspend and restore it on resume. But rcar_du_cmm_pm_suspend was also called on system shutdown. Though it does not cause any harm, it is not required during shutdown as it does not make sense to backup. This patch ensures that rcar_du_cmm_pm_suspend is called only during suspend Fixes: https://github.com/renesas-rcar/du_cmm/commit/9a65d02119e4ae405a89a850463a6a0d0f2c1ecb Signed-off-by: Balasubramani Vivekanandan - Resolved checkpatch errors - Resolved merge conflicts according to latest version Signed-off-by: kalakodima venkata rajesh --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 35 ++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 54 +++++++++++++++++++++++++------ drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 2 +- drivers/gpu/drm/rcar-du/rcar_du_encoder.h | 1 + include/drm/bridge/dw_hdmi.h | 1 + 5 files changed, 83 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 5971976..aa257d7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2033,6 +2033,41 @@ static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) mutex_unlock(&hdmi->mutex); } +/* + * This function controls clocks of dw_hdmi through drm_bridge + * at system suspend/resume. + * Arguments: + * bridge: drm_bridge that contains dw_hdmi. + * flag: controlled flag. + * false: is used when suspend. + * true: is used when resume. + */ +void dw_hdmi_s2r_ctrl(struct drm_bridge *bridge, int flag) +{ + struct dw_hdmi *hdmi = bridge->driver_private; + + if (!hdmi) + return; + + if (flag) { /* enable clk */ + if (hdmi->isfr_clk) + clk_prepare_enable(hdmi->isfr_clk); + if (hdmi->iahb_clk) + clk_prepare_enable(hdmi->iahb_clk); + + initialize_hdmi_ih_mutes(hdmi); + dw_hdmi_setup_i2c(hdmi); + dw_hdmi_i2c_init(hdmi); + dw_hdmi_phy_setup_hpd(hdmi, NULL); + } else { /* disable clk */ + if (hdmi->isfr_clk) + clk_disable_unprepare(hdmi->isfr_clk); + if (hdmi->iahb_clk) + clk_disable_unprepare(hdmi->iahb_clk); + } +} +EXPORT_SYMBOL_GPL(dw_hdmi_s2r_ctrl); + static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { .attach = dw_hdmi_bridge_attach, .enable = dw_hdmi_bridge_enable, diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 838b7c9..9eb63b0 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -368,18 +369,14 @@ static struct drm_driver rcar_du_driver = { */ #ifdef CONFIG_PM_SLEEP -static int rcar_du_pm_suspend(struct device *dev) +static int rcar_du_pm_shutdown(struct device *dev) { struct rcar_du_device *rcdu = dev_get_drvdata(dev); struct drm_atomic_state *state; - int i; - - if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) { - for (i = 0; i < rcdu->num_crtcs; ++i) - rcar_du_cmm_pm_suspend(&rcdu->crtcs[i]); - } - - drm_kms_helper_poll_disable(rcdu->ddev); +#if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI) + struct drm_encoder *encoder; +#endif + drm_kms_helper_poll_disable(rcdu->ddev); drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true); state = drm_atomic_helper_suspend(rcdu->ddev); @@ -389,11 +386,43 @@ static int rcar_du_pm_suspend(struct device *dev) return PTR_ERR(state); } +#if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI) + list_for_each_entry(encoder, + &rcdu->ddev->mode_config.encoder_list, + head) { + struct rcar_du_encoder *renc = to_rcar_encoder(encoder); + + if (renc->bridge && (renc->output == RCAR_DU_OUTPUT_HDMI0 || + renc->output == RCAR_DU_OUTPUT_HDMI1)) + dw_hdmi_s2r_ctrl(encoder->bridge, false); + } +#endif rcdu->suspend_state = state; return 0; } +static int rcar_du_pm_suspend(struct device *dev) +{ + struct rcar_du_device *rcdu = dev_get_drvdata(dev); + + int i, ret; + + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM)) { + for (i = 0; i < rcdu->num_crtcs; ++i) + rcar_du_cmm_pm_suspend(&rcdu->crtcs[i]); + } + + ret = rcar_du_pm_shutdown(dev); + + if (ret) + return ret; + + for (i = 0; i < rcdu->num_crtcs; ++i) + clk_set_rate(rcdu->crtcs[i].extclock, 0); + return 0; +} + static int rcar_du_pm_resume(struct device *dev) { struct rcar_du_device *rcdu = dev_get_drvdata(dev); @@ -504,6 +533,12 @@ static int rcar_du_probe(struct platform_device *pdev) return ret; } +static void rcar_du_shutdown(struct platform_device *pdev) +{ +#ifdef CONFIG_PM_SLEEP + rcar_du_pm_shutdown(&pdev->dev); +#endif +} static struct platform_driver rcar_du_platform_driver = { .probe = rcar_du_probe, .remove = rcar_du_remove, @@ -512,6 +547,7 @@ static struct platform_driver rcar_du_platform_driver = { .pm = &rcar_du_pm_ops, .of_match_table = rcar_du_of_table, }, + .shutdown = rcar_du_shutdown, }; static int __init rcar_du_init(void) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c index f9c933d..98df8a2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c @@ -62,7 +62,7 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu, dev_dbg(rcdu->dev, "initializing encoder %pOF for output %u\n", enc_node, output); - + renc->bridge = bridge; /* Locate the DRM bridge from the encoder DT node. */ bridge = of_drm_find_bridge(enc_node); if (!bridge) { diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h index 2d2abca..cc5bfcb 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h @@ -23,6 +23,7 @@ struct rcar_du_device; struct rcar_du_encoder { struct drm_encoder base; enum rcar_du_output output; + struct drm_bridge *bridge; }; #define to_rcar_encoder(e) \ diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index ccb5aa8..36383cf4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -171,5 +171,6 @@ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense); void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); +void dw_hdmi_s2r_ctrl(struct drm_bridge *bridge, int flag); #endif /* __IMX_HDMI_H__ */