From patchwork Wed Apr 3 15:28:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Li X-Patchwork-Id: 10884013 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4805117E9 for ; Wed, 3 Apr 2019 15:23:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B1FE289D1 for ; Wed, 3 Apr 2019 15:23:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F6B2289F9; Wed, 3 Apr 2019 15:23:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 76F2B289F4 for ; Wed, 3 Apr 2019 15:23:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=PtwJLyjgNtgkX/jJ+pXnZg3P8FNdePJ/5YTojdVKbxs=; b=UkDsSl3Cget8Hz ip4LN15b/bjC4i7F7KAMFjnGxHYKHFseVbwYzrK7T8Dt1VI+KpK9vAXlw7I6v7rH1qR53fttGvk0V hCxqJSJouGs38gfpxPiBLHOWaHHQQX8Dp9a8HOM8OeQolYDmAN956+KkS7u6yDMTN8E4IyIUgk7yh meID+gn7EEN2IQZrTIzP+oX7SkFNhWtMdwGMWBotYKpaO1Jkfz1b4MewjisAqpnTzpJRn8Oxv24mC WRyj9cI1TsxgKU2OHXwC5jmyi2/Pya7A+vgNELGfBFi0JsUZhuoP6nBDpaHcq1dOcPdhIdMQncCNT qOlcfKcTkSJdaQGLeqgA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBhje-0000P0-4k; Wed, 03 Apr 2019 15:23:30 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBhja-0000OH-QM for linux-arm-kernel@lists.infradead.org; Wed, 03 Apr 2019 15:23:28 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [10.3.19.206]) by Forcepoint Email with ESMTP id 12AAE4FDD608E969D7C1; Wed, 3 Apr 2019 23:23:17 +0800 (CST) Received: from euler.huawei.com (10.175.104.193) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.408.0; Wed, 3 Apr 2019 23:23:09 +0800 From: Wei Li To: , , Subject: [RFC PATCH] arm64: irqflags: fix incomplete save & restore Date: Wed, 3 Apr 2019 23:28:54 +0800 Message-ID: <20190403152854.27741-1-liwei391@huawei.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.175.104.193] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190403_082327_031206_B9D8100E X-CRM114-Status: UNSURE ( 9.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, mingo@redhat.com, james.morse@arm.com, huawei.libin@huawei.com, guohanjun@huawei.com, yuzenghui@huawei.com, wanghaibin.wang@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To support the arm64 pseudo nmi, function arch_local_irq_save() and arch_local_irq_restore() now operate ICC_PMR_EL1 insead of daif. But i found the logic of the save and restore may be suspicious: arch_local_irq_save(): daif.i_on pmr_on -> flag.i_on 1 0 | 0 1 1 | 1 0 1 | 0 --[1] 0 0 | 0 arch_local_irq_restore(): daif.i_on pmr_on <- flag.i_on x 0 | 0 x 1 | 1 As we see, the condintion [1] will never be restored honestly. When doing function_graph trace at gic_handle_irq(), calling local_irq_save() and local_irq_restore() in trace_graph_entry() will just go into this condintion. Therefore the irq can never be processed and leading to hang. In this patch, we do the save & restore exactly, and make sure the arch_irqs_disabled_flags() returns correctly. Fix: commit 4a503217ce37 ("arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking") Signed-off-by: Wei Li --- arch/arm64/include/asm/irqflags.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 43d8366c1e87..7bc6a79f31c4 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -76,8 +76,7 @@ static inline unsigned long arch_local_save_flags(void) * The asm is logically equivalent to: * * if (system_uses_irq_prio_masking()) - * flags = (daif_bits & PSR_I_BIT) ? - * GIC_PRIO_IRQOFF : + * flags = (daif_bits << 32) | * read_sysreg_s(SYS_ICC_PMR_EL1); * else * flags = daif_bits; @@ -87,11 +86,11 @@ static inline unsigned long arch_local_save_flags(void) "nop\n" "nop", "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1) "\n" - "ands %1, %1, " __stringify(PSR_I_BIT) "\n" - "csel %0, %0, %2, eq", + "lsl %1, %1, #32\n" + "orr %0, %0, %1", ARM64_HAS_IRQ_PRIO_MASKING) : "=&r" (flags), "+r" (daif_bits) - : "r" ((unsigned long) GIC_PRIO_IRQOFF) + : : "memory"); return flags; @@ -119,8 +118,8 @@ static inline void arch_local_irq_restore(unsigned long flags) "msr_s " __stringify(SYS_ICC_PMR_EL1) ", %0\n" "dsb sy", ARM64_HAS_IRQ_PRIO_MASKING) - : "+r" (flags) : + : "r" ((int)flags) : "memory"); } @@ -130,12 +129,14 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) asm volatile(ALTERNATIVE( "and %w0, %w1, #" __stringify(PSR_I_BIT) "\n" + "nop\n" "nop", + "and %w0, %w2, #" __stringify(PSR_I_BIT) "\n" "cmp %w1, #" __stringify(GIC_PRIO_IRQOFF) "\n" - "cset %w0, ls", + "cinc %w0, %w0, ls", ARM64_HAS_IRQ_PRIO_MASKING) : "=&r" (res) - : "r" ((int) flags) + : "r" ((int) flags), "r" (flags >> 32) : "memory"); return res;