From patchwork Thu Apr 4 21:25:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886347 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25E0E17E1 for ; Thu, 4 Apr 2019 21:25:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 167F928AF6 for ; Thu, 4 Apr 2019 21:25:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0AB1628AFC; Thu, 4 Apr 2019 21:25:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B707C28AF6 for ; Thu, 4 Apr 2019 21:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730687AbfDDVZz (ORCPT ); Thu, 4 Apr 2019 17:25:55 -0400 Received: from mail-eopbgr740047.outbound.protection.outlook.com ([40.107.74.47]:6544 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729400AbfDDVZy (ORCPT ); Thu, 4 Apr 2019 17:25:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZW8gZHZuD3wQMGTOOHdu82wdoI9L6G9fVD3ek1X1pZ4=; b=Ov0B9CzpnlavmoW5muZPj8cYufv0HLiryB3Fy5UuDDAAqRBHV+Rhyoz9bX1pzfWFHB0aa8y1FDOOdATyPtxHzi9RZKhQnKnUDVUXA/nmGoiUjR2S7q0Izp8yCeOcmrheuhcaxh1RN8sTLQR2o9EcsyXJ0gCgFPN+tBkhZsSArPo= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2845.namprd12.prod.outlook.com (52.135.102.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.17; Thu, 4 Apr 2019 21:25:47 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a%4]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 21:25:47 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 1/7] acpi/cppc: Add macro for CPPC register BUFFER only check Thread-Topic: [PATCH v2 1/7] acpi/cppc: Add macro for CPPC register BUFFER only check Thread-Index: AQHU6yz32WKT40X3o02yO8eIfc6cDA== Date: Thu, 4 Apr 2019 21:25:47 +0000 Message-ID: <4eae43aeb96e379bbdd9cd2a040fe53c147bd412.1554410643.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3d439b8f-ee15-4a64-13fa-08d6b9441a19 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2845; x-ms-traffictypediagnostic: SN6PR12MB2845: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(136003)(376002)(396003)(366004)(346002)(199004)(189003)(305945005)(5660300002)(26005)(102836004)(105586002)(66066001)(118296001)(8676002)(106356001)(6116002)(4744005)(3846002)(81156014)(97736004)(68736007)(53936002)(81166006)(316002)(7736002)(2201001)(50226002)(71190400001)(71200400001)(86362001)(6512007)(2501003)(8936002)(99286004)(25786009)(36756003)(256004)(4326008)(6486002)(478600001)(186003)(110136005)(486006)(14454004)(54906003)(446003)(72206003)(11346002)(2906002)(52116002)(2616005)(476003)(6506007)(386003)(76176011)(6436002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2845;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: YuAOjoJfEY+O2iV94tfdqhO3kxr/ldyx1bE+BUTFfN6NJgVKnu6O6ehtK0xLOCV3C9yI/cgNBepbVEsbLcgmEpJlO3awqrv5kFdwqtWimci5rXyxa6p/GCxmDpykwFoJJm46r2Lww92MSy4PDwTD9oAx3ILb9+g/TlUIynY50QLzwnxXWMT+vHmW2FN/v6OF0xgpYxag8KCp/RtuMU1rgcp0LvcfARyERmpRRFbch+8/6MbJqvY/0ABaMxujHKghqJ7uxt6rI8odN5jW6B+KeHYrMpCS/zMLCw1tVjgA6s7kXfxnKTwTnRkV4t/dsdiJsvKtje8VR4j2huf9SrCAKeZcyWpGBXZ3ygIiZwokSKAlvFIg1ry9nKxIla9xmHgQApkrwfCwB5AcC/jPaQQr+cSmQ0IL7SVmmO+3Zg79Ki4= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3d439b8f-ee15-4a64-13fa-08d6b9441a19 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:47.1403 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2845 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CPC_SUP_BUFFER_ONLY ensures that an expected BUFFER only register has a register type of ACPI_TYPE_BUFFER and is not NULL. Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index d4244e7d0e38..56a09e057c4f 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -115,6 +115,14 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ !!(cpc)->cpc_entry.int_value : \ !IS_NULL_REG(&(cpc)->cpc_entry.reg)) + +/* + * Evaluates to True if an optional cpc field is supported and is + * BUFFER only + */ +#define CPC_SUP_BUFFER_ONLY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ + !IS_NULL_REG(&(cpc)->cpc_entry.reg)) + /* * Arbitrary Retries in case the remote processor is slow to respond * to PCC commands. Keeping it high enough to cover emulators where From patchwork Thu Apr 4 21:25:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886349 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7221922 for ; Thu, 4 Apr 2019 21:25:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B396A28AF3 for ; Thu, 4 Apr 2019 21:25:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A792B28AF8; Thu, 4 Apr 2019 21:25:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22F6C28AF3 for ; Thu, 4 Apr 2019 21:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730721AbfDDVZ4 (ORCPT ); Thu, 4 Apr 2019 17:25:56 -0400 Received: from mail-eopbgr740047.outbound.protection.outlook.com ([40.107.74.47]:6544 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730674AbfDDVZ4 (ORCPT ); Thu, 4 Apr 2019 17:25:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ElAlkD+uZhbpdj0DyT5bL5qT98VOJp68BileWw2osEI=; b=XptcP6ebLNgEPvo54ipo3JMJlVsSjz9lyzvarKxoCegUenUNvT9HbLawT1FlGLXzAHaTh7L4htI07o7+ZaWWyOcZVYH2LCURpCFodC4ZXSK8P3pmWKkmt0burUpjNsn61jwUxySrW4QDxGynbY48/DYIYfD3paMlYzfwAvyl43I= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2845.namprd12.prod.outlook.com (52.135.102.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.17; Thu, 4 Apr 2019 21:25:49 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a%4]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 21:25:49 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 2/7] acpi/cppc: Ensure only supported CPPC sysfs entries are created Thread-Topic: [PATCH v2 2/7] acpi/cppc: Ensure only supported CPPC sysfs entries are created Thread-Index: AQHU6yz5Jgs7bPb6v0m5gJ5fN3WRzg== Date: Thu, 4 Apr 2019 21:25:49 +0000 Message-ID: <71114f283852625e3d88cd76ca4f8ac1fd8c25fa.1554410643.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 55d53135-e4a5-41e0-d400-08d6b9441b6c x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2845; x-ms-traffictypediagnostic: SN6PR12MB2845: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(136003)(376002)(396003)(366004)(346002)(199004)(189003)(305945005)(5660300002)(26005)(102836004)(105586002)(66066001)(118296001)(8676002)(106356001)(6116002)(3846002)(81156014)(97736004)(68736007)(53936002)(81166006)(316002)(7736002)(2201001)(50226002)(71190400001)(71200400001)(86362001)(6512007)(2501003)(8936002)(99286004)(25786009)(36756003)(256004)(4326008)(6486002)(478600001)(186003)(110136005)(486006)(14454004)(54906003)(446003)(72206003)(11346002)(2906002)(52116002)(2616005)(476003)(6506007)(386003)(76176011)(6436002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2845;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 2q074iE+Oam0Q2U1Ev9TmvW6UH/08+qiVUVZu5FBC6RuwXDshbsqvD/SI8+kH4gHsqRdQjUXDXAfAmne3WkPAFkg4aWqi1rf7U6AcP8X5i7RfMXNmFm56V9EXHNQXP9UOXujOqzCiFmkEokq/u0M07UaLHckSOI4f5Du9UavEPgML77JekunusTIaIPfereab7HqfdO4IE9OiAS906mWvbMCWnBXmDn/bm0GDKYBFSK+sD/f2iyPD4PiRFvxSzl+bwG5N1Ge0PcWaHQkJDWAFfXuNZgUP00j2jnoNVwNgu+5FvIAN+MlODs87P1LprXyy4ykEC0XZy3Bip8kpesojBW8hv9rdMK9poiLLlva3vsnd7HfSmKlaXE9ExpJ6IVXbkkHRincvhGHsXQs0Pel1FFq2oMr1VOI9mKzxfgN1hM= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55d53135-e4a5-41e0-d400-08d6b9441b6c X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:49.2588 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2845 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add attributes for registers that are supported by the platform. This prevents unsupported optional registers from having sysfs entries created. Also, add a macro REG_SUPPORTED which will decide on the check to perform based on the type of register. Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 100 +++++++++++++++++++++++++++++++++------ 1 file changed, 86 insertions(+), 14 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 56a09e057c4f..37157d19d2df 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -187,22 +187,8 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, } define_one_cppc_ro(feedback_ctrs); -static struct attribute *cppc_attrs[] = { - &feedback_ctrs.attr, - &reference_perf.attr, - &wraparound_time.attr, - &highest_perf.attr, - &lowest_perf.attr, - &lowest_nonlinear_perf.attr, - &nominal_perf.attr, - &nominal_freq.attr, - &lowest_freq.attr, - NULL -}; - static struct kobj_type cppc_ktype = { .sysfs_ops = &kobj_sysfs_ops, - .default_attrs = cppc_attrs, }; static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) @@ -717,6 +703,87 @@ static bool is_cppc_supported(int revision, int num_ent) * } */ +static bool is_buf_only(int reg_idx) +{ + switch (reg_idx) { + case HIGHEST_PERF: + case NOMINAL_PERF: + case LOW_NON_LINEAR_PERF: + case LOWEST_PERF: + case CTR_WRAP_TIME: + case AUTO_SEL_ENABLE: + case REFERENCE_PERF: + return false; + default: + return true; + } +} + +#define REG_SUPPORTED(cpc, idx) (is_buf_only(idx) ? \ + CPC_SUP_BUFFER_ONLY(&cpc->cpc_regs[idx]) : \ + CPC_SUPPORTED(&cpc->cpc_regs[idx])) + +static int is_mandatory_reg(int reg_idx) +{ + switch (reg_idx) { + case HIGHEST_PERF: + case NOMINAL_PERF: + case LOW_NON_LINEAR_PERF: + case LOWEST_PERF: + case REFERENCE_CTR: + case DELIVERED_CTR: + return 1; + } + + return 0; +} + +#define MANDATORY_REG_CNT 6 + +static int set_cppc_attrs(struct cpc_desc *cpc, int entries) +{ + int i, attr_i = 0, opt_reg_cnt = entries - MANDATORY_REG_CNT; + static struct attribute **cppc_attrs; + + cppc_attrs = kcalloc(entries, sizeof(*cppc_attrs), GFP_KERNEL); + if (!cppc_attrs) + return -ENOMEM; + + for (i = 0; i < MAX_CPC_REG_ENT && attr_i < opt_reg_cnt; i++) { + if (is_mandatory_reg(i) || !REG_SUPPORTED(cpc, i)) + continue; + + switch (i) { + case NOMINAL_FREQ: + cppc_attrs[attr_i++] = &nominal_freq.attr; + break; + case LOWEST_FREQ: + cppc_attrs[attr_i++] = &lowest_freq.attr; + break; + case REFERENCE_PERF: + cppc_attrs[attr_i++] = &reference_perf.attr; + break; + case CTR_WRAP_TIME: + cppc_attrs[attr_i++] = &wraparound_time.attr; + break; + } + } + + /* Set mandatory regs */ + cppc_attrs[attr_i++] = &highest_perf.attr; + cppc_attrs[attr_i++] = &nominal_perf.attr; + cppc_attrs[attr_i++] = &lowest_nonlinear_perf.attr; + cppc_attrs[attr_i++] = &lowest_perf.attr; + + /* Set feedback_ctr sysfs entry */ + cppc_attrs[attr_i] = &feedback_ctrs.attr; + + /* Set kobj_type member */ + cppc_ktype.default_attrs = cppc_attrs; + + return 0; +} + /** * acpi_cppc_processor_probe - Search for per CPU _CPC objects. * @pr: Ptr to acpi_processor containing this CPUs logical Id. @@ -871,6 +938,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) /* Plug PSD data into this CPUs CPC descriptor. */ per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; + ret = set_cppc_attrs(cpc_ptr, num_ent - 2); + if (ret) + goto out_free; + ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, "acpi_cppc"); if (ret) { @@ -932,6 +1003,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr) iounmap(addr); } + kfree(cppc_ktype.default_attrs); kobject_put(&cpc_ptr->kobj); kfree(cpc_ptr); } From patchwork Thu Apr 4 21:25:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886361 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 379D817E9 for ; Thu, 4 Apr 2019 21:26:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2848F28AFA for ; Thu, 4 Apr 2019 21:26:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1CD9228B04; Thu, 4 Apr 2019 21:26:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C196A28AFA for ; Thu, 4 Apr 2019 21:26:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730763AbfDDVZ6 (ORCPT ); Thu, 4 Apr 2019 17:25:58 -0400 Received: from mail-eopbgr740047.outbound.protection.outlook.com ([40.107.74.47]:6544 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730720AbfDDVZ5 (ORCPT ); Thu, 4 Apr 2019 17:25:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JFFa75NoUBhFlV+yqE//c6N02FdJVCEv38LUuxoZ02Q=; b=5uUvU63DQf/qtzrCbPYSD6dNZhiSciv7hbIxWePAw3NkWlrko0M/k2T6n5ZGpLk0Y7bnCG+XQ9hefNKOo9DJB4qjqafbjq0Qo13c/nDgHgRC0pUWn5jSGgLXG0+Uo0mXGv0rOwSc0azUTe4riHODQ6C9ohV8aHvMn0s8X9Koup0= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2845.namprd12.prod.outlook.com (52.135.102.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.17; Thu, 4 Apr 2019 21:25:52 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a%4]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 21:25:52 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 3/7] acpi/cppc: Modify show_cppc_data macro Thread-Topic: [PATCH v2 3/7] acpi/cppc: Modify show_cppc_data macro Thread-Index: AQHU6yz6JJqmaPEOAkm3pVU0VSvCPw== Date: Thu, 4 Apr 2019 21:25:50 +0000 Message-ID: <4ccf8a16e59b500946b3bdd13419a4956692528b.1554410643.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5bf66619-d84d-4a20-57db-08d6b9441c6f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2845; x-ms-traffictypediagnostic: SN6PR12MB2845: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(136003)(376002)(396003)(366004)(346002)(199004)(189003)(305945005)(5660300002)(26005)(102836004)(105586002)(66066001)(118296001)(8676002)(106356001)(6116002)(3846002)(81156014)(97736004)(68736007)(53936002)(81166006)(316002)(7736002)(2201001)(50226002)(71190400001)(71200400001)(86362001)(14444005)(6512007)(2501003)(8936002)(99286004)(25786009)(36756003)(256004)(4326008)(6486002)(478600001)(186003)(110136005)(486006)(14454004)(54906003)(446003)(72206003)(11346002)(2906002)(52116002)(2616005)(476003)(6506007)(386003)(76176011)(6436002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2845;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: B0YbOAYG+6khKLDSUsyI7qVsvTpgHpbtweWwKPt4ZxVsGHoLSG2Nfeqe5cOR5mb2qayH95VL6fY9LSbSycxfHTb0J5pgaYOaviYETBLgiEpDfciKrlB4RX+ezkTQTTmbWRhedNw219iVhyHFFtdC1mU7GVsVcEhgM7xa4Ls1NDHlaTrH6OgMkXrOgeHAFyz2PkHqL+fs9A17ViXsx796fQcIj4SRAZjCmRFYlVoEq7/hYSZIAhs/EQ8pTDrvOg2525l2bzdM+UTewuICoQ+7HVzav8Yx57EWf6oxefHivbAxG93J7Zn7763+h0/xEjQtbe25nCdDhvFXmO80VyWrGPQftoaeW1RHfbulh6zbJRj3bqVbsp7NpAUOpXF2ZBMWFCR8y26JTfcyUFzTgBO7RbWqlCYBRwu6byK0f+H8LPk= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5bf66619-d84d-4a20-57db-08d6b9441c6f X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:50.9300 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2845 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam The show_cppc_data macro implicity uses define_one_cppc_ro. This will prevent the creation of an attribute with read and write permissions. Create a separate macro that defines a show attribute and creates a read-only sysfs entry. This is in preparation for adding a macro to create sysfs entries with read+write permission. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 37157d19d2df..10ae5a5818e6 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -159,17 +159,20 @@ __ATTR(_name, 0444, show_##_name, NULL) return scnprintf(buf, PAGE_SIZE, "%llu\n", \ (u64)st_name.member_name); \ } \ + +#define show_cppc_data_ro(access_fn, struct_name, member_name) \ + show_cppc_data(access_fn, struct_name, member_name) \ define_one_cppc_ro(member_name) -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, highest_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); +show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); +show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); static ssize_t show_feedback_ctrs(struct kobject *kobj, struct attribute *attr, char *buf) From patchwork Thu Apr 4 21:25:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886355 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8F38922 for ; Thu, 4 Apr 2019 21:26:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C20FC28AF6 for ; Thu, 4 Apr 2019 21:26:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B670128AFB; Thu, 4 Apr 2019 21:26:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CF9428AF6 for ; Thu, 4 Apr 2019 21:26:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730812AbfDDV0B (ORCPT ); Thu, 4 Apr 2019 17:26:01 -0400 Received: from mail-eopbgr760073.outbound.protection.outlook.com ([40.107.76.73]:65094 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729400AbfDDV0A (ORCPT ); Thu, 4 Apr 2019 17:26:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VoKZKg93QxQs8RdMc/bIm79fcRjrtFnRYfzcaPH1Kpc=; b=Mz4WUeB9xvEf5YOFjlgcWfMuOOGzo4vkrB9y9YR2p5jzabRB3fX5B/WU3Kpv329gkkO5ml4zliJux2d01R1JWLCbhhqi99CocuNHhtc1gQ9yA1DCOPJAQJ5ZRbF36TtmetkNn9lohUlXq6L1d+IKRsxoxiMgJ0zWC1Z4dbGG3uM= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2784.namprd12.prod.outlook.com (52.135.107.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.22; Thu, 4 Apr 2019 21:25:53 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a%4]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 21:25:53 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 4/7] acpi/cppc: Rework cppc_set_perf() to use cppc_regs index Thread-Topic: [PATCH v2 4/7] acpi/cppc: Rework cppc_set_perf() to use cppc_regs index Thread-Index: AQHU6yz7GJ1UZm6gP0OxbL1joCOEFw== Date: Thu, 4 Apr 2019 21:25:52 +0000 Message-ID: <3a7e7f2f252958bfbf3cbe69d90870122f99bad6.1554410643.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9d84caa0-b574-4380-c322-08d6b9441d55 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:SN6PR12MB2784; x-ms-traffictypediagnostic: SN6PR12MB2784: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(346002)(366004)(396003)(136003)(376002)(199004)(189003)(97736004)(6436002)(478600001)(71200400001)(118296001)(7736002)(71190400001)(36756003)(14444005)(256004)(72206003)(4326008)(2201001)(86362001)(486006)(68736007)(14454004)(6486002)(66066001)(316002)(8676002)(2501003)(102836004)(52116002)(2906002)(110136005)(26005)(99286004)(6506007)(54906003)(76176011)(2616005)(186003)(81156014)(5660300002)(81166006)(305945005)(50226002)(8936002)(6512007)(25786009)(53936002)(6116002)(446003)(106356001)(105586002)(3846002)(476003)(11346002)(386003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2784;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: C3g1N1KSGsjDOoc1wXhmllQP20+8faK5t5f2Vzv0au7tfGqmgFVoGNJLsryejlCFYAQ+2m4sgr8HwCDxepcLbKVtpYWc8ek02rmjDja/Yh27tH/Kn18yvmnVtWssDCEGRuuppU/7PdUVlW47Jpr3MWv53bo6FyXcjDodmjzFlXDK6Eg2zZdkVoclxJHQNU6LuWi2m3frkKZh56t/kRI8betEzhvVEYniMYlXqbX73FA5+Vq7c1gWqNSWGkDWbI7uONPgEtqaEyh6nyVkih/ID5YQ4un3UrdYF9tjQH+pOvehjYE1aq21T92Cjh+7u1zy6fyoFXE3mXOiaDL/g01u213aKVzMtOm6TwD3Q6ag4uWVygBSHTtMao1r3y0Ih1iSS/CHR7bImjqbVbmVJHYM358znKPpJlvPJXNQHEZHxKk= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d84caa0-b574-4380-c322-08d6b9441d55 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:52.6482 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2784 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam The cppc_set_perf() currently only works for DESIRED_PERF. To make it generic, pass in the index of the register being accessed. Also, rename cppc_set_perf() to cppc_set_reg(). This is in preparation for it to be used for more than just the DESIRED_PERF register. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 36 ++++++++++++++++++++++------------ drivers/cpufreq/cppc_cpufreq.c | 6 +++--- include/acpi/cppc_acpi.h | 2 +- 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 10ae5a5818e6..1cce231b8501 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -60,7 +60,7 @@ struct cppc_pcc_data { /* * Lock to provide controlled access to the PCC channel. * - * For performance critical usecases(currently cppc_set_perf) + * For performance-critical usecases(currently cppc_set_reg) * We need to take read_lock and check if channel belongs to OSPM * before reading or writing to PCC subspace * We need to take write_lock before transferring the channel @@ -1346,26 +1346,38 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); /** - * cppc_set_perf - Set a CPUs performance controls. - * @cpu: CPU for which to set performance controls. + * cppc_set_reg - Set the CPUs control register. + * @cpu: CPU for which to set the register. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * @reg_idx: Index of the register being accessed * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, + enum cppc_regs reg_idx) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); - struct cpc_register_resource *desired_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; + struct cpc_register_resource *reg; int ret = 0; + u32 value; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpu); return -ENODEV; } - desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + switch (reg_idx) { + case DESIRED_PERF: + value = perf_ctrls->desired_perf; + break; + default: + pr_debug("CPC register index #%d not writeable\n", reg_idx); + return -EINVAL; + } + + reg = &cpc_desc->cpc_regs[reg_idx]; /* * This is Phase-I where we want to write to CPC registers @@ -1374,7 +1386,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * Since read_lock can be acquired by multiple CPUs simultaneously we * achieve that goal here */ - if (CPC_IN_PCC(desired_reg)) { + if (CPC_IN_PCC(reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1401,14 +1413,14 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * Skip writing MIN/MAX until Linux knows how to come up with * useful values. */ - cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); + cpc_write(cpu, reg, value); - if (CPC_IN_PCC(desired_reg)) + if (CPC_IN_PCC(reg)) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ /* * This is Phase-II where we transfer the ownership of PCC to Platform * - * Short Summary: Basically if we think of a group of cppc_set_perf + * Short Summary: Basically if we think of a group of cppc_set_reg * requests that happened in short overlapping interval. The last CPU to * come out of Phase-I will enter Phase-II and ring the doorbell. * @@ -1451,7 +1463,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * case during a CMD_READ and if there are pending writes it delivers * the write command before servicing the read command */ - if (CPC_IN_PCC(desired_reg)) { + if (CPC_IN_PCC(reg)) { if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ /* Update only if there are pending write commands */ if (pcc_ss_data->pending_pcc_write_cmd) @@ -1467,7 +1479,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } return ret; } -EXPORT_SYMBOL_GPL(cppc_set_perf); +EXPORT_SYMBOL_GPL(cppc_set_reg); /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 2ae978d27e61..420bd44f6958 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -211,7 +211,7 @@ static int cppc_cpufreq_set_target(struct cpufreq_policy *policy, freqs.new = target_freq; cpufreq_freq_transition_begin(policy, &freqs); - ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu->cpu, &cpu->perf_ctrls, DESIRED_PERF); cpufreq_freq_transition_end(policy, &freqs, ret != 0); if (ret) @@ -235,7 +235,7 @@ static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy) cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf; - ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu_num, &cpu->perf_ctrls, DESIRED_PERF); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", cpu->perf_caps.lowest_perf, cpu_num, ret); @@ -348,7 +348,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) cpu->perf_caps.highest_perf); cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf; - ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu_num, &cpu->perf_ctrls, DESIRED_PERF); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", cpu->perf_caps.highest_perf, cpu_num, ret); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index ba6fd7202775..ba3b3fb64572 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,7 +139,7 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); -extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Thu Apr 4 21:25:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B956A17E1 for ; Thu, 4 Apr 2019 21:26:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB27A28AF8 for ; Thu, 4 Apr 2019 21:26:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9FB1928B04; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 5/7] acpi/cppc: Add macros to define a R/W sysfs entry for CPPC registers Thread-Topic: [PATCH v2 5/7] acpi/cppc: Add macros to define a R/W sysfs entry for CPPC registers Thread-Index: AQHU6yz79kHizkaTb0yix5NLjnzz5A== Date: Thu, 4 Apr 2019 21:25:53 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1d7e4330-6b65-48cf-fbdc-08d6b9441e41 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:SN6PR12MB2784; x-ms-traffictypediagnostic: SN6PR12MB2784: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(346002)(366004)(396003)(136003)(376002)(199004)(189003)(97736004)(6436002)(478600001)(71200400001)(118296001)(7736002)(71190400001)(36756003)(14444005)(256004)(72206003)(4326008)(2201001)(86362001)(486006)(68736007)(14454004)(6486002)(66066001)(316002)(8676002)(2501003)(102836004)(52116002)(2906002)(110136005)(26005)(99286004)(6506007)(54906003)(76176011)(2616005)(186003)(81156014)(5660300002)(81166006)(305945005)(50226002)(8936002)(6512007)(25786009)(53936002)(6116002)(446003)(106356001)(105586002)(3846002)(476003)(11346002)(386003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2784;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: r8TZYo7KSHG6zwxbiJ+W9vzfYshfYJ++0nvo1xMWjZy4CZ/9hZqK4bRiMOTvZKCJmyOE2lKh/KT7NFp8eB05iHJMI6QyY5JBtkoH4WTkHncMk1BLblR+Vcq0Xr3OgJN1QQmslh3KS5fs6CHnirJwAhUhcTgKPQi9X5aH9OsQFsoRMdsoQ4rhIu3lr3CPkSPtLSd2B4+QgQxhAUEEbAy12K6X3LlzB4VzWLvV8Hsbqj+k4DMLhDK62kl7EAmKqh1A009I/633s4P9jkmN3mY8TyVuY5TCDVev8mMuauq6tVgBYUc2kJOZD0QD4Z9ew14q1WcbTVw3Rtcu7BVW/5X+HcmVPE4c/fJs8pD2s9je4Z9ZUvYge4LqNQ3V4QGU0EhkeR3hsnEJT+RamNXvz19cffxsmCJ69CeLF7FpA7XoKRY= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1d7e4330-6b65-48cf-fbdc-08d6b9441e41 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:53.8330 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2784 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam Some CPPC registers can be used to configure the platform. To enable this, create macros to define the show, store routines and create sysfs entries with R/W permission. Signed-off-by: Yazen Ghannam [ carved into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 1cce231b8501..1e862415faf0 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -142,6 +142,10 @@ struct cppc_attr { static struct cppc_attr _name = \ __ATTR(_name, 0444, show_##_name, NULL) +#define define_one_cppc_rw(_name) \ +static struct cppc_attr _name = \ +__ATTR(_name, 0644, show_##_name, store_##_name) + #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) #define show_cppc_data(access_fn, struct_name, member_name) \ @@ -164,6 +168,33 @@ __ATTR(_name, 0444, show_##_name, NULL) show_cppc_data(access_fn, struct_name, member_name) \ define_one_cppc_ro(member_name) +#define store_cppc_data(struct_name, member_name, reg_idx) \ + static ssize_t store_##member_name(struct kobject *kobj, \ + struct attribute *attr, \ + const char *c, ssize_t count)\ + { \ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ + struct struct_name st_name = {0}; \ + u32 val; \ + int ret; \ + \ + ret = kstrtou32(c, 0, &val); \ + if (ret) \ + return ret; \ + \ + st_name.member_name = val; \ + \ + ret = cppc_set_reg(cpc_ptr->cpu_id, &st_name, reg_idx); \ + if (ret) \ + return ret; \ + \ + return count; \ + } \ + +#define store_cppc_data_rw(struct_name, member_name, reg_idx) \ + store_cppc_data(struct_name, member_name, reg_idx) \ + define_one_cppc_rw(member_name) + show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, highest_perf); show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); From patchwork Thu Apr 4 21:25:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886371 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A014F922 for ; Thu, 4 Apr 2019 21:26:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 923B728AF6 for ; Thu, 4 Apr 2019 21:26:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8638328AFA; Thu, 4 Apr 2019 21:26:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCFE128AF6 for ; Thu, 4 Apr 2019 21:26:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730210AbfDDV0U (ORCPT ); Thu, 4 Apr 2019 17:26:20 -0400 Received: from mail-eopbgr760073.outbound.protection.outlook.com ([40.107.76.73]:65094 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729400AbfDDV0U (ORCPT ); Thu, 4 Apr 2019 17:26:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nCLOiXEqYHT5rVVxMtxxuuqR9NNXeUhqaZrcZ9KShG0=; b=CH1GCdKkrcKFeq0u6JwVfamapQXc/A1MkKOb9m2eeBdu5MpFExqyYlf3yfuZqHg47lfaanNt8OHaGdSkEdlygiOWvRNUgI4EFSj1ZrultGukouV1udfS5K/DSanUqU5M0iDiPJfNR8LA9VjsKQFGU3em47/92MQG51H+yu+lHkY= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2784.namprd12.prod.outlook.com (52.135.107.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.22; Thu, 4 Apr 2019 21:25:55 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::65cb:af55:6bd4:55a%4]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 21:25:55 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 6/7] acpi/cppc: Add support for optional CPPC registers Thread-Topic: [PATCH v2 6/7] acpi/cppc: Add support for optional CPPC registers Thread-Index: AQHU6yz8Ze4s7qGdUEKuNcRjfPi3YA== Date: Thu, 4 Apr 2019 21:25:55 +0000 Message-ID: <7c999115c8ef4cdaeb4ca2839fdcd01485292ac8.1554410643.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b8af6c15-9ad3-4e5b-b84b-08d6b9441f12 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:SN6PR12MB2784; x-ms-traffictypediagnostic: SN6PR12MB2784: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(346002)(366004)(396003)(136003)(376002)(199004)(189003)(97736004)(6436002)(478600001)(71200400001)(118296001)(7736002)(71190400001)(36756003)(14444005)(256004)(72206003)(4326008)(2201001)(86362001)(486006)(68736007)(14454004)(6486002)(66066001)(316002)(8676002)(2501003)(102836004)(52116002)(2906002)(110136005)(26005)(99286004)(6506007)(54906003)(76176011)(2616005)(186003)(81156014)(5660300002)(81166006)(305945005)(50226002)(8936002)(6512007)(25786009)(53936002)(6116002)(446003)(106356001)(105586002)(3846002)(476003)(11346002)(386003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2784;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: SrxzS1TXSuZJSSdG8VTCe7TwrT1cLYQuzqjl93dTVWqax6ZygZ7/HAMmfnE5rNJh3jrLnrtTpRX8D5/JIB5mOtk9pvmp5L/pW+eRNJswpd6vM/5DBBOf5SpkGVn0HerQoNclOeE1LqGfdLyhs9wCW4TAbknIXhKVvayq0QLd0mIiUhj/3MXU60/IeF4Cdc1XJeYhxSmh0Ssy6WHG458McE7RW0Ok+PI+2eG+yNCBwhn2tASzBANYpFw7fysoUCv66bV0i/SfIUnEFbFALE7Ublgs+CrkZw7s2j2qwY8FYtu9/80+RFEZzBQWSihGod4CD2I3oS08sMFS1rlX4sEs0Gr01rJ9Gz3Elt9w8TlVTsro7cbiOmXV4MZzD2ht+V5MntymOgKzBMDgUGwMSgZMOxHCh7qiwJU91OkZqFueAfI= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b8af6c15-9ad3-4e5b-b84b-08d6b9441f12 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:55.3221 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2784 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam Newer AMD processors support a subset of the optional CPPC registers. Create show, store and helper routines for supported CPPC registers. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 120 ++++++++++++++++++++++++++++++++++++--- include/acpi/cppc_acpi.h | 3 + 2 files changed, 115 insertions(+), 8 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 1e862415faf0..bb57d526e54e 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -204,6 +204,17 @@ show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, desired_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, max_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, min_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, energy_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, auto_sel_enable); + +store_cppc_data_rw(cppc_perf_ctrls, desired_perf, DESIRED_PERF); +store_cppc_data_rw(cppc_perf_ctrls, max_perf, MAX_PERF); +store_cppc_data_rw(cppc_perf_ctrls, min_perf, MIN_PERF); +store_cppc_data_rw(cppc_perf_ctrls, energy_perf, ENERGY_PERF); +store_cppc_data_rw(cppc_perf_ctrls, auto_sel_enable, AUTO_SEL_ENABLE); static ssize_t show_feedback_ctrs(struct kobject *kobj, struct attribute *attr, char *buf) @@ -800,6 +811,21 @@ static int set_cppc_attrs(struct cpc_desc *cpc, int entries) case CTR_WRAP_TIME: cppc_attrs[attr_i++] = &wraparound_time.attr; break; + case MAX_PERF: + cppc_attrs[attr_i++] = &max_perf.attr; + break; + case MIN_PERF: + cppc_attrs[attr_i++] = &min_perf.attr; + break; + case ENERGY_PERF: + cppc_attrs[attr_i++] = &energy_perf.attr; + break; + case AUTO_SEL_ENABLE: + cppc_attrs[attr_i++] = &auto_sel_enable.attr; + break; + case DESIRED_PERF: + cppc_attrs[attr_i++] = &desired_perf.attr; + break; } } @@ -1391,7 +1417,7 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; struct cpc_register_resource *reg; - int ret = 0; + int ret = 0, regs_in_pcc = 0; u32 value; if (!cpc_desc) { @@ -1403,6 +1429,18 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, case DESIRED_PERF: value = perf_ctrls->desired_perf; break; + case MAX_PERF: + value = perf_ctrls->max_perf; + break; + case MIN_PERF: + value = perf_ctrls->min_perf; + break; + case ENERGY_PERF: + value = perf_ctrls->energy_perf; + break; + case AUTO_SEL_ENABLE: + value = perf_ctrls->auto_sel_enable; + break; default: pr_debug("CPC register index #%d not writeable\n", reg_idx); return -EINVAL; @@ -1418,6 +1456,7 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, * achieve that goal here */ if (CPC_IN_PCC(reg)) { + regs_in_pcc = 1; if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1440,13 +1479,10 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, cpc_desc->write_cmd_status = 0; } - /* - * Skip writing MIN/MAX until Linux knows how to come up with - * useful values. - */ - cpc_write(cpu, reg, value); + if (CPC_SUPPORTED(reg)) + cpc_write(cpu, reg, value); - if (CPC_IN_PCC(reg)) + if (regs_in_pcc) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ /* * This is Phase-II where we transfer the ownership of PCC to Platform @@ -1494,7 +1530,7 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, * case during a CMD_READ and if there are pending writes it delivers * the write command before servicing the read command */ - if (CPC_IN_PCC(reg)) { + if (regs_in_pcc) { if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ /* Update only if there are pending write commands */ if (pcc_ss_data->pending_pcc_write_cmd) @@ -1512,6 +1548,74 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } EXPORT_SYMBOL_GPL(cppc_set_reg); +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_reg, *max_reg, *min_reg; + struct cpc_register_resource *energy_reg, *auto_sel_enable_reg; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + u64 desired, max, min, energy, auto_sel_enable; + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU: %d\n", cpu); + return -ENODEV; + } + + desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + max_reg = &cpc_desc->cpc_regs[MAX_PERF]; + min_reg = &cpc_desc->cpc_regs[MIN_PERF]; + energy_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + auto_sel_enable_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(max_reg) || + CPC_IN_PCC(min_reg) || CPC_IN_PCC(energy_reg) || + CPC_IN_PCC(auto_sel_enable_reg)) { + pcc_ss_data = pcc_data[pcc_ss_id]; + down_write(&pcc_ss_data->pcc_lock); + regs_in_pcc = 1; + + /*Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret = -EIO; + goto out_err; + } + } + + /* desired_perf is the only mandatory value in perf_ctrls */ + if (cpc_read(cpu, desired_reg, &desired)) + ret = -EFAULT; + + if (CPC_SUP_BUFFER_ONLY(max_reg) && cpc_read(cpu, max_reg, &max)) + ret = -EFAULT; + + if (CPC_SUP_BUFFER_ONLY(min_reg) && cpc_read(cpu, min_reg, &min)) + ret = -EFAULT; + + if (CPC_SUP_BUFFER_ONLY(energy_reg) && + cpc_read(cpu, energy_reg, &energy)) + ret = -EFAULT; + + if (CPC_SUPPORTED(auto_sel_enable_reg) && + cpc_read(cpu, auto_sel_enable_reg, &auto_sel_enable)) + ret = -EFAULT; + + if (!ret) { + perf_ctrls->desired_perf = desired; + perf_ctrls->max_perf = max; + perf_ctrls->min_perf = min; + perf_ctrls->energy_perf = energy; + perf_ctrls->auto_sel_enable = auto_sel_enable; + } + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); + /** * cppc_get_transition_latency - returns frequency transition latency in ns * diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index ba3b3fb64572..6f651235933c 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -117,6 +117,8 @@ struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 auto_sel_enable; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -140,6 +142,7 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); +extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Thu Apr 4 21:25:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10886367 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AAED17E1 for ; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH v2 7/7] acpi/cppc: Add support for CPPC Enable register Thread-Topic: [PATCH v2 7/7] acpi/cppc: Add support for CPPC Enable register Thread-Index: AQHU6yz+DxZ5qtCYS0KW8MgU0wIz4g== Date: Thu, 4 Apr 2019 21:25:57 +0000 Message-ID: <22e1dec2fc26026647dc0f367b2e79599e062399.1554410643.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0052.namprd02.prod.outlook.com (2603:10b6:803:20::14) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1e6e04ae-13db-469b-6782-08d6b9442046 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:SN6PR12MB2784; x-ms-traffictypediagnostic: SN6PR12MB2784: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(39860400002)(346002)(366004)(396003)(136003)(376002)(199004)(189003)(97736004)(6436002)(478600001)(71200400001)(118296001)(7736002)(71190400001)(36756003)(14444005)(256004)(72206003)(4326008)(2201001)(86362001)(486006)(68736007)(14454004)(6486002)(66066001)(316002)(8676002)(2501003)(102836004)(52116002)(2906002)(110136005)(26005)(99286004)(6506007)(54906003)(76176011)(2616005)(186003)(81156014)(5660300002)(81166006)(305945005)(50226002)(8936002)(6512007)(25786009)(53936002)(6116002)(446003)(106356001)(105586002)(3846002)(476003)(11346002)(386003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2784;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: MFgc768k2mNtPBzZBFer4IvDzTO7lb7yOwjTeoqAF9Q2D+julURrtTCJ2/bsdhwdz5FunUgyM6U2kMV7WBUYzGI4Zg2+4KW5IL02wS1oXQiecUi8YhU3uJnSvIYWFIV3HQRgIoQFYj/5vZ8BUf9zZD63Yhsw69zgoETfhDh/n5FaOdUOTO8or/OH2+l/j9Fqq95uOvOyGO7VMOGz7HxvzG8Kgy9FATch7bMwQ5si47jmZ6EVF8FzLBqvZ5Tcj9/FzJ9+dVLM7BHWrIpCiSsnhMtf5dBTIl9S1ZMP83bMnvDm7jPriY/s6tNaRspw1lK3XCjd+InxE+AYeLEBZMLE5rhbf+jRPFKX/HDN9cTfTE/G4Cl77Nn6xDl9XrLumJGlITfL16Z0vUq2sIDnpsidKmdetxHR1vr3CWV2MRYkPHc= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e6e04ae-13db-469b-6782-08d6b9442046 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 21:25:57.6618 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2784 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam To enable CPPC on a processor, the OS should write a value "1" to the CPPC Enable register. Add support for this register. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 96 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 1 + 2 files changed, 97 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index bb57d526e54e..b74c489a3e8d 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -232,6 +232,43 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, } define_one_cppc_ro(feedback_ctrs); +/* Used to move ENABLE register value between userspace and platform */ +static bool cppc_cpu_enable; + +static ssize_t show_enable(struct kobject *kobj, + struct attribute *attr, + char *buf) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + int ret; + + ret = cppc_get_enable(cpc_ptr->cpu_id); + if (ret) + return ret; + + return scnprintf(buf, PAGE_SIZE, "%d\n", cppc_cpu_enable); +} + +static ssize_t store_enable(struct kobject *kobj, + struct attribute *attr, + const char *c, ssize_t count) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + int ret; + + ret = kstrtobool(c, &cppc_cpu_enable); + if (ret) + return ret; + + ret = cppc_set_reg(cpc_ptr->cpu_id, NULL, ENABLE); + if (ret) + return ret; + + return count; +} + +define_one_cppc_rw(enable); + static struct kobj_type cppc_ktype = { .sysfs_ops = &kobj_sysfs_ops, }; @@ -826,6 +863,9 @@ static int set_cppc_attrs(struct cpc_desc *cpc, int entries) case DESIRED_PERF: cppc_attrs[attr_i++] = &desired_perf.attr; break; + case ENABLE: + cppc_attrs[attr_i++] = &enable.attr; + break; } } @@ -1426,6 +1466,9 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } switch (reg_idx) { + case ENABLE: + value = cppc_cpu_enable; + break; case DESIRED_PERF: value = perf_ctrls->desired_perf; break; @@ -1616,6 +1659,59 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } EXPORT_SYMBOL_GPL(cppc_get_perf); +/** + * cppc_get_enable - Read a CPUs enable register. + * @cpu: CPU from which to read control values. + * + * Return: 0 for success. + */ +int cppc_get_enable(int cpu) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *enable_reg; + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + u64 enable; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU: %d\n", cpu); + return -ENODEV; + } + + enable_reg = &cpc_desc->cpc_regs[ENABLE]; + + if (!CPC_SUP_BUFFER_ONLY(enable_reg)) { + pr_warn("CPC ENABLE register not supported.\n"); + return -ENOTSUPP; + } + + if (CPC_IN_PCC(enable_reg)) { + pcc_ss_data = pcc_data[pcc_ss_id]; + down_write(&pcc_ss_data->pcc_lock); + regs_in_pcc = 1; + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret = -EIO; + goto out_err; + } + } + + if (cpc_read(cpu, enable_reg, &enable)) { + ret = -EFAULT; + goto out_err; + } + + cppc_cpu_enable = enable; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_enable); + /** * cppc_get_transition_latency - returns frequency transition latency in ns * diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6f651235933c..fcdedff8e6bd 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { cpumask_var_t shared_cpu_map; }; +extern int cppc_get_enable(int cpu); extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx);