From patchwork Thu Apr 4 23:22:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kasireddy, Vivek" X-Patchwork-Id: 10886663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1863A1390 for ; Thu, 4 Apr 2019 23:41:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EECD628B00 for ; Thu, 4 Apr 2019 23:41:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E2B0A28B05; Thu, 4 Apr 2019 23:41:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5C6FC28B00 for ; Thu, 4 Apr 2019 23:41:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A8936E5C4; Thu, 4 Apr 2019 23:41:00 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19B3E6E5C4 for ; Thu, 4 Apr 2019 23:40:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Apr 2019 16:40:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,309,1549958400"; d="scan'208";a="128743463" Received: from orsmsx101.amr.corp.intel.com ([10.22.225.128]) by orsmga007.jf.intel.com with ESMTP; 04 Apr 2019 16:40:58 -0700 Received: from orsmsx155.amr.corp.intel.com (10.22.240.21) by ORSMSX101.amr.corp.intel.com (10.22.225.128) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 4 Apr 2019 16:40:58 -0700 Received: from vkasired-desk2.fm.intel.com (10.22.254.140) by ORSMSX155.amr.corp.intel.com (10.22.240.21) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 4 Apr 2019 16:40:57 -0700 From: Vivek Kasireddy To: Date: Thu, 4 Apr 2019 16:22:37 -0700 Message-ID: <20190404232237.20290-1-vivek.kasireddy@intel.com> X-Mailer: git-send-email 2.14.5 MIME-Version: 1.0 X-Originating-IP: [10.22.254.140] Subject: [Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v2) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for DPLL4 on EHL that include the following restrictions: - DPLL4 cannot be used with DDIA (combo port A internal eDP usage). DPLL4 can be used with other DDIs, including DDID (combo port A external usage). - DPLL4 cannot be enabled when DC5 or DC6 are enabled. - The DPLL4 enable, lock, power enabled, and power state are connected to the MGPLL1_ENABLE register. v2: (suggestions from Bob Paauwe) - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and iterate twice: once for Combo plls and once for MG plls. - Use MG pll funcs for DPLL4 instead of creating new ones and modify mg_pll_enable to include the restrictions for EHL. Cc: Lucas De Marchi Signed-off-by: Vivek Kasireddy Reviewed-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 60 ++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index e01c057ce50b..cb756acedc94 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2870,6 +2870,56 @@ icl_get_dpll(struct intel_crtc_state *crtc_state, return pll; } +static struct intel_shared_dpll * +ehl_get_dpll(struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); + struct intel_shared_dpll *pll; + enum port port = encoder->port; + enum intel_dpll_id min, max; + bool ret; + + if (!intel_port_is_combophy(dev_priv, port)) { + MISSING_CASE(port); + return NULL; + } + + min = DPLL_ID_ICL_DPLL0; + max = DPLL_ID_ICL_DPLL1; + ret = icl_calc_dpll_state(crtc_state, encoder); + if (ret) { + pll = intel_find_shared_dpll(crtc_state, min, max); + if (pll) { + intel_reference_shared_dpll(pll, crtc_state); + return pll; + } + } else { + DRM_DEBUG_KMS("Could not calculate PLL state.\n"); + } + + if (encoder->type == INTEL_OUTPUT_EDP) { + DRM_DEBUG_KMS("Cannot use DPLL4 with EDP.\n"); + return NULL; + } + + min = max = DPLL_ID_ICL_MGPLL1; + ret = icl_calc_mg_pll_state(crtc_state, false); + if (!ret) { + DRM_DEBUG_KMS("Could not calculate PLL state.\n"); + return NULL; + } + + pll = intel_find_shared_dpll(crtc_state, min, max); + if (!pll) { + DRM_DEBUG_KMS("No PLL selected\n"); + return NULL; + } + + intel_reference_shared_dpll(pll, crtc_state); + return pll; +} + static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) @@ -3115,6 +3165,13 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv, i915_reg_t enable_reg = MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id)); + if (IS_ELKHARTLAKE(dev_priv) && + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5 || + I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6)) { + DRM_ERROR("Cant enable DPLL4 when DC5 or DC6 are enabled\n"); + return; + } + icl_pll_power_enable(dev_priv, pll, enable_reg); icl_mg_pll_write(dev_priv, pll); @@ -3249,12 +3306,13 @@ static const struct intel_dpll_mgr icl_pll_mgr = { static const struct dpll_info ehl_plls[] = { { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1,0 }, { }, }; static const struct intel_dpll_mgr ehl_pll_mgr = { .dpll_info = ehl_plls, - .get_dpll = icl_get_dpll, + .get_dpll = ehl_get_dpll, .dump_hw_state = icl_dump_hw_state, };