From patchwork Mon Apr 8 10:14:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 10889233 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1151813B5 for ; Mon, 8 Apr 2019 10:16:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC9EC285A4 for ; Mon, 8 Apr 2019 10:16:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E0A2E285C9; Mon, 8 Apr 2019 10:16:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8DF00285A4 for ; Mon, 8 Apr 2019 10:16:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hDRIt-0003mO-9o; Mon, 08 Apr 2019 10:15:03 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hDRIr-0003lr-R0 for xen-devel@lists.xenproject.org; Mon, 08 Apr 2019 10:15:01 +0000 X-Inumbo-ID: 2ac39585-59e7-11e9-92d7-bc764e045a96 Received: from mail-lj1-x244.google.com (unknown [2a00:1450:4864:20::244]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 2ac39585-59e7-11e9-92d7-bc764e045a96; Mon, 08 Apr 2019 10:15:01 +0000 (UTC) Received: by mail-lj1-x244.google.com with SMTP id f23so10726286ljc.0 for ; Mon, 08 Apr 2019 03:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qucunmK9xgz8gtRcruJM1bVATnlVA3EmGKtWXeWisWY=; b=tD7Pi+qdvjqpW3r9aG8gWFuhH51F8205ntSRehtwQMoqkin6/PSv1Em/uPw38b7H+G aX4PLvwQQnWFKPYBWoe6GXezbMaLokdlSm3sEAPUkeXmHt/pvh8x4t2cxK5A/IjvALgJ rnpQY1QDEzE9saoWZu9vDZhItpucLu8F8bYcH6LD50bJX/CwY87297ik3xRrO4TyMrv9 IPmQOi5bwMitCF42d4XPkO6s8E0fMgk/zITPKriYCxUdQ6Tb0Dfg2Xe3UQ9uXSUBuNK2 b4zapqW4214mM05p9/X8E22QhONAb7DtBVh6vEjsQbRHboQ52AFMDdWl4GBQrD/xwgVi CtFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qucunmK9xgz8gtRcruJM1bVATnlVA3EmGKtWXeWisWY=; b=KWjRtq7rkNsoQyjQbpSrhu8eZMfi8SJtemdqsCA3ZFHtlbUQrMU7/Anvo5lzRnAmMq CDEs98eoZqCCJ+n4lxSD4t/0cwiJUgTSEei4/0eAUR4b73/eBg4mfvGKSMOUhOgfrzv/ Usg3D4tSIYGK7yQwG34rk28U6ITdLqMBW6GurdKiczWzwQUzlZVm3brA495q72CedpDm IvQb+kq6n30h2Dc9lW4AIPnXUDipo46Ehu38uh/3Da5XW2fmOBTY/agp8yge9OXyvA+B nuiJpWPOI+PzRgnh2lfs86DRwBQ67/WQO7RMeSRwfDyWzsKKBsMRh/KKCcUOuQmmZHhK sqkQ== X-Gm-Message-State: APjAAAVMQOqCsdVttATCEwKHiXIe6iKFZJKuseA+3OgWJBogCLSRdjhB kE1Nl3G7DsrKEf0qYSiKKSWml/H9qXo= X-Google-Smtp-Source: APXvYqzOHJlMDJzxx5EXMO9HRIPvtrfrHsasNXQ9m8hakWs/d89GG3Q7ClPVkerUrq0i/TXU23OCgg== X-Received: by 2002:a2e:9843:: with SMTP id e3mr381201ljj.28.1554718499494; Mon, 08 Apr 2019 03:14:59 -0700 (PDT) Received: from otyshchenko.kyiv.epam.com (ll-22.209.223.85.sovam.net.ua. [85.223.209.22]) by smtp.gmail.com with ESMTPSA id x30sm6275717ljd.38.2019.04.08.03.14.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Apr 2019 03:14:58 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Mon, 8 Apr 2019 13:14:45 +0300 Message-Id: <1554718489-11318-2-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> References: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V3 1/5] xen/arm: Clarify usage of earlyprintk for Lager board X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko Current sentence is not entirely correct. Since SCIF0 interface is applicable for Lager board, but is not applicable for all R-Car H2 based boards. For example, Stout board uses SCIFA0 interface. Signed-off-by: Oleksandr Tyshchenko Acked-by: Julien Grall --- docs/misc/arm/early-printk.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index f765f59..b23c54f 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -39,7 +39,7 @@ the name of the machine: - fastmodel: printk on ARM Fastmodel software emulators - hikey960: printk with pl011 with Hikey 960 - juno: printk with pl011 on Juno platform - - lager: printk with SCIF0 on Renesas R-Car H2 processors + - lager: printk with SCIF0 on Renesas Lager board (R-Car H2 processor) - midway: printk with the pl011 on Calxeda Midway processors - mvebu: printk with the MVEBU for Marvell Armada 3700 SoCs - omap5432: printk with UART3 on TI OMAP5432 processors From patchwork Mon Apr 8 10:14:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksandr Tyshchenko X-Patchwork-Id: 10889237 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F68B1805 for ; Mon, 8 Apr 2019 10:16:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 551B0285A4 for ; Mon, 8 Apr 2019 10:16:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 49C39285E8; Mon, 8 Apr 2019 10:16:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7B2CC285A4 for ; Mon, 8 Apr 2019 10:16:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hDRIu-0003ng-TR; Mon, 08 Apr 2019 10:15:04 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hDRIt-0003mk-Jv for xen-devel@lists.xenproject.org; Mon, 08 Apr 2019 10:15:03 +0000 X-Inumbo-ID: 2b87595f-59e7-11e9-92d7-bc764e045a96 Received: from mail-lf1-x142.google.com (unknown [2a00:1450:4864:20::142]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 2b87595f-59e7-11e9-92d7-bc764e045a96; Mon, 08 Apr 2019 10:15:02 +0000 (UTC) Received: by mail-lf1-x142.google.com with SMTP id a28so9028378lfo.7 for ; Mon, 08 Apr 2019 03:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MHk+ZsNFhbgNEh1E9NW6377RCFWJiyede3RFe1N4FJA=; b=aSVltA+YXUXlJfu7J62qtR77rIQMm3eUleelcPAwV9axlqX8MuGo7JzyJbAabF8j+5 +lIQ9Reru5KHim3hcFS50up3t6l7WngcAbxiaKy8aiJco3HomXK3A2I63uFCHGwiogBJ gi9C3empQrqSh7eDxRofa3dt96Z4EHXWerIZ0x7OjIuU4SvNV5uawAjM6HL6XsH7lJCD QKhf9CM59jEvL+laj7vKAWq2ZoPVfviVEQyn7QzQB/Jedcf35CxjDo8dDTW4+nam+R/E G3QAQbJ8TAWMACa+CZJ9TstOJVbEwk4lX9XwnmMf+fa9RAywcx34daqm5fSwD3ktlDax U2ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MHk+ZsNFhbgNEh1E9NW6377RCFWJiyede3RFe1N4FJA=; b=HoyJUJr11fqC+vYAQ3awgGRYTspOXbHmokQskTy6rOuQClkMLWWZfI9aKXGE78gktx 1jOoyYBm0/tbS/sMAvA1wIt3t56a0ZCnBuqbP1OGXznWQqumzZa4dbQQ0Cr2z0zbZZ99 ldkeIzoKWoasdwosdz7HWmLH7IVgrGtTQiUbtjHfSwbu84RhaEnBgUTxzP7mzbwQ3EbI LY46G1uFluECvjwZlnNTC8d0WjKTu8rztoU6ZrwtqG/YDFJxseqSU4qi/JO4nv3RcFEL Vzo2lWvYNBjteiapYJCVpKTggp8TBh0oTA8gMO14v+dAz/v5FC1EDfawLPhGxWx/c9pW 2NwQ== X-Gm-Message-State: APjAAAUQRLhAAv6LZWspyrTxN0Q6bjmoXDFsoSpghkWhxBoBFttT/nJN 7rvWygFMnrNcHfZs56kjy9cwwLuq0Jk= X-Google-Smtp-Source: APXvYqwJW1DI7lmHVZvogNLBAqm4TddNmXfyIrZHwMuMD8p1WgcvBzefRIOz1Q/dVLKRXs0mVUVGQA== X-Received: by 2002:ac2:4303:: with SMTP id l3mr1376778lfh.61.1554718500622; Mon, 08 Apr 2019 03:15:00 -0700 (PDT) Received: from otyshchenko.kyiv.epam.com (ll-22.209.223.85.sovam.net.ua. [85.223.209.22]) by smtp.gmail.com with ESMTPSA id x30sm6275717ljd.38.2019.04.08.03.14.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Apr 2019 03:15:00 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Mon, 8 Apr 2019 13:14:46 +0300 Message-Id: <1554718489-11318-3-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> References: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V3 2/5] xen/arm: drivers: scif: Extend driver to handle other interfaces X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko Extend driver to be able to handle other SCIF(X) compatible interfaces as well. These interfaces have lot in common, but mostly differ in offsets and bits for some registers. Introduce "port_params" array to keep interface specific things. The "data" field in struct dt_device_match is used for recognizing what interface is present on a target board. Please note, nothing has been technically changed for Renesas "Lager" and other supported boards (SCIF). Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Changes in v2: - Name a enum for describing interfaces this driver supports - Use local variable for "params" where appropriate - Use "data" field in struct dt_device_match instead of calling dt_device_is_compatible() - Don't check for "overrun_reg != status_reg" condition during initialization Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only reworks a driver - Drop "port_type" variable from scif_uart_init(), pass a pointer directly --- xen/drivers/char/scif-uart.c | 119 ++++++++++++++++++++++++++++------------ xen/include/asm-arm/scif-uart.h | 4 -- 2 files changed, 85 insertions(+), 38 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 465fb34..958f717 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -40,16 +40,51 @@ static struct scif_uart { char __iomem *regs; struct irqaction irqaction; struct vuart_info vuart; + const struct port_params *params; } scif_com = {0}; +enum port_types +{ + SCIF_PORT, + NR_PORTS, +}; + +struct port_params +{ + unsigned int status_reg; + unsigned int tx_fifo_reg; + unsigned int rx_fifo_reg; + unsigned int overrun_reg; + unsigned int overrun_mask; + unsigned int error_mask; + unsigned int irq_flags; + unsigned int fifo_size; +}; + +static const struct port_params port_params[NR_PORTS] = +{ + [SCIF_PORT] = + { + .status_reg = SCIF_SCFSR, + .tx_fifo_reg = SCIF_SCFTDR, + .rx_fifo_reg = SCIF_SCFRDR, + .overrun_reg = SCIF_SCLSR, + .overrun_mask = SCLSR_ORER, + .error_mask = SCFSR_PER | SCFSR_FER | SCFSR_BRK | SCFSR_ER, + .irq_flags = SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, + .fifo_size = 16, + }, +}; + static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) { struct serial_port *port = data; struct scif_uart *uart = port->uart; + const struct port_params *params = uart->params; uint16_t status, ctrl; ctrl = scif_readw(uart, SCIF_SCSCR); - status = scif_readw(uart, SCIF_SCFSR) & ~SCFSR_TEND; + status = scif_readw(uart, params->status_reg) & ~SCFSR_TEND; /* Ignore next flag if TX Interrupt is disabled */ if ( !(ctrl & SCSCR_TIE) ) status &= ~SCFSR_TDFE; @@ -65,13 +100,16 @@ static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) serial_rx_interrupt(port, regs); /* Error Interrupt */ - if ( status & SCIF_ERRORS ) - scif_writew(uart, SCIF_SCFSR, ~SCIF_ERRORS); - if ( scif_readw(uart, SCIF_SCLSR) & SCLSR_ORER ) - scif_writew(uart, SCIF_SCLSR, 0); + if ( status & params->error_mask ) + scif_writew(uart, params->status_reg, ~params->error_mask); + if ( params->overrun_reg != params->status_reg ) + { + if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) + scif_writew(uart, params->overrun_reg, ~params->overrun_mask); + } ctrl = scif_readw(uart, SCIF_SCSCR); - status = scif_readw(uart, SCIF_SCFSR) & ~SCFSR_TEND; + status = scif_readw(uart, params->status_reg) & ~SCFSR_TEND; /* Ignore next flag if TX Interrupt is disabled */ if ( !(ctrl & SCSCR_TIE) ) status &= ~SCFSR_TDFE; @@ -81,12 +119,13 @@ static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) static void __init scif_uart_init_preirq(struct serial_port *port) { struct scif_uart *uart = port->uart; + const struct port_params *params = uart->params; /* * Wait until last bit has been transmitted. This is needed for a smooth * transition when we come from early printk */ - while ( !(scif_readw(uart, SCIF_SCFSR) & SCFSR_TEND) ); + while ( !(scif_readw(uart, params->status_reg) & SCFSR_TEND) ); /* Disable TX/RX parts and all interrupts */ scif_writew(uart, SCIF_SCSCR, 0); @@ -95,10 +134,10 @@ static void __init scif_uart_init_preirq(struct serial_port *port) scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST); /* Clear all errors and flags */ - scif_readw(uart, SCIF_SCFSR); - scif_writew(uart, SCIF_SCFSR, 0); - scif_readw(uart, SCIF_SCLSR); - scif_writew(uart, SCIF_SCLSR, 0); + scif_readw(uart, params->status_reg); + scif_writew(uart, params->status_reg, 0); + scif_readw(uart, params->overrun_reg); + scif_writew(uart, params->overrun_reg, 0); /* Setup trigger level for TX/RX FIFOs */ scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11); @@ -111,6 +150,7 @@ static void __init scif_uart_init_preirq(struct serial_port *port) static void __init scif_uart_init_postirq(struct serial_port *port) { struct scif_uart *uart = port->uart; + const struct port_params *params = uart->params; int rc; uart->irqaction.handler = scif_uart_interrupt; @@ -122,14 +162,17 @@ static void __init scif_uart_init_postirq(struct serial_port *port) uart->irq); /* Clear all errors */ - if ( scif_readw(uart, SCIF_SCFSR) & SCIF_ERRORS ) - scif_writew(uart, SCIF_SCFSR, ~SCIF_ERRORS); - if ( scif_readw(uart, SCIF_SCLSR) & SCLSR_ORER ) - scif_writew(uart, SCIF_SCLSR, 0); + if ( scif_readw(uart, params->status_reg) & params->error_mask ) + scif_writew(uart, params->status_reg, ~params->error_mask); + if ( params->overrun_reg != params->status_reg ) + { + if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) + scif_writew(uart, params->overrun_reg, ~params->overrun_mask); + } /* Enable TX/RX and Error Interrupts */ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | - SCSCR_TIE | SCSCR_RIE | SCSCR_REIE); + params->irq_flags); } static void scif_uart_suspend(struct serial_port *port) @@ -145,43 +188,47 @@ static void scif_uart_resume(struct serial_port *port) static int scif_uart_tx_ready(struct serial_port *port) { struct scif_uart *uart = port->uart; + const struct port_params *params = uart->params; uint16_t cnt; /* Check for empty space in TX FIFO */ - if ( !(scif_readw(uart, SCIF_SCFSR) & SCFSR_TDFE) ) + if ( !(scif_readw(uart, params->status_reg) & SCFSR_TDFE) ) return 0; /* Check number of data bytes stored in TX FIFO */ cnt = scif_readw(uart, SCIF_SCFDR) >> 8; - ASSERT( cnt >= 0 && cnt <= SCIF_FIFO_MAX_SIZE ); + ASSERT( cnt >= 0 && cnt <= params->fifo_size ); - return (SCIF_FIFO_MAX_SIZE - cnt); + return (params->fifo_size - cnt); } static void scif_uart_putc(struct serial_port *port, char c) { struct scif_uart *uart = port->uart; + const struct port_params *params = uart->params; - scif_writeb(uart, SCIF_SCFTDR, c); + scif_writeb(uart, params->tx_fifo_reg, c); /* Clear required TX flags */ - scif_writew(uart, SCIF_SCFSR, scif_readw(uart, SCIF_SCFSR) & - ~(SCFSR_TEND | SCFSR_TDFE)); + scif_writew(uart, params->status_reg, + scif_readw(uart, params->status_reg) & + ~(SCFSR_TEND | SCFSR_TDFE)); } static int scif_uart_getc(struct serial_port *port, char *pc) { struct scif_uart *uart = port->uart; + const struct port_params *params = uart->params; /* Check for available data bytes in RX FIFO */ - if ( !(scif_readw(uart, SCIF_SCFSR) & (SCFSR_RDF | SCFSR_DR)) ) + if ( !(scif_readw(uart, params->status_reg) & (SCFSR_RDF | SCFSR_DR)) ) return 0; - *pc = scif_readb(uart, SCIF_SCFRDR); + *pc = scif_readb(uart, params->rx_fifo_reg); /* dummy read */ - scif_readw(uart, SCIF_SCFSR); + scif_readw(uart, params->status_reg); /* Clear required RX flags */ - scif_writew(uart, SCIF_SCFSR, ~(SCFSR_RDF | SCFSR_DR)); + scif_writew(uart, params->status_reg, ~(SCFSR_RDF | SCFSR_DR)); return 1; } @@ -229,9 +276,16 @@ static struct uart_driver __read_mostly scif_uart_driver = { .vuart_info = scif_vuart_info, }; +static const struct dt_device_match scif_uart_dt_match[] __initconst = +{ + { .compatible = "renesas,scif", .data = (void *)SCIF_PORT }, + { /* sentinel */ }, +}; + static int __init scif_uart_init(struct dt_device_node *dev, const void *data) { + const struct dt_device_match *match; const char *config = data; struct scif_uart *uart; int res; @@ -265,10 +319,13 @@ static int __init scif_uart_init(struct dt_device_node *dev, return -ENOMEM; } + match = dt_match_node(scif_uart_dt_match, dev); + uart->params = &port_params[(enum port_types)match->data]; + uart->vuart.base_addr = addr; uart->vuart.size = size; - uart->vuart.data_off = SCIF_SCFTDR; - uart->vuart.status_off = SCIF_SCFSR; + uart->vuart.data_off = uart->params->tx_fifo_reg; + uart->vuart.status_off = uart->params->status_reg; uart->vuart.status = SCFSR_TDFE; /* Register with generic serial driver */ @@ -279,12 +336,6 @@ static int __init scif_uart_init(struct dt_device_node *dev, return 0; } -static const struct dt_device_match scif_uart_dt_match[] __initconst = -{ - DT_MATCH_COMPATIBLE("renesas,scif"), - { /* sentinel */ }, -}; - DT_DEVICE_START(scif_uart, "SCIF UART", DEVICE_SERIAL) .dt_match = scif_uart_dt_match, .init = scif_uart_init, diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uart.h index 8137850..c343f2f 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -21,8 +21,6 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H -#define SCIF_FIFO_MAX_SIZE 16 - /* Register offsets */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ @@ -57,8 +55,6 @@ #define SCFSR_RDF (1 << 1) /* Receive FIFO Data Full */ #define SCFSR_DR (1 << 0) /* Receive Data Ready */ -#define SCIF_ERRORS (SCFSR_PER | SCFSR_FER | SCFSR_ER | SCFSR_BRK) - /* Line Status Register (SCLSR) */ #define SCLSR_TO (1 << 2) /* Timeout */ #define SCLSR_ORER (1 << 0) /* Overrun Error */ From patchwork Mon Apr 8 10:14:47 2019 Content-Type: text/plain; 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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id x30sm6275717ljd.38.2019.04.08.03.15.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Apr 2019 03:15:01 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Mon, 8 Apr 2019 13:14:47 +0300 Message-Id: <1554718489-11318-4-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> References: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V3 3/5] xen/arm: drivers: scif: Add support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko For the driver to be able to handle SCIFA interface as well, this patch just adds the following: - SCIFA related macros - New element in "port_params" array to keep SCIFA specific things - SCIFA compatible string This patch makes possible to use existing driver for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Changes in v3: - This patch is a result of splitting an initial patch "xen/arm: drivers: scif: Add support for SCIFA compatible UARTs" and only adds SCIFA support --- xen/drivers/char/scif-uart.c | 18 +++++++++++++++++- xen/include/asm-arm/scif-uart.h | 40 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 958f717..94cb230 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -1,7 +1,7 @@ /* * xen/drivers/char/scif-uart.c * - * Driver for SCIF (Serial communication interface with FIFO) + * Driver for SCIF(A) (Serial communication interface with FIFO (A)) * compatible UART. * * Oleksandr Tyshchenko @@ -46,6 +46,7 @@ static struct scif_uart { enum port_types { SCIF_PORT, + SCIFA_PORT, NR_PORTS, }; @@ -74,6 +75,20 @@ static const struct port_params port_params[NR_PORTS] = .irq_flags = SCSCR_RIE | SCSCR_TIE | SCSCR_REIE, .fifo_size = 16, }, + + [SCIFA_PORT] = + { + .status_reg = SCIFA_SCASSR, + .tx_fifo_reg = SCIFA_SCAFTDR, + .rx_fifo_reg = SCIFA_SCAFRDR, + .overrun_reg = SCIFA_SCASSR, + .overrun_mask = SCASSR_ORER, + .error_mask = SCASSR_PER | SCASSR_FER | SCASSR_BRK | SCASSR_ER | + SCASSR_ORER, + .irq_flags = SCASCR_RIE | SCASCR_TIE | SCASCR_DRIE | SCASCR_ERIE | + SCASCR_BRIE, + .fifo_size = 64, + }, }; static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) @@ -279,6 +294,7 @@ static struct uart_driver __read_mostly scif_uart_driver = { static const struct dt_device_match scif_uart_dt_match[] __initconst = { { .compatible = "renesas,scif", .data = (void *)SCIF_PORT }, + { .compatible = "renesas,scifa", .data = (void *)SCIFA_PORT }, { /* sentinel */ }, }; diff --git a/xen/include/asm-arm/scif-uart.h b/xen/include/asm-arm/scif-uart.h index c343f2f..bce3404 100644 --- a/xen/include/asm-arm/scif-uart.h +++ b/xen/include/asm-arm/scif-uart.h @@ -2,7 +2,7 @@ * xen/include/asm-arm/scif-uart.h * * Common constant definition between early printk and the UART driver - * for the SCIF compatible UART. + * for the SCIF(A) compatible UART. * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -21,7 +21,7 @@ #ifndef __ASM_ARM_SCIF_UART_H #define __ASM_ARM_SCIF_UART_H -/* Register offsets */ +/* Register offsets (SCIF) */ #define SCIF_SCSMR (0x00) /* Serial mode register */ #define SCIF_SCBRR (0x04) /* Bit rate register */ #define SCIF_SCSCR (0x08) /* Serial control register */ @@ -79,6 +79,42 @@ #define SCFCR_TTRG10 (SCFCR_TTRG1) #define SCFCR_TTRG11 (SCFCR_TTRG1 | SCFCR_TTRG0) +/* Register offsets (SCIFA) */ +#define SCIFA_SCASMR (0x00) /* Serial mode register */ +#define SCIFA_SCABRR (0x04) /* Bit rate register */ +#define SCIFA_SCASCR (0x08) /* Serial control register */ +#define SCIFA_SCATDSR (0x0C) /* Transmit data stop register */ +#define SCIFA_SCAFER (0x10) /* FIFO error count register */ +#define SCIFA_SCASSR (0x14) /* Serial status register */ +#define SCIFA_SCAFCR (0x18) /* FIFO control register */ +#define SCIFA_SCAFDR (0x1C) /* FIFO data count register */ +#define SCIFA_SCAFTDR (0x20) /* Transmit FIFO data register */ +#define SCIFA_SCAFRDR (0x24) /* Receive FIFO data register */ +#define SCIFA_SCAPCR (0x30) /* Serial port control register */ +#define SCIFA_SCAPDR (0x34) /* Serial port data register */ + +/* Serial Control Register (SCASCR) */ +#define SCASCR_ERIE (1 << 10) /* Receive Error Interrupt Enable */ +#define SCASCR_BRIE (1 << 9) /* Break Interrupt Enable */ +#define SCASCR_DRIE (1 << 8) /* Receive Data Ready Interrupt Enable */ +#define SCASCR_TIE (1 << 7) /* Transmit Interrupt Enable */ +#define SCASCR_RIE (1 << 6) /* Receive Interrupt Enable */ +#define SCASCR_TE (1 << 5) /* Transmit Enable */ +#define SCASCR_RE (1 << 4) /* Receive Enable */ +#define SCASCR_CKE0 (1 << 0) /* Clock Enable 0 */ + +/* Serial Status Register (SCASSR) */ +#define SCASSR_ORER (1 << 9) /* Overrun Error */ +#define SCASSR_TSF (1 << 8) /* Transmit Data Stop */ +#define SCASSR_ER (1 << 7) /* Receive Error */ +#define SCASSR_TEND (1 << 6) /* Transmission End */ +#define SCASSR_TDFE (1 << 5) /* Transmit FIFO Data Empty */ +#define SCASSR_BRK (1 << 4) /* Break Detect */ +#define SCASSR_FER (1 << 3) /* Framing Error */ +#define SCASSR_PER (1 << 2) /* Parity Error */ +#define SCASSR_RDF (1 << 1) /* Receive FIFO Data Full */ +#define SCASSR_DR (1 << 0) /* Receive Data Ready */ + #endif /* __ASM_ARM_SCIF_UART_H */ /* From patchwork Mon Apr 8 10:14:48 2019 Content-Type: text/plain; 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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id x30sm6275717ljd.38.2019.04.08.03.15.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Apr 2019 03:15:02 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Mon, 8 Apr 2019 13:14:48 +0300 Message-Id: <1554718489-11318-5-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> References: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V3 4/5] xen/arm: Extend SCIF early prink code to handle other interfaces X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko Extend early prink code to be able to handle other SCIF(X) compatible interfaces as well. These interfaces have lot in common, but mostly differ in offsets and bits for some registers. Introduce "EARLY_PRINTK_VERSION" config option to choose which interface version should be used (to properly apply register offsets). Please note, nothing has been technically changed for Renesas "Lager" and other supported boards (SCIF). The "EARLY_PRINTK_VERSION" option for that board should be empty: CONFIG_EARLY_PRINTK=scif,0xe6e60000 Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Changes in v3: - It was decided not to introduce new debug-scifa.inc for handling SCIFA interface, but to extend existing debug-scif.inc for handling both interfaces. This patch is a result of splitting an initial patch "xen/arm: Add SCIFA UART support for early printk" and only reworks a code --- xen/arch/arm/Rules.mk | 7 +++++++ xen/arch/arm/arm32/debug-scif.inc | 13 +++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index f264592..3d9a0ed 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -68,6 +68,13 @@ EARLY_PRINTK_INIT_UART := y EARLY_PRINTK_BAUD := $(word 3,$(EARLY_PRINTK_CFG)) endif endif +ifeq ($(EARLY_PRINTK_INC),scif) +ifneq ($(word 3,$(EARLY_PRINTK_CFG)),) +CFLAGS-y += -DEARLY_PRINTK_VERSION_$(word 3,$(EARLY_PRINTK_CFG)) +else +CFLAGS-y += -DEARLY_PRINTK_VERSION_NONE +endif +endif ifneq ($(EARLY_PRINTK_INC),) EARLY_PRINTK := y diff --git a/xen/arch/arm/arm32/debug-scif.inc b/xen/arch/arm/arm32/debug-scif.inc index 143f05d..a8d2eae 100644 --- a/xen/arch/arm/arm32/debug-scif.inc +++ b/xen/arch/arm/arm32/debug-scif.inc @@ -19,6 +19,11 @@ #include +#ifdef EARLY_PRINTK_VERSION_NONE +#define STATUS_REG SCIF_SCFSR +#define TX_FIFO_REG SCIF_SCFTDR +#endif + /* * SCIF UART wait UART to be ready to transmit * rb: register which contains the UART base address @@ -26,7 +31,7 @@ */ .macro early_uart_ready rb rc 1: - ldrh \rc, [\rb, #SCIF_SCFSR] /* <- SCFSR (status register) */ + ldrh \rc, [\rb, #STATUS_REG] /* Read status register */ tst \rc, #SCFSR_TDFE /* Check TDFE bit */ beq 1b /* Wait for the UART to be ready */ .endm @@ -37,10 +42,10 @@ * rt: register which contains the character to transmit */ .macro early_uart_transmit rb rt - strb \rt, [\rb, #SCIF_SCFTDR] /* -> SCFTDR (data register) */ - ldrh \rt, [\rb, #SCIF_SCFSR] /* <- SCFSR (status register) */ + strb \rt, [\rb, #TX_FIFO_REG] /* Write data register */ + ldrh \rt, [\rb, #STATUS_REG] /* Read status register */ and \rt, \rt, #(~(SCFSR_TEND | SCFSR_TDFE)) /* Clear TEND and TDFE bits */ - strh \rt, [\rb, #SCIF_SCFSR] /* -> SCFSR (status register) */ + strh \rt, [\rb, #STATUS_REG] /* Write status register */ .endm /* From patchwork Mon Apr 8 10:14:49 2019 Content-Type: text/plain; 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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id x30sm6275717ljd.38.2019.04.08.03.15.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Apr 2019 03:15:03 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Date: Mon, 8 Apr 2019 13:14:49 +0300 Message-Id: <1554718489-11318-6-git-send-email-olekstysh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> References: <1554718489-11318-1-git-send-email-olekstysh@gmail.com> Subject: [Xen-devel] [PATCH V3 5/5] xen/arm: Add early printk support for SCIFA compatible UARTs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr Tyshchenko , julien.grall@arm.com, sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Oleksandr Tyshchenko This patch makes possible to use existing early prink code for Renesas "Stout" board based on R-Car H2 SoC (SCIFA). The "EARLY_PRINTK_VERSION" for that board should be 'A': CONFIG_EARLY_PRINTK=scif,0xe6c40000,A Signed-off-by: Oleksandr Tyshchenko CC: Julien Grall --- Changes in v3: - It was decided not to introduce new debug-scifa.inc for handling SCIFA interface, but to extend existing debug-scif.inc for handling both interfaces. This patch is a result of splitting an initial patch "xen/arm: Add SCIFA UART support for early printk" and only adds a support. --- xen/arch/arm/arm32/debug-scif.inc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/arm32/debug-scif.inc b/xen/arch/arm/arm32/debug-scif.inc index a8d2eae..94a18ea 100644 --- a/xen/arch/arm/arm32/debug-scif.inc +++ b/xen/arch/arm/arm32/debug-scif.inc @@ -1,7 +1,7 @@ /* * xen/arch/arm/arm32/debug-scif.inc * - * SCIF specific debug code + * SCIF(A) specific debug code * * Oleksandr Tyshchenko * Copyright (C) 2014, Globallogic. @@ -22,10 +22,13 @@ #ifdef EARLY_PRINTK_VERSION_NONE #define STATUS_REG SCIF_SCFSR #define TX_FIFO_REG SCIF_SCFTDR +#elif EARLY_PRINTK_VERSION_A +#define STATUS_REG SCIFA_SCASSR +#define TX_FIFO_REG SCIFA_SCAFTDR #endif /* - * SCIF UART wait UART to be ready to transmit + * SCIF(A) UART wait UART to be ready to transmit * rb: register which contains the UART base address * rc: scratch register */ @@ -37,7 +40,7 @@ .endm /* - * SCIF UART transmit character + * SCIF(A) UART transmit character * rb: register which contains the UART base address * rt: register which contains the character to transmit */