From patchwork Tue Apr 9 20:47:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 10892401 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B4FC17E6 for ; Tue, 9 Apr 2019 20:47:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA5F5288A9 for ; Tue, 9 Apr 2019 20:47:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DE02B2894C; Tue, 9 Apr 2019 20:47:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BA6E288A9 for ; Tue, 9 Apr 2019 20:47:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726636AbfDIUra (ORCPT ); Tue, 9 Apr 2019 16:47:30 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:39685 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726612AbfDIUr3 (ORCPT ); Tue, 9 Apr 2019 16:47:29 -0400 Received: by mail-pl1-f194.google.com with SMTP id a96so5443952pla.6 for ; Tue, 09 Apr 2019 13:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hQtEpFr/2QLJJRhgfs3xG1fw3zbFUfL+gsBwRn2FRiU=; b=Vxr3Ka6p31s9x4dd+PrU3fntx+g16qjSfCMXIEspakxskDnqurocM5WnuYakx6KOV0 yHe3K1tHjILdPNGwuQDwV2qP5psDPm/RbPKZdEB2FuDsoUwanlWkd9AbqgpLb/HT0Fqr KLLckLDp8uyS4EFkJpK6x/83eswdMi3p+4ZWA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hQtEpFr/2QLJJRhgfs3xG1fw3zbFUfL+gsBwRn2FRiU=; b=O5UYoQscvLJZc75gNRS96k3wC8kfNgIVDptKyz24x02hqnPnIZ1McWfpjg2fjH7FSY lcATrmNJYTszahMXe2rABSopcI4az3AWUy+At+2T0pkD9CDyAS57/aIDTZde+mpM8Vyt 9XJeDyyyBS+hrGV86BX4hCCHDFP81ChKZhMycrgFH1raE4p5GjNU7ZQM+z59Vp/PMGhH UjX8lxk8PtgNwhF29V64abfvv592TQfYjllHhTl+fN5akInmjrUhl4H1R82LdylyNHWO 0BZRdSYyjX+UxRoIufyWR8EntEEZRnHqvGhe5l6Oy3AhGPa01GJPwS8FsQBRtlHgRjHW CaCA== X-Gm-Message-State: APjAAAX42NuNuzjMZ+R7Ewb0tzBdH7volv6VUXXOlQRe+KeL8VQTHice uYrGuFy/v1codXjzAYrsKsLO+w== X-Google-Smtp-Source: APXvYqyuMD3gSme+CuuouGXSlNmkP4JX+ynXAbAEWa8G9WeOBvo3pVFWxQjDCZTk5zyU9r4fD8SvMg== X-Received: by 2002:a17:902:1105:: with SMTP id d5mr15107160pla.311.1554842848669; Tue, 09 Apr 2019 13:47:28 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id x28sm35014016pgl.38.2019.04.09.13.47.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Apr 2019 13:47:28 -0700 (PDT) From: Douglas Anderson To: Heiko Stuebner Cc: Michael Turquette , Stephen Boyd , Caesar Wang , linux-rockchip@lists.infradead.org, mka@chromium.org, ryandcase@chromium.org, Elaine Zhang , linux-clk@vger.kernel.org, Douglas Anderson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] Revert "clk: rockchip: mark noc and some special clk as critical on rk3288" Date: Tue, 9 Apr 2019 13:47:05 -0700 Message-Id: <20190409204707.150347-2-dianders@chromium.org> X-Mailer: git-send-email 2.21.0.392.gf8f6787159e-goog In-Reply-To: <20190409204707.150347-1-dianders@chromium.org> References: <20190409204707.150347-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit 55bb6a633c33caf68ab470907ecf945289cb733d. The clocks that were enabled by that patch are pretty questionable. Specifically looking at what has been shipping on rk3288-veyron Chromebooks almost all of these clocks are safely turned off and cause no apparent problems. If some boards need these clocks turned on for some reason then it seems like we should figure out how to do that at a board level. NOTE: turning these clocks off doesn't seem to do a whole lot in terms of power savings (checking the power on the logic rail). It appears to save maybe 1-2mW. ...but still it seems like we should turn the clocks off if they aren't needed. Digging into the clocks here to describe why they shouldn't need to be left on: atclk: No documentation about this clock other than that it goes to the CPU. CPU functions fine without it on. jtag: Presumably this clock is only needed if you're debugging with JTAG. It doesn't seem like it makes sense to waste power for every rk3288 user. Perhaps this could be turned on with a CONFIG option? pclk_dbg, pclk_core_niu: On veyron Chromebooks we turn these two clocks on only during kernel panics in order to access some coresight registers. Since nothing in the upstream kernel does this we should be able to leave them off safely. hsicphy12m_xin12m: There is no indication of why this clock would need to be turned on for boards that don't use HSIC. pclk_ddrupctl[0-1], pclk_publ0[0-1]: On veyron Chromebooks we turn these 4 clocks on only when doing DDR transitions and they are off otherwise. I see no reason why they'd need to be on in the upstream kernel which doesn't support DDRFreq. pmu_hclk_otg0: A "chip design defect" is mentioned in the original patch but no details. This clock has always been gated in shipping veyron Chromebooks so presumably this chip defect doesn't affect all boards. Signed-off-by: Douglas Anderson --- drivers/clk/rockchip/clk-rk3288.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 5a67b7869960..06287810474e 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -313,13 +313,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 6, GFLAGS), - COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(0, "atclk", "armclk", 0, RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 7, GFLAGS), COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 8, GFLAGS), - GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, + GATE(0, "pclk_dbg", "pclk_dbg_pre", 0, RK3288_CLKGATE_CON(12), 9, GFLAGS), GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(12), 10, GFLAGS), @@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", RK3288_CLKSEL_CON(22), 7, IFLAGS), - GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, + GATE(0, "jtag", "ext_jtag", 0, RK3288_CLKGATE_CON(4), 14, GFLAGS), COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0, @@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, RK3288_CLKGATE_CON(3), 6, GFLAGS), - GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED, + GATE(0, "hsicphy12m_xin12m", "xin12m", 0, RK3288_CLKGATE_CON(13), 9, GFLAGS), DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0, RK3288_CLKSEL_CON(11), 8, 6, DFLAGS), @@ -837,12 +837,6 @@ static const char *const rk3288_critical_clocks[] __initconst = { "pclk_alive_niu", "pclk_pd_pmu", "pclk_pmu_niu", - "pclk_core_niu", - "pclk_ddrupctl0", - "pclk_publ0", - "pclk_ddrupctl1", - "pclk_publ1", - "pmu_hclk_otg0", }; static void __iomem *rk3288_cru_base; From patchwork Tue Apr 9 20:47:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 10892403 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C3E813B5 for ; Tue, 9 Apr 2019 20:47:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0811428935 for ; Tue, 9 Apr 2019 20:47:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F0CF22894E; Tue, 9 Apr 2019 20:47:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9112428935 for ; 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However, most rk3288-based boards don't specify the PWM regulator in their device tree. We'll deal with that by making it critical. NOTE: it's important to make it critical and not just IGNORE_UNUSED because all PWMs in the system share the same clock. We don't want another PWM user to turn the clock on and off and kill the logic rail. This change is in preparation for actually having the PWMs in the rk3288 device tree actually point to the proper PWM clock. Up until now they've all pointed to the clock for the old IP block and they've all worked due to the fact that rkpwm was IGNORE_UNUSED and that the clock rates for both clocks were the same. Signed-off-by: Douglas Anderson --- drivers/clk/rockchip/clk-rk3288.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 06287810474e..c3321eade23e 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -697,7 +697,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), - GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS), /* ddrctrl [DDR Controller PHY clock] gates */ GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS), @@ -837,6 +837,7 @@ static const char *const rk3288_critical_clocks[] __initconst = { "pclk_alive_niu", "pclk_pd_pmu", "pclk_pmu_niu", + "pclk_rkpwm", }; static void __iomem *rk3288_cru_base; From patchwork Tue Apr 9 20:47:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 10892409 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 01D3F13B5 for ; Tue, 9 Apr 2019 20:47:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E295928935 for ; Tue, 9 Apr 2019 20:47:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D66B52894E; Tue, 9 Apr 2019 20:47:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 776E928935 for ; Tue, 9 Apr 2019 20:47:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726633AbfDIUrp (ORCPT ); Tue, 9 Apr 2019 16:47:45 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:46197 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726655AbfDIUrb (ORCPT ); Tue, 9 Apr 2019 16:47:31 -0400 Received: by mail-pf1-f196.google.com with SMTP id 9so10424844pfj.13 for ; Tue, 09 Apr 2019 13:47:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qGw/m7HHCKFTJMNBAQqfOMUpuzIj1MTny7DgtGjU83w=; b=SOvXYeUjqflbpCsSB6HQYFOY66k0ViRsIFWTvrG7DM8QKLlYBuV7/nmqu9ZI2/KBrD CxniiwWrpWcQrJTAlwvV7yhkD8Dpi/w4XIKHdfHWklbA8OWMz2rMFIiuLphm/XMDrM5I AgNXnhgsH9gjmzxjI46kbprt0DrALCvz7jQU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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Signed-off-by: Caesar Wang Signed-off-by: Douglas Anderson --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 8bce2fc49b24..efdfa3737561 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -677,7 +677,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -688,7 +688,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -699,7 +699,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -710,7 +710,7 @@ #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; };