From patchwork Wed Apr 10 12:42:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893809 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21C051390 for ; Wed, 10 Apr 2019 12:42:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A0BD26B39 for ; Wed, 10 Apr 2019 12:42:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2107289B6; Wed, 10 Apr 2019 12:42:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FCAC26B39 for ; Wed, 10 Apr 2019 12:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732027AbfDJMmu (ORCPT ); Wed, 10 Apr 2019 08:42:50 -0400 Received: from kozue.soulik.info ([108.61.200.231]:43948 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732026AbfDJMmt (ORCPT ); Wed, 10 Apr 2019 08:42:49 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id 4E2481014EA; Wed, 10 Apr 2019 21:43:36 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: Randy Li , hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 2/9] rockchip: mpp: rkvdec: rbsp Date: Wed, 10 Apr 2019 20:42:19 +0800 Message-Id: <20190410124226.8612-3-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Randy Li It is a bit writer. Signed-off-by: Randy Li --- drivers/staging/rockchip-mpp/rkvdec/rbsp.c | 96 ++++++++++++++++++++++ drivers/staging/rockchip-mpp/rkvdec/rbsp.h | 30 +++++++ 2 files changed, 126 insertions(+) create mode 100644 drivers/staging/rockchip-mpp/rkvdec/rbsp.c create mode 100644 drivers/staging/rockchip-mpp/rkvdec/rbsp.h diff --git a/drivers/staging/rockchip-mpp/rkvdec/rbsp.c b/drivers/staging/rockchip-mpp/rkvdec/rbsp.c new file mode 100644 index 000000000000..3fbc50e9bca1 --- /dev/null +++ b/drivers/staging/rockchip-mpp/rkvdec/rbsp.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2012 Vista Silicon S.L. + * Copyright (C) 2019 Randy Li + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#include "rbsp.h" + +int rbsp_init(struct rbsp *rbsp, void *buf, int size, int bit_pos) +{ + if (!buf) + return -EINVAL; + if (DIV_ROUND_UP(bit_pos, 32) >= size) + return -EINVAL; + + rbsp->buf = buf; + rbsp->size = size >> 2; + rbsp->pos = bit_pos; + + return 0; +} + +static inline int rbsp_read_bit(struct rbsp *rbsp) +{ + int shift = rbsp->pos % 32; + int ofs = rbsp->pos++ / 32; + + if (ofs >= rbsp->size) + return -EINVAL; + + return (rbsp->buf[ofs] >> shift) & 1; +} + +static inline int rbsp_write_bit(struct rbsp *rbsp, int bit) +{ + int shift = rbsp->pos % 32; + int ofs = rbsp->pos++ / 32; + + if (ofs >= rbsp->size) + return -EINVAL; + + rbsp->buf[ofs] &= ~(1 << shift); + rbsp->buf[ofs] |= bit << shift; + + return 0; +} + +int rbsp_write_bits(struct rbsp *rbsp, int num, int value) +{ + int shift = rbsp->pos % 32; + int ofs = rbsp->pos / 32; + + if (ofs >= rbsp->size) + return -EINVAL; + + if (num + shift >= 32) { + u32 lbits = 32 - shift; + u32 hbits = num + shift - 32; + + rbsp->buf[ofs] &= ~(((1 << lbits) - 1) << shift); + rbsp->buf[ofs] |= value << shift; + + value >>= (32 - shift); + rbsp->buf[ofs + 1] &= ~(((1 << hbits) - 1)); + rbsp->buf[ofs + 1] |= value; + } else { + rbsp->buf[ofs] &= ~(((1 << num) - 1) << shift); + rbsp->buf[ofs] |= value << shift; + } + + rbsp->pos += num; + + return 0; +} + +int rbsp_write_flag(struct rbsp *rbsp, int value) +{ + if (value) + return rbsp_write_bit(rbsp, BIT(0)); + else + return rbsp_write_bit(rbsp, 0); +} diff --git a/drivers/staging/rockchip-mpp/rkvdec/rbsp.h b/drivers/staging/rockchip-mpp/rkvdec/rbsp.h new file mode 100644 index 000000000000..d87c582bfd41 --- /dev/null +++ b/drivers/staging/rockchip-mpp/rkvdec/rbsp.h @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2012 Vista Silicon S.L. + * Copyright (C) 2019 Randy Li + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _RBSP_H_ +#define _RBSP_H_ + +struct rbsp { + u32 *buf; + int size; + int pos; +}; + +int rbsp_init(struct rbsp *rbsp, void *buf, int size, int bit_pos); +int rbsp_write_flag(struct rbsp *rbsp, int bit); +int rbsp_write_bits(struct rbsp *rbsp, int num, int value); + +#endif From patchwork Wed Apr 10 12:42:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 098DD1515 for ; Wed, 10 Apr 2019 12:43:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E603A26B39 for ; Wed, 10 Apr 2019 12:43:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA145289B6; Wed, 10 Apr 2019 12:43:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F091B26B39 for ; Wed, 10 Apr 2019 12:42:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732033AbfDJMm7 (ORCPT ); Wed, 10 Apr 2019 08:42:59 -0400 Received: from kozue.soulik.info ([108.61.200.231]:43962 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732026AbfDJMm7 (ORCPT ); Wed, 10 Apr 2019 08:42:59 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id C4F861014EF; Wed, 10 Apr 2019 21:43:38 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: Randy Li , hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 3/9] [WIP]: rockchip: mpp: HEVC decoder ctrl data Date: Wed, 10 Apr 2019 20:42:20 +0800 Message-Id: <20190410124226.8612-4-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Randy Li Not done yet, not enough data. Signed-off-by: Randy Li --- drivers/staging/rockchip-mpp/Makefile | 4 +- .../staging/rockchip-mpp/rkvdec/hevc-data.c | 208 ++++++++++++++++++ .../staging/rockchip-mpp/rkvdec/hevc-data.h | 27 +++ drivers/staging/rockchip-mpp/rkvdec/hevc.c | 2 + 4 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/rockchip-mpp/rkvdec/hevc-data.c create mode 100644 drivers/staging/rockchip-mpp/rkvdec/hevc-data.h diff --git a/drivers/staging/rockchip-mpp/Makefile b/drivers/staging/rockchip-mpp/Makefile index 9722b0059563..8da33fa5142d 100644 --- a/drivers/staging/rockchip-mpp/Makefile +++ b/drivers/staging/rockchip-mpp/Makefile @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 rk-mpp-service-objs := mpp_service.o rk-mpp-device-objs := mpp_dev_common.o -rk-mpp-vdec-objs := mpp_dev_rkvdec.o rkvdec/hevc.o rkvdec/avc.o +rk-mpp-vdec-objs := mpp_dev_rkvdec.o +rk-mpp-vdec-objs += rkvdec/avc.o +rk-mpp-vdec-objs += rkvdec/hevc.o rkvdec/hevc-data.o rkvdec/rbsp.o rk-mpp-vdpu2-objs := mpp_dev_vdpu2.o vdpu2/mpeg2.o obj-$(CONFIG_ROCKCHIP_MPP_SERVICE) += rk-mpp-service.o diff --git a/drivers/staging/rockchip-mpp/rkvdec/hevc-data.c b/drivers/staging/rockchip-mpp/rkvdec/hevc-data.c new file mode 100644 index 000000000000..26694a2f46c5 --- /dev/null +++ b/drivers/staging/rockchip-mpp/rkvdec/hevc-data.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Randy Li, + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "hevc-data.h" + +/* 7.3.2.2.1 General sequence parameter set RBSP syntax */ +int rkvdec_hevc_write_sps(struct rbsp *rbsp, + const struct v4l2_ctrl_hevc_sps *sps) +{ + /* TODO: sps_video_parameter_set_id */ + rbsp_write_bits(rbsp, 4, 0); + /* TODO: sps_seq_parameter_set_id */ + rbsp_write_bits(rbsp, 4, 0); + /* chroma_format_idc */ + rbsp_write_bits(rbsp, 2, sps->chroma_format_idc); + rbsp_write_bits(rbsp, 13, sps->pic_width_in_luma_samples); + rbsp_write_bits(rbsp, 13, sps->pic_height_in_luma_samples); + /* bit_depth_luma */ + rbsp_write_bits(rbsp, 4, sps->bit_depth_luma_minus8 + 8); + rbsp_write_bits(rbsp, 4, sps->bit_depth_chroma_minus8 + 8); + /* log2_max_pic_order_cnt_lsb */ + rbsp_write_bits(rbsp, 5, sps->log2_max_pic_order_cnt_lsb_minus4 + 4); + /* FIXME it is 3 bits in document */ + rbsp_write_bits(rbsp, 2, sps->log2_diff_max_min_luma_coding_block_size); + /* log2_min_luma_coding_block_size */ + rbsp_write_bits(rbsp, 3, + sps->log2_min_luma_coding_block_size_minus3 + 3); + /* log2_min_transform_block_size */ + rbsp_write_bits(rbsp, 3, + sps->log2_min_luma_transform_block_size_minus2 + 2); + rbsp_write_bits(rbsp, 2, + sps->log2_diff_max_min_luma_transform_block_size); + rbsp_write_bits(rbsp, 3, sps->max_transform_hierarchy_depth_inter); + rbsp_write_bits(rbsp, 3, sps->max_transform_hierarchy_depth_intra); + + rbsp_write_flag(rbsp, sps->scaling_list_enabled_flag); + rbsp_write_flag(rbsp, sps->amp_enabled_flag); + rbsp_write_flag(rbsp, sps->sample_adaptive_offset_enabled_flag); + rbsp_write_flag(rbsp, sps->pcm_enabled_flag); + + /* pcm_sample_bit_depth_luma */ + rbsp_write_bits(rbsp, 4, sps->pcm_sample_bit_depth_luma_minus1 + 1); + /* pcm_sample_bit_depth_chroma */ + rbsp_write_bits(rbsp, 4, sps->pcm_sample_bit_depth_chroma_minus1 + 1); + rbsp_write_flag(rbsp, sps->pcm_loop_filter_disabled_flag); + + rbsp_write_bits(rbsp, 3, + sps->log2_diff_max_min_pcm_luma_coding_block_size); + /* log2_min_pcm_luma_coding_block_size */ + rbsp_write_bits(rbsp, 3, + sps->log2_min_pcm_luma_coding_block_size_minus3 + 3); + rbsp_write_bits(rbsp, 7, sps->num_short_term_ref_pic_sets); + rbsp_write_flag(rbsp, sps->long_term_ref_pics_present_flag); + rbsp_write_bits(rbsp, 6, sps->num_long_term_ref_pics_sps); + rbsp_write_flag(rbsp, sps->sps_temporal_mvp_enabled_flag); + rbsp_write_flag(rbsp, sps->strong_intra_smoothing_enabled_flag); + /* Above is 100 bits total */ +#if 0 + /* transform_skip_rotation_enabled_flag to intra_smoothing_disabled_flag */ + rbsp_write_bits(rbsp, 7, 0); + /* sps_max_dec_pic_buffering_minus1 */ + rbsp_write_bits(rbsp, 4, sps->sps_max_dec_pic_buffering_minus1); + rbsp_write_flag(rbsp, sps->separate_colour_plane_flag); + /* TODO: high_precision_offsets_enabled */ + rbsp_write_flag(rbsp, 0); + /* TODO: persistent_rice_adaptation_enabled_flag */ + rbsp_write_flag(rbsp, 0); + /* reserved */ + rbsp_write_bits(rbsp, 14, 0xffffffff); +#else + rbsp_write_bits(rbsp, 7, 0); + /* padding */ + rbsp_write_bits(rbsp, 21, 0xffffffff); +#endif + + return 0; +} + +int rkvdec_hevc_write_pps(struct rbsp *rbsp, + const struct v4l2_ctrl_hevc_sps *sps, + const struct v4l2_ctrl_hevc_pps *pps, + const struct v4l2_ctrl_hevc_slice_params *slice_params) +{ + + u32 min_cb_log2_size_y, ctb_log2_size_y, log2_min_cu_qp_delta_size; + u16 column_width[20] = { 0, }; + u16 row_height[22] = { 0, }; + u8 i; + + min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; + ctb_log2_size_y = min_cb_log2_size_y + + sps->log2_diff_max_min_luma_coding_block_size; + + log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; + + /* pps_pic_parameter_set_id */ + rbsp_write_bits(rbsp, 6, 0); + /* pps_seq_parameter_set_id */ + rbsp_write_bits(rbsp, 4, 0); + /* dependent_slice_segments_enabled_flag */ + rbsp_write_flag(rbsp, pps->dependent_slice_segment_flag); + rbsp_write_flag(rbsp, pps->output_flag_present_flag); + /* FIXME it is 3 bits in document */ + rbsp_write_bits(rbsp, 13, pps->num_extra_slice_header_bits); + /* sign_data_hiding_flag */ + rbsp_write_flag(rbsp, pps->sign_data_hiding_enabled_flag); + rbsp_write_flag(rbsp, pps->cabac_init_present_flag); + /* FIXME: from slice params ? */ + rbsp_write_bits(rbsp, 4, slice_params->num_ref_idx_l0_active_minus1 + 1); + rbsp_write_bits(rbsp, 4, slice_params->num_ref_idx_l1_active_minus1 + 1); + /* FIXME it is 6 bits in document init_qp_minus26 */ + rbsp_write_bits(rbsp, 7, pps->init_qp_minus26); + rbsp_write_flag(rbsp, pps->constrained_intra_pred_flag); + rbsp_write_flag(rbsp, pps->transform_skip_enabled_flag); + rbsp_write_flag(rbsp, pps->cu_qp_delta_enabled_flag); + /* Log2MinCuQpDeltaSize */ + rbsp_write_bits(rbsp, 3, log2_min_cu_qp_delta_size); + rbsp_write_bits(rbsp, 5, pps->pps_cb_qp_offset); + rbsp_write_bits(rbsp, 5, pps->pps_cr_qp_offset); + rbsp_write_flag(rbsp, pps->pps_slice_chroma_qp_offsets_present_flag); + rbsp_write_flag(rbsp, pps->weighted_pred_flag); + rbsp_write_flag(rbsp, pps->weighted_bipred_flag); + rbsp_write_flag(rbsp, pps->transquant_bypass_enabled_flag); + rbsp_write_flag(rbsp, pps->tiles_enabled_flag); + rbsp_write_flag(rbsp, pps->entropy_coding_sync_enabled_flag); + rbsp_write_flag(rbsp, pps->pps_loop_filter_across_slices_enabled_flag); + rbsp_write_flag(rbsp, pps->loop_filter_across_tiles_enabled_flag); + rbsp_write_flag(rbsp, pps->deblocking_filter_override_enabled_flag); + /* pps_deblocking_filter_disabled_flag */ + rbsp_write_flag(rbsp, pps->pps_disable_deblocking_filter_flag); + rbsp_write_bits(rbsp, 4, pps->pps_beta_offset_div2); + rbsp_write_bits(rbsp, 4, pps->pps_tc_offset_div2); + rbsp_write_flag(rbsp, pps->lists_modification_present_flag); + rbsp_write_bits(rbsp, 3, pps->log2_parallel_merge_level_minus2 + 2); + rbsp_write_flag(rbsp, pps->slice_segment_header_extension_present_flag); + /* reserved, log2_transform_skip_max_size_minus2 */ + rbsp_write_bits(rbsp, 3, 0); + /* num_tile_columns */ + rbsp_write_bits(rbsp, 5, pps->num_tile_columns_minus1 + 1); + /* num_tile_rows */ + rbsp_write_bits(rbsp, 5, pps->num_tile_rows_minus1 + 1); + /* ? */ + rbsp_write_bits(rbsp, 3, 2); + /* align 30 ? */ + rbsp_write_bits(rbsp, 32, 0xffffffff); + + /* TODO: support tile video */ + column_width[0] = 0; + row_height[0] = 0; + + for (i = 0; i < 20; i++) { + if (column_width[i]) + column_width[i]--; + rbsp_write_bits(rbsp, column_width[i], 8); + } + for (i = 0; i < 22; i++) { + if (row_height[i]) + row_height[i]--; + rbsp_write_bits(rbsp, row_height[i], 8); + } + + /* TODO: scaleing_address */ + + return 0; +} + +int rkvdec_hevc_write_soft_rps(struct rbsp *rbsp, + const struct v4l2_ctrl_hevc_slice_params *slice_params) +{ + int i; + + for (i = 0; i < 15; i++) { + /* FIXME: is long term */ + rbsp_write_flag(rbsp, 0); + rbsp_write_bits(rbsp, 4, slice_params->ref_idx_l0[i]); + } + + for (i = 0; i < 15; i++) { + /* FIXME: is long term */ + rbsp_write_flag(rbsp, 0); + rbsp_write_bits(rbsp, 4, slice_params->ref_idx_l1[i]); + } + /* TODO: lowdelay_flag */ + rbsp_write_flag(rbsp, 1); + + /* TODO: Rps_bit_offset_include_lt */ + rbsp_write_bits(rbsp, 10, 0); + rbsp_write_bits(rbsp, 9, 0); +} + +/* 7.3.7 Short-term reference picture set syntax */ +int rkvdec_hevc_write_rps(struct rbsp *rbsp, + const struct v4l2_ctrl_hevc_pps *pps) +{ + +} diff --git a/drivers/staging/rockchip-mpp/rkvdec/hevc-data.h b/drivers/staging/rockchip-mpp/rkvdec/hevc-data.h new file mode 100644 index 000000000000..6b94cd41d377 --- /dev/null +++ b/drivers/staging/rockchip-mpp/rkvdec/hevc-data.h @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Randy Li, + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include + +#include "rbsp.h" + +int rkvdec_hevc_write_sps(struct rbsp *rbsp, + const struct v4l2_ctrl_hevc_sps *sps); + +int rkvdec_hevc_write_rps(struct rbsp *rbsp, + const struct v4l2_ctrl_hevc_pps *pps); diff --git a/drivers/staging/rockchip-mpp/rkvdec/hevc.c b/drivers/staging/rockchip-mpp/rkvdec/hevc.c index 78f150000128..6f74ce45533a 100644 --- a/drivers/staging/rockchip-mpp/rkvdec/hevc.c +++ b/drivers/staging/rockchip-mpp/rkvdec/hevc.c @@ -25,6 +25,8 @@ #include "hal.h" #include "regs.h" +#include "hevc-data.h" + static void init_hw_cfg(struct rkvdec_regs *p_regs) { p_regs->sw_interrupt.dec_e = 1; From patchwork Wed Apr 10 12:42:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7363F1515 for ; Wed, 10 Apr 2019 12:43:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B96F26B39 for ; Wed, 10 Apr 2019 12:43:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4F9D1289B6; Wed, 10 Apr 2019 12:43:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E9E0426B39 for ; Wed, 10 Apr 2019 12:43:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732034AbfDJMnB (ORCPT ); Wed, 10 Apr 2019 08:43:01 -0400 Received: from kozue.soulik.info ([108.61.200.231]:43986 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732028AbfDJMnA (ORCPT ); Wed, 10 Apr 2019 08:43:00 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id 4C5791014EC; Wed, 10 Apr 2019 21:43:46 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: ayaka , randy.li@rock-chips.com, hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 4/9] [WIP]: rockchip: mpp: H.264 decoder ctrl data Date: Wed, 10 Apr 2019 20:42:21 +0800 Message-Id: <20190410124226.8612-5-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I really don't want to do this. Signed-off-by: Randy Li Signed-off-by: ayaka --- drivers/staging/rockchip-mpp/Makefile | 2 +- drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c | 8 +- .../staging/rockchip-mpp/rkvdec/avc-data.c | 239 ++++++++++++++++++ .../staging/rockchip-mpp/rkvdec/avc-data.h | 40 +++ drivers/staging/rockchip-mpp/rkvdec/avc.c | 71 +++++- drivers/staging/rockchip-mpp/vdpu2/avc.c | 165 ++++++++++++ 6 files changed, 514 insertions(+), 11 deletions(-) create mode 100644 drivers/staging/rockchip-mpp/rkvdec/avc-data.c create mode 100644 drivers/staging/rockchip-mpp/rkvdec/avc-data.h create mode 100644 drivers/staging/rockchip-mpp/vdpu2/avc.c diff --git a/drivers/staging/rockchip-mpp/Makefile b/drivers/staging/rockchip-mpp/Makefile index 8da33fa5142d..e2c2bf297812 100644 --- a/drivers/staging/rockchip-mpp/Makefile +++ b/drivers/staging/rockchip-mpp/Makefile @@ -2,7 +2,7 @@ rk-mpp-service-objs := mpp_service.o rk-mpp-device-objs := mpp_dev_common.o rk-mpp-vdec-objs := mpp_dev_rkvdec.o -rk-mpp-vdec-objs += rkvdec/avc.o +rk-mpp-vdec-objs += rkvdec/avc.o rkvdec/avc-data.o rk-mpp-vdec-objs += rkvdec/hevc.o rkvdec/hevc-data.o rkvdec/rbsp.o rk-mpp-vdpu2-objs := mpp_dev_vdpu2.o vdpu2/mpeg2.o diff --git a/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c b/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c index 756821dbf829..97abfdfc344f 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c +++ b/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c @@ -284,13 +284,15 @@ static int rkvdec_s_fmt_vid_cap_mplane(struct file *filp, void *priv, pix_mp->plane_fmt[1].bytesperline * ALIGN(pix_mp->height, 8); #else - /* TODO: HEVC only request the height is aligned with 8 */ + /* + * TODO: H.264 would use 16 alignment while the resolution is under HD, + * HEVC only request the height is aligned with 8 + */ pix_mp->plane_fmt[0].sizeimage = pix_mp->plane_fmt[0].bytesperline * ALIGN(pix_mp->height, - 16); + 8); /* Additional space for motion vector */ pix_mp->plane_fmt[0].sizeimage *= 2; - pix_mp->plane_fmt[0].sizeimage += SZ_4M; pix_mp->plane_fmt[1].sizeimage = SZ_2M; #endif pix_mp->num_planes = 2; diff --git a/drivers/staging/rockchip-mpp/rkvdec/avc-data.c b/drivers/staging/rockchip-mpp/rkvdec/avc-data.c new file mode 100644 index 000000000000..57172528f988 --- /dev/null +++ b/drivers/staging/rockchip-mpp/rkvdec/avc-data.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Randy Li, + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "avc-data.h" + +static const u32 zig_zag_4x4[16] = { + 0, 1, 4, 8, 5, 2, 3, 6, 9, 12, 13, 10, 7, 11, 14, 15 +}; + +static const u32 zig_zag_8x8[64] = { + 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, + 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, + 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, + 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 +}; + +static void fill_is_long_term(struct rbsp *rbsp, const struct v4l2_ctrl_h264_decode_param + *decode_param) +{ + u16 is_long_term = 0; + u8 i; + + for (i = 0; i < 16; i++) + if (decode_param->dpb[i]. + flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + is_long_term |= (1 << i); + + rbsp_write_bits(rbsp, 16, is_long_term); +} + +/* in zig-zag order */ +void rkvdec_avc_update_scaling_list(u8 * buf, const struct + v4l2_ctrl_h264_scaling_matrix + *scaling) +{ + u8 i, j; + + for (i = 0; i < 6; i++) + for (j = 0; j < 16; j++) + buf[zig_zag_4x4[j] + (i << 4)] = + scaling->scaling_list_4x4[i][j]; + + for (i = 0; i < 2; i++) + for (j = 0; j < 64; j++) + buf[zig_zag_8x8[j] + (i << 6)] = + scaling->scaling_list_8x8[i][j]; +} + +int rkvdec_avc_write_sps(struct rbsp *rbsp, + const struct v4l2_ctrl_h264_sps *sps) +{ + /* TODO: seq_parameter_set_id */ + rbsp_write_bits(rbsp, 4, 0); + rbsp_write_bits(rbsp, 8, sps->profile_idc); + /* constraint_set3_flag */ + rbsp_write_flag(rbsp, sps->constraint_set_flags >> 3); + rbsp_write_bits(rbsp, 2, sps->chroma_format_idc); + /* bit_depth_luma Not used */ + rbsp_write_bits(rbsp, 3, sps->bit_depth_luma_minus8); + /* bit_depth_chroma Not used */ + rbsp_write_bits(rbsp, 3, sps->bit_depth_chroma_minus8); + /* TODO: qpprime_y_zero_transform_bypass_flag */ + rbsp_write_flag(rbsp, 0); + rbsp_write_bits(rbsp, 4, sps->log2_max_frame_num_minus4); + rbsp_write_bits(rbsp, 5, sps->max_num_ref_frames); + rbsp_write_bits(rbsp, 2, sps->pic_order_cnt_type); + rbsp_write_bits(rbsp, 4, sps->log2_max_pic_order_cnt_lsb_minus4); + /* delta_pic_order_always_zero_flag */ + rbsp_write_flag(rbsp, + sps->flags & + V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); + rbsp_write_bits(rbsp, 9, sps->pic_width_in_mbs_minus1 + 1); + /* TODO: check whether it work for field coding */ + rbsp_write_bits(rbsp, 9, sps->pic_height_in_map_units_minus1 + 1); + rbsp_write_flag(rbsp, sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); + rbsp_write_flag(rbsp, sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); + rbsp_write_flag(rbsp, + sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); + + /* TODO: mvc */ + rbsp_write_flag(rbsp, 0); + /* num_views_minus1 */ + rbsp_write_bits(rbsp, 2, 0); + /* view_id[0] */ + rbsp_write_bits(rbsp, 10, 0); + /* view_id[1] */ + rbsp_write_bits(rbsp, 10, 0); + /* num_anchor_refs_l0 */ + rbsp_write_flag(rbsp, 0); + /* anchor_ref_l0 */ + rbsp_write_bits(rbsp, 10, 0); + rbsp_write_flag(rbsp, 0); + rbsp_write_bits(rbsp, 10, 0); + /* num_non_anchor_refs_l0 */ + rbsp_write_flag(rbsp, 0); + rbsp_write_bits(rbsp, 10, 0); + rbsp_write_flag(rbsp, 0); + rbsp_write_bits(rbsp, 10, 0); + /* Align with 128 bit */ + rbsp_write_bits(rbsp, 2, 0); + + return 0; +} + +int rkvdec_avc_write_pps(struct rbsp *rbsp, + const struct v4l2_ctrl_h264_pps *pps) +{ + /* TODO: pps_pic_parameter_set_id */ + rbsp_write_bits(rbsp, 8, 0); + rbsp_write_bits(rbsp, 5, 0); + rbsp_write_flag(rbsp, + pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); + rbsp_write_flag(rbsp, + pps->flags & + V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); + rbsp_write_bits(rbsp, 5, pps->num_ref_idx_l0_default_active_minus1); + rbsp_write_bits(rbsp, 5, pps->num_ref_idx_l1_default_active_minus1); + rbsp_write_flag(rbsp, pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED); + rbsp_write_bits(rbsp, 2, pps->weighted_bipred_idc); + rbsp_write_bits(rbsp, 7, pps->pic_init_qp_minus26); + rbsp_write_bits(rbsp, 6, pps->pic_init_qs_minus26); + rbsp_write_bits(rbsp, 5, pps->chroma_qp_index_offset); + rbsp_write_flag(rbsp, + pps->flags & + V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); + rbsp_write_flag(rbsp, + pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); + rbsp_write_flag(rbsp, + pps->flags & + V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); + rbsp_write_flag(rbsp, + pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); + rbsp_write_bits(rbsp, 5, pps->second_chroma_qp_index_offset); + rbsp_write_flag(rbsp, + pps->flags & + V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT); + + return 0; +} + +int rkvdec_avc_write_pps_tail(struct rbsp *rbsp, dma_addr_t scaling_addr, const struct v4l2_ctrl_h264_decode_param + *decode_param) +{ + /* scaling list buffer */ + rbsp_write_bits(rbsp, 32, scaling_addr); + + /* DPB */ + fill_is_long_term(rbsp, decode_param); + + /* TODO: VOIdx, Layer id */ + rbsp_write_bits(rbsp, 16, 0); + + /* Align with 128 bit */ + rbsp_write_bits(rbsp, 8, 0); + + return 0; +} + +static inline void fill_rps_list(struct rbsp *rbsp, const struct v4l2_ctrl_h264_decode_param + *decode_param, const u8 * list) +{ + u8 i; + + for (i = 0; i < 32; i++) { + u8 idx, active_flag; + + idx = list[i]; + + active_flag = decode_param->dpb[idx].flags & + V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; + if (!active_flag) { + rbsp_write_bits(rbsp, 7, 0); + } else { + rbsp_write_bits(rbsp, 5, idx | BIT(5)); + /* TODO: bottom flag */ + rbsp_write_flag(rbsp, 0); + /* TODO: view id */ + rbsp_write_flag(rbsp, 0); + } + } +} + +int rkvdec_avc_write_rps(struct rbsp *rbsp, + const struct v4l2_ctrl_h264_sps *sps, + const struct v4l2_ctrl_h264_slice_param *slice_param, + const struct v4l2_ctrl_h264_decode_param *decode_param) +{ + int max_frame_num = 1 << (sps->log2_max_frame_num_minus4 + 4); + u8 i; + + for (i = 0; i < 16; i++) { + u16 frame_num = decode_param->dpb[i].frame_num; + + rbsp_write_bits(rbsp, 16, frame_num > max_frame_num ? + frame_num - max_frame_num : frame_num); + } + + /* reserved */ + rbsp_write_bits(rbsp, 16, 0); + /* TODO: VoidX */ + rbsp_write_bits(rbsp, 16, 0); + + switch (slice_param->slice_type) { + case V4L2_H264_SLICE_TYPE_P: + fill_rps_list(rbsp, decode_param, slice_param->ref_pic_list0); + for (i = 0; i < 14; i++) + rbsp_write_bits(rbsp, 32, 0); + break; + case V4L2_H264_SLICE_TYPE_B: + for (i = 0; i < 7; i++) + rbsp_write_bits(rbsp, 32, 0); + fill_rps_list(rbsp, decode_param, slice_param->ref_pic_list0); + fill_rps_list(rbsp, decode_param, slice_param->ref_pic_list1); + break; + case V4L2_H264_SLICE_TYPE_I: + /* TODO: SVC */ + default: + for (i = 0; i < 21; i++) + rbsp_write_bits(rbsp, 32, 0); + break; + } + + rbsp_write_bits(rbsp, 32, 0); + rbsp_write_bits(rbsp, 32, 0); + + return 0; +} diff --git a/drivers/staging/rockchip-mpp/rkvdec/avc-data.h b/drivers/staging/rockchip-mpp/rkvdec/avc-data.h new file mode 100644 index 000000000000..38ad17273b8a --- /dev/null +++ b/drivers/staging/rockchip-mpp/rkvdec/avc-data.h @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Randy Li, + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include + +#include "rbsp.h" + +void rkvdec_avc_update_scaling_list(u8 * buf, const struct + v4l2_ctrl_h264_scaling_matrix + *scaling); + +int rkvdec_avc_write_sps(struct rbsp *rbsp, + const struct v4l2_ctrl_h264_sps *sps); + +int rkvdec_avc_write_pps(struct rbsp *rbsp, + const struct v4l2_ctrl_h264_pps *pps); + +int rkvdec_avc_write_pps_tail(struct rbsp *rbsp, dma_addr_t scaling_addr, + const struct v4l2_ctrl_h264_decode_param *decode_param); + +int rkvdec_avc_write_rps(struct rbsp *rbsp, + const struct v4l2_ctrl_h264_sps *sps, + const struct v4l2_ctrl_h264_slice_param *slice_param, + const struct v4l2_ctrl_h264_decode_param + *decode_param); diff --git a/drivers/staging/rockchip-mpp/rkvdec/avc.c b/drivers/staging/rockchip-mpp/rkvdec/avc.c index 3d91a119e533..1cb5b2208bfa 100644 --- a/drivers/staging/rockchip-mpp/rkvdec/avc.c +++ b/drivers/staging/rockchip-mpp/rkvdec/avc.c @@ -24,6 +24,56 @@ #include "mpp_dev_common.h" #include "hal.h" #include "regs.h" +#include "avc-data.h" + +static void generate_input_data(struct rkvdec_regs *p_regs, + struct vb2_v4l2_buffer *src_buf, + const struct v4l2_ctrl_h264_sps *sps, + const struct v4l2_ctrl_h264_pps *pps, + const struct v4l2_ctrl_h264_scaling_matrix + *scaling, const struct v4l2_ctrl_h264_slice_param + *slice_param, const struct v4l2_ctrl_h264_decode_param + *decode_param) +{ + struct rbsp rbsp = { 0, }; + size_t r_scaling_offs, r_sps_offs, r_rps_offs; + size_t stream_len = 0; + dma_addr_t scaling_addr = 0; + void *r_data = NULL; + int i; + + stream_len = slice_param->size + 64; + + r_data = vb2_plane_vaddr(&src_buf->vb2_buf, 0); + r_scaling_offs = ALIGN(stream_len, 16); + r_data += r_scaling_offs; + + if (pps->flags & V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT) { + rkvdec_avc_update_scaling_list(r_data, scaling); + r_sps_offs = r_scaling_offs + 6 * 16 + 2 * 64 + 128; + r_sps_offs = ALIGN(r_sps_offs, 16); + scaling_addr = p_regs->sw_strm_rlc_base + r_scaling_offs; + } else { + r_sps_offs = r_scaling_offs; + scaling_addr = 0; + } + + rbsp_init(&rbsp, r_data + r_sps_offs, SZ_2M - r_sps_offs, 0); + rkvdec_avc_write_sps(&rbsp, sps); + rkvdec_avc_write_pps(&rbsp, pps); + rkvdec_avc_write_pps_tail(&rbsp, scaling_addr, decode_param); + p_regs->sw_pps_base = p_regs->sw_strm_rlc_base + r_sps_offs; + + for (i = 1; i < 256; i++) + memset(r_data + r_sps_offs + i * 32, 0, 32); + + /* 256 bits */ + r_rps_offs = r_sps_offs + 32 * 256 + 128; + r_rps_offs = ALIGN(r_rps_offs, 16); + rbsp_init(&rbsp, r_data + r_rps_offs, SZ_2M - r_rps_offs, 0); + rkvdec_avc_write_rps(&rbsp, sps, slice_param, decode_param); + p_regs->sw_rps_base = p_regs->sw_strm_rlc_base + r_rps_offs; +} static void init_hw_cfg(struct rkvdec_regs *p_regs) { @@ -152,18 +202,23 @@ int rkvdec_avc_gen_reg(struct mpp_session *session, void *regs, { const struct v4l2_ctrl_h264_sps *sps; const struct v4l2_ctrl_h264_pps *pps; + const struct v4l2_ctrl_h264_scaling_matrix *scaling; const struct v4l2_ctrl_h264_slice_param *slice_param; const struct v4l2_ctrl_h264_decode_param *decode_param; struct vb2_v4l2_buffer *dst_buf; struct rkvdec_regs *p_regs = regs; - size_t stream_len = 0; sps = rockchip_mpp_get_cur_ctrl(session, V4L2_CID_MPEG_VIDEO_H264_SPS); pps = rockchip_mpp_get_cur_ctrl(session, V4L2_CID_MPEG_VIDEO_H264_PPS); - slice_param = rockchip_mpp_get_cur_ctrl(session, - V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); - decode_param = rockchip_mpp_get_cur_ctrl(session, - V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); + scaling = + rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); + slice_param = + rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); + decode_param = + rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); if (!sps || !pps || !slice_param || !decode_param) return -EINVAL; @@ -178,12 +233,14 @@ int rkvdec_avc_gen_reg(struct mpp_session *session, void *regs, p_regs->sw_sysctrl.strm_start_bit = slice_param->header_bit_size; /* hardware wants a zerod memory at the stream end */ - stream_len = slice_param->size + 64; - p_regs->sw_stream_len = stream_len; + p_regs->sw_stream_len = slice_param->size + 64; dst_buf = v4l2_m2m_next_dst_buf(session->fh.m2m_ctx); rkvdec_avc_gen_ref(p_regs, dst_buf, decode_param); + generate_input_data(p_regs, src_buf, sps, pps, scaling, slice_param, + decode_param); + return 0; } diff --git a/drivers/staging/rockchip-mpp/vdpu2/avc.c b/drivers/staging/rockchip-mpp/vdpu2/avc.c new file mode 100644 index 000000000000..f77bb8ef810a --- /dev/null +++ b/drivers/staging/rockchip-mpp/vdpu2/avc.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Randy Li, + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include +#include +#include + +#include "mpp_dev_common.h" +#include "hal.h" +#include "regs.h" + +#define DEC_LITTLE_ENDIAN (1) + +static const u8 zigzag[64] = { + 0, 1, 8, 16, 9, 2, 3, 10, + 17, 24, 32, 25, 18, 11, 4, 5, + 12, 19, 26, 33, 40, 48, 41, 34, + 27, 20, 13, 6, 7, 14, 21, 28, + 35, 42, 49, 56, 57, 50, 43, 36, + 29, 22, 15, 23, 30, 37, 44, 51, + 58, 59, 52, 45, 38, 31, 39, 46, + 53, 60, 61, 54, 47, 55, 62, 63 +}; + +static const u8 intra_default_q_matrix[64] = { + 8, 16, 19, 22, 26, 27, 29, 34, + 16, 16, 22, 24, 27, 29, 34, 37, + 19, 22, 26, 27, 29, 34, 34, 38, + 22, 22, 26, 27, 29, 34, 37, 40, + 22, 26, 27, 29, 32, 35, 40, 48, + 26, 27, 29, 32, 35, 40, 48, 58, + 26, 27, 29, 34, 38, 46, 56, 69, + 27, 29, 35, 38, 46, 56, 69, 83 +}; + +static void init_hw_cfg(struct vdpu2_regs *p_regs) +{ + p_regs->sw54.dec_strm_wordsp = 1; + p_regs->sw54.dec_strendian_e = DEC_LITTLE_ENDIAN; + p_regs->sw54.dec_in_wordsp = 1; + p_regs->sw54.dec_out_wordsp = 1; + p_regs->sw54.dec_in_endian = DEC_LITTLE_ENDIAN; //change + p_regs->sw54.dec_out_endian = DEC_LITTLE_ENDIAN; + p_regs->sw57.dec_timeout = 1; + p_regs->sw57.dec_timeout_e = 1; + + p_regs->sw57.dec_clk_gate_e = 1; + p_regs->sw57.pref_sigchan = 1; + p_regs->sw57.bus_pos_sel = 1; + p_regs->sw57.intra_dbl3t = 1; + p_regs->sw57.inter_dblspeed = 1; + p_regs->sw57.intra_dblspeed = 1; + + p_regs->sw50.tiled_mode_msb = 0; + p_regs->sw56.dec_max_burst = 16; + p_regs->sw50.dec_scmd_dis = 0; + p_regs->sw50.dec_adv_pre_dis = 0; + p_regs->sw52.apf_threshold = 8; + + p_regs->sw50.dec_latency = 0; + p_regs->sw56.dec_data_disc_e = 0; + + p_regs->sw55.dec_irq = 0; + p_regs->sw56.dec_axi_rd_id = 0; + p_regs->sw56.dec_axi_wr_id = 0; + + p_reg->sw59.pred_bc_tap_0_0 = 1; + /* -5 */ + p_reg->sw59.pred_bc_tap_0_1 = 0x3fb; + p_reg->sw59.pred_bc_tap_0_2 = 20; + + p_regs->sw53.dec_mode = RKVDPU2_FMT_H264D; +} + +int rkvdpu_mpeg2_gen_reg(struct mpp_session *session, void *regs, + struct vb2_v4l2_buffer *src_buf) +{ + const struct v4l2_ctrl_h264_sps *sps; + const struct v4l2_ctrl_h264_pps *pps; + const struct v4l2_ctrl_h264_scaling_matrix *scaling; + const struct v4l2_ctrl_h264_slice_param *slice_param; + const struct v4l2_ctrl_h264_decode_param *decode_param; + struct vb2_v4l2_buffer *dst_buf; + struct rkvdec_regs *p_regs = regs; + + sps = rockchip_mpp_get_cur_ctrl(session, V4L2_CID_MPEG_VIDEO_H264_SPS); + pps = rockchip_mpp_get_cur_ctrl(session, V4L2_CID_MPEG_VIDEO_H264_PPS); + scaling = + rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); + slice_param = + rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); + decode_param = + rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); + + if (!sps || !pps || !slice_param || !decode_param) + return -EINVAL; + + init_hw_cfg(p_regs); + + p_regs->sw120.pic_mb_width = sps->pic_width_in_mbs_minus1 + 1; + p_regs->sw120.pic_mb_height_p = sps->pic_height_in_map_units_minus1 + 1; + +#if 0 + /* PICT_FRAME */ + if (picture->picture_structure == 3) { + p_regs->sw57.pic_fieldmode_e = 0; + } else { + p_regs->sw57.pic_fieldmode_e = 1; + /* PICT_TOP_FIEL */ + if (picture->picture_structure == 1) + p_regs->sw57.pic_topfield_e = 1; + } +#endif + p_regs->sw51.qp_init = pps->pic_init_qp_minus26 + 26; + p_regs->sw114.max_refidx0 = slice_params->num_ref_idx_l0_active_minus1 + 1; + p_regs->sw111.max_refnum = sps->num_ref_frames; + + p_regs->sw115.const_intra_en = pps->constrained_intra_pred_flag; + +#if 0 + p_regs->sw112.dblk_ctrl_flag = pp->deblocking_filter_control_present_flag; + p_regs->sw112.rpcp_flag = pp->redundant_pic_cnt_present_flag; + p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; + p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag; + p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id; + p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id; + p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen; +#endif + + p_regs->sw52.startmb_x = 0; + p_regs->sw52.startmb_y = 0; + p_regs->sw57.dec_out_dis = 0; + p_regs->sw50.filtering_dis = 1; + + p_regs->sw64.rlc_vlc_base = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + p_regs->sw122.strm_start_bit = params->data_bit_offset; + stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); + p_regs->sw51.stream_len = stream_len; + + qtable = vb2_plane_vaddr(&src_buf->vb2_buf, 0) + ALIGN(stream_len, 8); + p_regs->sw61.qtable_base = p_regs->sw64.rlc_vlc_base + + ALIGN(stream_len, 8); + + return 0; +} From patchwork Wed Apr 10 12:42:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893821 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D552B17EF for ; Wed, 10 Apr 2019 12:43:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCD0526B39 for ; Wed, 10 Apr 2019 12:43:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0C3128A50; Wed, 10 Apr 2019 12:43:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4755C28908 for ; Wed, 10 Apr 2019 12:43:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732038AbfDJMnD (ORCPT ); Wed, 10 Apr 2019 08:43:03 -0400 Received: from kozue.soulik.info ([108.61.200.231]:44006 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732035AbfDJMnD (ORCPT ); Wed, 10 Apr 2019 08:43:03 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id A5EA21014ED; Wed, 10 Apr 2019 21:43:48 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: Randy Li , hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 5/9] [TEST]: rockchip: mpp: support qtable Date: Wed, 10 Apr 2019 20:42:22 +0800 Message-Id: <20190410124226.8612-6-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Randy Li I don't care, I don't want to store buffers for a session. I just want to use it to verify the FFmpeg. --- drivers/staging/rockchip-mpp/mpp_dev_common.h | 3 +++ drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c | 5 ++++- drivers/staging/rockchip-mpp/vdpu2/mpeg2.c | 13 ++++++++----- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/staging/rockchip-mpp/mpp_dev_common.h b/drivers/staging/rockchip-mpp/mpp_dev_common.h index 36770af53a95..33d7725be67b 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_common.h +++ b/drivers/staging/rockchip-mpp/mpp_dev_common.h @@ -100,6 +100,9 @@ struct mpp_session { struct v4l2_ctrl_handler ctrl_handler; /* TODO: FIXME: slower than helper function ? */ struct v4l2_ctrl **ctrls; + + dma_addr_t qtable_addr; + void *qtable_vaddr; }; /* The context for the a task */ diff --git a/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c b/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c index dbd9f334562e..1be73ab9c2be 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c +++ b/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c @@ -246,6 +246,9 @@ static int rkvdpu_open(struct file *filp) if (IS_ERR_OR_NULL(session)) return PTR_ERR(session); + session->qtable_vaddr = dmam_alloc_coherent(mpp_dev->dev, 64 * 4, + &session->qtable_addr, + GFP_KERNEL); filp->private_data = &session->fh; pm_runtime_get_sync(mpp_dev->dev); @@ -529,7 +532,7 @@ static int rockchip_mpp_rkvdpu_probe(struct platform_device *pdev) ret = mpp_dev_register_node(mpp_dev, mpp_dev->variant->node_name, NULL, &rkvdpu_ioctl_ops); if (ret) - dev_err(dev, "register char device failed: %d\n", ret); + dev_err(dev, "register v4l2/media device failed: %d\n", ret); memcpy(mpp_dev->fmt_out, fmt_out_templ, sizeof(fmt_out_templ)); memcpy(mpp_dev->fmt_cap, fmt_cap_templ, sizeof(fmt_cap_templ)); diff --git a/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c b/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c index d32958c4cb20..837ee4a4a000 100644 --- a/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c +++ b/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c @@ -52,7 +52,7 @@ static const u8 intra_default_q_matrix[64] = { static void mpeg2_dec_copy_qtable(u8 * qtable, const struct v4l2_ctrl_mpeg2_quantization *ctrl) { - int i, n; + int i; if (!qtable || !ctrl) return; @@ -111,16 +111,12 @@ int rkvdpu_mpeg2_gen_reg(struct mpp_session *session, void *regs, struct vb2_v4l2_buffer *src_buf) { const struct v4l2_ctrl_mpeg2_slice_params *params; - const struct v4l2_ctrl_mpeg2_quantization *quantization; const struct v4l2_mpeg2_sequence *sequence; const struct v4l2_mpeg2_picture *picture; struct vdpu2_regs *p_regs = regs; params = rockchip_mpp_get_cur_ctrl(session, V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS); - quantization = rockchip_mpp_get_cur_ctrl(session, - V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); - if (!params) return -EINVAL; @@ -211,6 +207,7 @@ int rkvdpu_mpeg2_prepare_buf(struct mpp_session *session, void *regs) { const struct v4l2_ctrl_mpeg2_slice_params *params; const struct v4l2_mpeg2_sequence *sequence; + const struct v4l2_ctrl_mpeg2_quantization *quantization; const struct v4l2_mpeg2_picture *picture; struct vb2_v4l2_buffer *dst_buf; dma_addr_t cur_addr, fwd_addr, bwd_addr; @@ -223,6 +220,9 @@ int rkvdpu_mpeg2_prepare_buf(struct mpp_session *session, void *regs) picture = ¶ms->picture; sequence = ¶ms->sequence; + quantization = rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); + dst_buf = v4l2_m2m_next_dst_buf(session->fh.m2m_ctx); cur_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); @@ -266,5 +266,8 @@ int rkvdpu_mpeg2_prepare_buf(struct mpp_session *session, void *regs) p_regs->sw135.refer3_base = cur_addr >> 2; } + mpeg2_dec_copy_qtable(session->qtable_vaddr, quantization); + p_regs->sw61.qtable_base = session->qtable_addr; + return 0; } From patchwork Wed Apr 10 12:42:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893823 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 126411515 for ; Wed, 10 Apr 2019 12:43:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EFA1D28908 for ; Wed, 10 Apr 2019 12:43:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E3E6E289D7; Wed, 10 Apr 2019 12:43:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7246128908 for ; Wed, 10 Apr 2019 12:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732039AbfDJMnF (ORCPT ); Wed, 10 Apr 2019 08:43:05 -0400 Received: from kozue.soulik.info ([108.61.200.231]:44030 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732035AbfDJMnF (ORCPT ); Wed, 10 Apr 2019 08:43:05 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id CB93F1014F0; Wed, 10 Apr 2019 21:43:51 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: Randy Li , hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 6/9] [TEST]: rockchip: mpp: vdpu2: move qtable to input buffer Date: Wed, 10 Apr 2019 20:42:23 +0800 Message-Id: <20190410124226.8612-7-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Randy Li I want the memory region !!! It can save more time if those data are prepared in userspace. Signed-off-by: Randy Li --- drivers/staging/rockchip-mpp/mpp_dev_common.c | 3 +-- drivers/staging/rockchip-mpp/mpp_dev_common.h | 3 --- drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c | 3 +++ drivers/staging/rockchip-mpp/vdpu2/mpeg2.c | 20 +++++++++++-------- 4 files changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/staging/rockchip-mpp/mpp_dev_common.c b/drivers/staging/rockchip-mpp/mpp_dev_common.c index 21816ad8a43b..97c4d897f168 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_common.c +++ b/drivers/staging/rockchip-mpp/mpp_dev_common.c @@ -1217,8 +1217,7 @@ static int rockchip_mpp_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->io_modes = VB2_MMAP | VB2_DMABUF; src_vq->drv_priv = session; src_vq->mem_ops = &vb2_dma_contig_memops; - src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | - DMA_ATTR_NO_KERNEL_MAPPING; + src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); src_vq->min_buffers_needed = 1; src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; diff --git a/drivers/staging/rockchip-mpp/mpp_dev_common.h b/drivers/staging/rockchip-mpp/mpp_dev_common.h index 33d7725be67b..36770af53a95 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_common.h +++ b/drivers/staging/rockchip-mpp/mpp_dev_common.h @@ -100,9 +100,6 @@ struct mpp_session { struct v4l2_ctrl_handler ctrl_handler; /* TODO: FIXME: slower than helper function ? */ struct v4l2_ctrl **ctrls; - - dma_addr_t qtable_addr; - void *qtable_vaddr; }; /* The context for the a task */ diff --git a/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c b/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c index 1be73ab9c2be..92d68b962fe1 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c +++ b/drivers/staging/rockchip-mpp/mpp_dev_vdpu2.c @@ -176,6 +176,9 @@ static int rkvdpu_s_fmt_vid_out_mplane(struct file *filp, void *priv, if (sizes >= SZ_16M) return -EINVAL; + /* For those slice header data */ + pix_mp->plane_fmt[pix_mp->num_planes - 1].sizeimage += SZ_1M; + if (vdpu_setup_ctrls(session, pix_mp->pixelformat)) return -EINVAL; diff --git a/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c b/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c index 837ee4a4a000..c12d1a8ef2da 100644 --- a/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c +++ b/drivers/staging/rockchip-mpp/vdpu2/mpeg2.c @@ -113,7 +113,10 @@ int rkvdpu_mpeg2_gen_reg(struct mpp_session *session, void *regs, const struct v4l2_ctrl_mpeg2_slice_params *params; const struct v4l2_mpeg2_sequence *sequence; const struct v4l2_mpeg2_picture *picture; + const struct v4l2_ctrl_mpeg2_quantization *quantization; struct vdpu2_regs *p_regs = regs; + void *qtable = NULL; + size_t stream_len = 0; params = rockchip_mpp_get_cur_ctrl(session, V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS); @@ -122,6 +125,8 @@ int rkvdpu_mpeg2_gen_reg(struct mpp_session *session, void *regs, sequence = ¶ms->sequence; picture = ¶ms->picture; + quantization = rockchip_mpp_get_cur_ctrl(session, + V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); init_hw_cfg(p_regs); @@ -198,7 +203,13 @@ int rkvdpu_mpeg2_gen_reg(struct mpp_session *session, void *regs, p_regs->sw64.rlc_vlc_base = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); p_regs->sw122.strm_start_bit = params->data_bit_offset; - p_regs->sw51.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); + stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); + p_regs->sw51.stream_len = stream_len; + + qtable = vb2_plane_vaddr(&src_buf->vb2_buf, 0) + ALIGN(stream_len, 8); + mpeg2_dec_copy_qtable(qtable, quantization); + p_regs->sw61.qtable_base = p_regs->sw64.rlc_vlc_base + + ALIGN(stream_len, 8); return 0; } @@ -207,7 +218,6 @@ int rkvdpu_mpeg2_prepare_buf(struct mpp_session *session, void *regs) { const struct v4l2_ctrl_mpeg2_slice_params *params; const struct v4l2_mpeg2_sequence *sequence; - const struct v4l2_ctrl_mpeg2_quantization *quantization; const struct v4l2_mpeg2_picture *picture; struct vb2_v4l2_buffer *dst_buf; dma_addr_t cur_addr, fwd_addr, bwd_addr; @@ -220,9 +230,6 @@ int rkvdpu_mpeg2_prepare_buf(struct mpp_session *session, void *regs) picture = ¶ms->picture; sequence = ¶ms->sequence; - quantization = rockchip_mpp_get_cur_ctrl(session, - V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); - dst_buf = v4l2_m2m_next_dst_buf(session->fh.m2m_ctx); cur_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); @@ -266,8 +273,5 @@ int rkvdpu_mpeg2_prepare_buf(struct mpp_session *session, void *regs) p_regs->sw135.refer3_base = cur_addr >> 2; } - mpeg2_dec_copy_qtable(session->qtable_vaddr, quantization); - p_regs->sw61.qtable_base = session->qtable_addr; - return 0; } From patchwork Wed Apr 10 12:42:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B9F81515 for ; Wed, 10 Apr 2019 12:43:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA4BB28908 for ; Wed, 10 Apr 2019 12:43:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DDCE8289D7; Wed, 10 Apr 2019 12:43:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7453228908 for ; Wed, 10 Apr 2019 12:43:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732041AbfDJMnI (ORCPT ); Wed, 10 Apr 2019 08:43:08 -0400 Received: from kozue.soulik.info ([108.61.200.231]:44030 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732040AbfDJMnI (ORCPT ); Wed, 10 Apr 2019 08:43:08 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id 086B81014F2; Wed, 10 Apr 2019 21:43:53 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: ayaka , randy.li@rock-chips.com, hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 7/9] [TEST]: rkvdec: spspps address alignment Date: Wed, 10 Apr 2019 20:42:24 +0800 Message-Id: <20190410124226.8612-8-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I found the offset for cpu access is not equal to the DMA opeartion. Signed-off-by: ayaka --- drivers/staging/rockchip-mpp/mpp_dev_common.h | 3 +++ drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c | 3 +++ drivers/staging/rockchip-mpp/rkvdec/avc.c | 14 +++++++------- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/staging/rockchip-mpp/mpp_dev_common.h b/drivers/staging/rockchip-mpp/mpp_dev_common.h index 36770af53a95..6718bcccde1f 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_common.h +++ b/drivers/staging/rockchip-mpp/mpp_dev_common.h @@ -100,6 +100,9 @@ struct mpp_session { struct v4l2_ctrl_handler ctrl_handler; /* TODO: FIXME: slower than helper function ? */ struct v4l2_ctrl **ctrls; + + void *aux_vaddr; + dma_addr_t aux_addr; }; /* The context for the a task */ diff --git a/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c b/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c index 97abfdfc344f..cc1fa9737bc1 100644 --- a/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c +++ b/drivers/staging/rockchip-mpp/mpp_dev_rkvdec.c @@ -382,6 +382,9 @@ static int rkvdec_open(struct file *filp) filp->private_data = &session->fh; pm_runtime_get_sync(mpp_dev->dev); + session->aux_vaddr = dmam_alloc_coherent(mpp_dev->dev, SZ_1M, + &session->aux_addr, GFP_KERNEL); + mpp_debug_leave(); return 0; } diff --git a/drivers/staging/rockchip-mpp/rkvdec/avc.c b/drivers/staging/rockchip-mpp/rkvdec/avc.c index 1cb5b2208bfa..8266a990dca6 100644 --- a/drivers/staging/rockchip-mpp/rkvdec/avc.c +++ b/drivers/staging/rockchip-mpp/rkvdec/avc.c @@ -26,8 +26,8 @@ #include "regs.h" #include "avc-data.h" -static void generate_input_data(struct rkvdec_regs *p_regs, - struct vb2_v4l2_buffer *src_buf, +static void generate_input_data(struct mpp_session *session, + struct rkvdec_regs *p_regs, const struct v4l2_ctrl_h264_sps *sps, const struct v4l2_ctrl_h264_pps *pps, const struct v4l2_ctrl_h264_scaling_matrix @@ -44,8 +44,8 @@ static void generate_input_data(struct rkvdec_regs *p_regs, stream_len = slice_param->size + 64; - r_data = vb2_plane_vaddr(&src_buf->vb2_buf, 0); - r_scaling_offs = ALIGN(stream_len, 16); + r_data = session->aux_vaddr; + r_scaling_offs = 0; r_data += r_scaling_offs; if (pps->flags & V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT) { @@ -62,7 +62,7 @@ static void generate_input_data(struct rkvdec_regs *p_regs, rkvdec_avc_write_sps(&rbsp, sps); rkvdec_avc_write_pps(&rbsp, pps); rkvdec_avc_write_pps_tail(&rbsp, scaling_addr, decode_param); - p_regs->sw_pps_base = p_regs->sw_strm_rlc_base + r_sps_offs; + p_regs->sw_pps_base = session->aux_addr + r_sps_offs; for (i = 1; i < 256; i++) memset(r_data + r_sps_offs + i * 32, 0, 32); @@ -72,7 +72,7 @@ static void generate_input_data(struct rkvdec_regs *p_regs, r_rps_offs = ALIGN(r_rps_offs, 16); rbsp_init(&rbsp, r_data + r_rps_offs, SZ_2M - r_rps_offs, 0); rkvdec_avc_write_rps(&rbsp, sps, slice_param, decode_param); - p_regs->sw_rps_base = p_regs->sw_strm_rlc_base + r_rps_offs; + p_regs->sw_rps_base = session->aux_addr + r_rps_offs; } static void init_hw_cfg(struct rkvdec_regs *p_regs) @@ -238,7 +238,7 @@ int rkvdec_avc_gen_reg(struct mpp_session *session, void *regs, dst_buf = v4l2_m2m_next_dst_buf(session->fh.m2m_ctx); rkvdec_avc_gen_ref(p_regs, dst_buf, decode_param); - generate_input_data(p_regs, src_buf, sps, pps, scaling, slice_param, + generate_input_data(session, p_regs, sps, pps, scaling, slice_param, decode_param); return 0; From patchwork Wed Apr 10 12:42:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A57F41390 for ; Wed, 10 Apr 2019 12:43:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D41D26B39 for ; Wed, 10 Apr 2019 12:43:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7EBE728A26; Wed, 10 Apr 2019 12:43:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30FCA26B39 for ; Wed, 10 Apr 2019 12:43:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732042AbfDJMnL (ORCPT ); Wed, 10 Apr 2019 08:43:11 -0400 Received: from kozue.soulik.info ([108.61.200.231]:44030 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732028AbfDJMnL (ORCPT ); Wed, 10 Apr 2019 08:43:11 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id D233A1014F3; Wed, 10 Apr 2019 21:43:57 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: Randy Li , hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 8/9] arm64: dts: rockchip: boost clocks for rk3328 Date: Wed, 10 Apr 2019 20:42:25 +0800 Message-Id: <20190410124226.8612-9-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Randy Li Or VOP won't work well. Signed-off-by: Randy Li --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 84f14b132e8f..55a72abed6e7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -738,8 +738,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, + <300000000>, <100000000>, + <400000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>, From patchwork Wed Apr 10 12:42:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 10893837 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53E001390 for ; Wed, 10 Apr 2019 12:43:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A62326B39 for ; Wed, 10 Apr 2019 12:43:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E418289D7; Wed, 10 Apr 2019 12:43:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 96A7B26B39 for ; Wed, 10 Apr 2019 12:43:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732044AbfDJMnQ (ORCPT ); Wed, 10 Apr 2019 08:43:16 -0400 Received: from kozue.soulik.info ([108.61.200.231]:44094 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732028AbfDJMnP (ORCPT ); Wed, 10 Apr 2019 08:43:15 -0400 Received: from misaki.sumomo.pri (unknown [IPv6:2001:470:b30d:2:c604:15ff:0:401]) by kozue.soulik.info (Postfix) with ESMTPA id 1500C1014F7; Wed, 10 Apr 2019 21:44:00 +0900 (JST) From: ayaka To: linux-media@vger.kernel.org Cc: Randy Li , randy.li@rock-chips.com, hverkuil@xs4all.nl, maxime.ripard@bootlin.com, joro@8bytes.org, nicolas@ndufresne.ca, jernej.skrabec@gmail.com, paul.kocialkowski@bootlin.com, thomas.petazzoni@bootlin.com, mchehab@kernel.org, ezequiel@collabora.com, posciak@chromium.org, groeck@chromium.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 9/9] arm64: dts: rockchip: add video codec for rk3328 Date: Wed, 10 Apr 2019 20:42:26 +0800 Message-Id: <20190410124226.8612-10-ayaka@soulik.info> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190410124226.8612-1-ayaka@soulik.info> References: <20190410124226.8612-1-ayaka@soulik.info> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Randy Li Having problem with vepu2 The sclk_vdec_core for RKVDEC is in gpll at vendor kernel. Signed-off-by: Randy Li --- arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 32 ++++++ .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 32 ++++++ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 108 +++++++++++++++++- 3 files changed, 170 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts index 8302d86d35c4..c89714f79f93 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts @@ -213,6 +213,18 @@ }; }; +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvdec_srv { + status = "okay"; +}; + &sdio { bus-width = <4>; cap-sd-highspeed; @@ -269,3 +281,23 @@ &usb_host0_ohci { status = "okay"; }; + +&vdpu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vpu_service{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 2157a528276b..520e444806cc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -256,6 +256,14 @@ }; }; +&h265e { + status = "okay"; +}; + +&h265e_mmu { + status = "okay"; +}; + &i2s1 { status = "okay"; @@ -300,6 +308,18 @@ }; }; +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvdec_srv { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -370,6 +390,10 @@ status = "okay"; }; +&vdpu { + status = "okay"; +}; + &vop { status = "okay"; }; @@ -377,3 +401,11 @@ &vop_mmu { status = "okay"; }; + +&vpu_mmu { + status = "okay"; +}; + +&vpu_service{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 55a72abed6e7..9b3f8d22b60a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -573,6 +573,27 @@ resets = <&cru SRST_GPU_A>; }; + venc_srv: venc-srv { + compatible = "rockchip,mpp-service"; + status = "disabled"; + }; + + h265e: h265e@ff330000 { + compatible = "rockchip,hevc-encoder-v1"; + reg = <0x0 0xff330000 0 0x200>; + interrupts = ; + clocks = <&cru ACLK_H265>, <&cru PCLK_H265>, + <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, + <&cru ACLK_RKVENC>, <&cru ACLK_AXISRAM>; + clock-names = "aclk_h265", "pclk_h265", "clk_core", + "clk_dsp", "aclk_venc", "aclk_axi2sram"; + iommus = <&h265e_mmu>; + rockchip,srv = <&venc_srv>; + syscon = <&grf 0x040c 0x8000800 0x80000>; + power-domains = <&power RK3328_PD_HEVC>; + status = "disabled"; + }; + h265e_mmu: iommu@ff330200 { compatible = "rockchip,iommu"; reg = <0x0 0xff330200 0 0x100>; @@ -584,6 +605,25 @@ status = "disabled"; }; + vepu: vepu@ff340000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xff340000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_H264>, <&cru HCLK_H264>, + <&cru SCLK_VENC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", + "clk_core"; + resets = <&cru SRST_RKVENC_H264_A>, + <&cru SRST_RKVENC_H264_H>; + reset-names = "video_a", "video_h"; + iommus = <&vepu_mmu>; + rockchip,srv = <&venc_srv>; + syscon = <&grf 0x040c 0x8000800 0x80000>; + power-domains = <&power RK3328_PD_HEVC>; + status = "disabled"; + }; + + vepu_mmu: iommu@ff340800 { compatible = "rockchip,iommu"; reg = <0x0 0xff340800 0x0 0x40>; @@ -595,6 +635,42 @@ status = "disabled"; }; + + vpu_service: vdpu-srv { + compatible = "rockchip,mpp-service"; + status = "disabled"; + }; + + vdpu: vpu-decoder@ff350000 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xff350400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>; + reset-names = "video_a", "video_h"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3328_PD_VPU>; + rockchip,srv = <&vpu_service>; + status = "disabled"; + }; + + avsd: avs-decoder@ff351000 { + compatible = "rockchip,avs-decoder-v1"; + reg = <0x0 0xff351000 0x0 0x200>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>; + reset-names = "video_a", "video_h"; + power-domains = <&power RK3328_PD_VPU>; + iommus = <&vpu_mmu>; + rockchip,srv = <&vpu_service>; + status = "disabled"; + }; + vpu_mmu: iommu@ff350800 { compatible = "rockchip,iommu"; reg = <0x0 0xff350800 0x0 0x40>; @@ -606,6 +682,34 @@ status = "disabled"; }; + rkvdec_srv: rkvdec-srv { + compatible = "rockchip,mpp-service"; + status = "disabled"; + }; + + rkvdec: rkvdec@ff36000 { + compatible = "rockchip,video-decoder-v1"; + reg = <0x0 0xff360000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", + "clk_core"; + assigned-clocks = <&cru ACLK_RKVDEC_PRE>, <&cru SCLK_VDEC_CORE>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru PLL_GPLL>; + assigned-clock-rates = <500000000>, <245760000>; + resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>, + <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>, + <&cru SRST_VDEC_CABAC>, <&cru SRST_VDEC_CORE>; + reset-names = "video_a", "video_h", "niu_a", "niu_h", + "video_cabac", "video_core"; + iommus = <&rkvdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + rockchip,srv = <&rkvdec_srv>; + status = "disabled"; + }; + rkvdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; @@ -740,8 +844,8 @@ <15000000>, <15000000>, <300000000>, <100000000>, <400000000>, <100000000>, - <50000000>, <100000000>, - <100000000>, <100000000>, + <50000000>, <300000000>, + <300000000>, <300000000>, <50000000>, <50000000>, <50000000>, <50000000>, <24000000>, <600000000>,