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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y125sm12124318wmc.39.2019.04.12.01.37.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Apr 2019 01:37:30 -0700 (PDT) From: Guillaume La Roque To: jbrunet@baylibre.com, narmstrong@baylibre.com, khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: clk: g12a-clkc: add Temperature Sensor clock ID Date: Fri, 12 Apr 2019 10:37:27 +0200 Message-Id: <20190412083728.21029-2-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190412083728.21029-1-glaroque@baylibre.com> References: <20190412083728.21029-1-glaroque@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190412_013732_822719_BE9C901C X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add clock id used by temperature sensor for G12A Socs Signed-off-by: Guillaume La Roque --- include/dt-bindings/clock/g12a-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 30303728fe09..85cfcab10507 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -133,5 +133,6 @@ #define CLKID_MPLL_5OM 177 #define CLKID_CPU_CLK 187 #define CLKID_PCIE_PLL 201 +#define CLKID_TS 203 #endif /* __G12A_CLKC_H */ From patchwork Fri Apr 12 08:37:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 10897523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6C3217E0 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y125sm12124318wmc.39.2019.04.12.01.37.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Apr 2019 01:37:31 -0700 (PDT) From: Guillaume La Roque To: jbrunet@baylibre.com, narmstrong@baylibre.com, khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/2] clk: meson-g12a: Add Temperature Sensor clock Date: Fri, 12 Apr 2019 10:37:28 +0200 Message-Id: <20190412083728.21029-3-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190412083728.21029-1-glaroque@baylibre.com> References: <20190412083728.21029-1-glaroque@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190412_093733_468760_144B3593 X-CRM114-Status: GOOD ( 14.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add TS clock used by two temperature sensor Signed-off-by: Guillaume La Roque --- drivers/clk/meson/g12a.c | 31 +++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 3 ++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 3a3134976534..cbb4abc0311e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -2335,6 +2335,33 @@ static struct clk_regmap g12a_mali = { }, }; +static struct clk_regmap g12a_ts_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_TS_CLK_CNTL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "ts_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_ts = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_TS_CLK_CNTL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "ts", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "ts_div" }, + .num_parents = 1, + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); @@ -2615,6 +2642,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, + [CLKID_TS_DIV] = &g12a_ts_div.hw, + [CLKID_TS] = &g12a_ts.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2803,6 +2832,8 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_cpu_clk_trace, &g12a_pcie_pll_od, &g12a_pcie_pll_dco, + &g12a_ts_div, + &g12a_ts, }; static const struct meson_eeclkc_data g12a_clkc_data = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 1393a09730a6..5633c72e432d 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -189,8 +189,9 @@ #define CLKID_PCIE_PLL_DCO 198 #define CLKID_PCIE_PLL_DCO_DIV2 199 #define CLKID_PCIE_PLL_OD 200 +#define CLKID_TS_DIV 202 -#define NR_CLKS 202 +#define NR_CLKS 204 /* include the CLKIDs that have been made part of the DT binding */ #include