From patchwork Fri Apr 12 10:20:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897771 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 28EF91390 for ; Fri, 12 Apr 2019 09:55:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0889C28E29 for ; Fri, 12 Apr 2019 09:55:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F065C28E2B; Fri, 12 Apr 2019 09:55:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4E8D428E29 for ; Fri, 12 Apr 2019 09:55:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEF56891B4; Fri, 12 Apr 2019 09:55:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B38B4891B4; Fri, 12 Apr 2019 09:55:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350658" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:07 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:50:57 +0530 Message-Id: <1555064463-18479-2-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v3 1/7] drm: Add gamma mode property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Add a gamma mode property to enable various kind of gamma modes supported by platforms like: Interpolated, Split, Multi Segmented etc. Userspace can get this property and should be able to get the platform capabilties wrt various gamma modes possible and the possible ranges. It can select one of the modes exposed as blob_id as an enum and set the respective mode. It can then create the LUT and send it to driver using already available GAMMA_LUT property as blob. v2: Addressed Sam Ravnborg's review comments. Implemented gamma mode with just one property and renamed the current one to GAMMA_MODE property as recommended by Ville. Signed-off-by: Ville Syrjälä Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_uapi.c | 5 +++ drivers/gpu/drm/drm_color_mgmt.c | 77 +++++++++++++++++++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 8 ++++ include/drm/drm_crtc.h | 7 ++++ include/drm/drm_mode_config.h | 6 +++ include/uapi/drm/drm_mode.h | 38 +++++++++++++++++++ 6 files changed, 141 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index ea797d4..d85e0c9 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -459,6 +459,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == config->gamma_mode_property) { + state->gamma_mode = val; + state->color_mgmt_changed |= replaced; } else if (property == config->prop_out_fence_ptr) { s32 __user *fence_ptr = u64_to_user_ptr(val); @@ -495,6 +498,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, *val = (state->mode_blob) ? state->mode_blob->base.id : 0; else if (property == config->prop_vrr_enabled) *val = state->vrr_enabled; + else if (property == config->gamma_mode_property) + *val = state->gamma_mode; else if (property == config->degamma_lut_property) *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; else if (property == config->ctm_property) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index d5d34d0..4d6792d 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -176,6 +176,83 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_crtc_enable_color_mgmt); +void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_mode_config *config = &dev->mode_config; + + if (!config->gamma_mode_property) + return; + + drm_object_attach_property(&crtc->base, + config->gamma_mode_property, 0); +} +EXPORT_SYMBOL(drm_crtc_attach_gamma_mode_property); + +int drm_color_create_gamma_mode_property(struct drm_device *dev, + int num_values) +{ + struct drm_mode_config *config = &dev->mode_config; + struct drm_property *prop; + + prop = drm_property_create(dev, + DRM_MODE_PROP_ENUM, + "GAMMA_MODE", num_values); + if (!prop) + return -ENOMEM; + + config->gamma_mode_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_color_create_gamma_mode_property); + +int drm_color_add_gamma_mode_range(struct drm_device *dev, + const char *name, + const struct drm_color_lut_range *ranges, + size_t length) +{ + struct drm_mode_config *config = &dev->mode_config; + struct drm_property_blob *blob; + struct drm_property *prop; + int num_ranges = length / sizeof(ranges[0]); + int i, ret, num_types_0; + + if (WARN_ON(length == 0 || length % sizeof(ranges[0]) != 0)) + return -EINVAL; + + num_types_0 = hweight8(ranges[0].flags & (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA)); + if (num_types_0 == 0) + return -EINVAL; + + for (i = 1; i < num_ranges; i++) { + int num_types = hweight8(ranges[i].flags & (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA)); + + /* either all ranges have DEGAMMA|GAMMA or none have it */ + if (num_types_0 != num_types) + return -EINVAL; + } + + prop = config->gamma_mode_property; + if (!prop) + return -EINVAL; + + blob = drm_property_create_blob(dev, length, ranges); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + ret = drm_property_add_enum(prop, blob->base.id, name); + if (ret) { + drm_property_blob_put(blob); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_color_add_gamma_mode_range); + /** * drm_mode_crtc_set_gamma_size - set the gamma table size * @crtc: CRTC to set the gamma table size for diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index d1c662d..f18e9b8 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -51,6 +51,14 @@ static inline int drm_color_lut_size(const struct drm_property_blob *blob) return blob->length / sizeof(struct drm_color_lut); } +int drm_color_create_gamma_mode_property(struct drm_device *dev, + int num_values); +void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc); +int drm_color_add_gamma_mode_range(struct drm_device *dev, + const char *name, + const struct drm_color_lut_range *ranges, + size_t length); + enum drm_color_encoding { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_BT709, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 58ad983..f2e60bd 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -249,6 +249,13 @@ struct drm_crtc_state { struct drm_property_blob *mode_blob; /** + * @gamma_mode: This is a blob_id and exposes the platform capabilties + * wrt to various gamma modes and the respective lut ranges. This also + * helps user select a gamma mode amongst the supported ones. + */ + u32 gamma_mode; + + /** * @degamma_lut: * * Lookup table for converting framebuffer pixel data before apply the diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 7f60e8e..8f961c5b 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -761,6 +761,12 @@ struct drm_mode_config { */ struct drm_property *content_type_property; /** + * @gamma_mode_property: Optional CRTC property to enumerate and + * select the mode of the crtc gamma/degmama LUTs. This also exposes + * the lut ranges of the various supported gamma modes to userspace. + */ + struct drm_property *gamma_mode_property; + /** * @degamma_lut_property: Optional CRTC property to set the LUT used to * convert the framebuffer's colors to linear gamma. */ diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 83cd163..e70b7f8 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -630,6 +630,44 @@ struct drm_color_lut { __u16 reserved; }; +/* + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT + * can be used for either purpose, but not simultaneously. To expose + * modes that support gamma and degamma simultaneously the gamma mode + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA + * ranges. + */ +/* LUT is for gamma (after CTM) */ +#define DRM_MODE_LUT_GAMMA BIT(0) +/* LUT is for degamma (before CTM) */ +#define DRM_MODE_LUT_DEGAMMA BIT(1) +/* linearly interpolate between the points */ +#define DRM_MODE_LUT_INTERPOLATE BIT(2) +/* + * the last value of the previous range is the + * first value of the current range. + */ +#define DRM_MODE_LUT_REUSE_LAST BIT(3) +/* the curve must be non-decreasing */ +#define DRM_MODE_LUT_NON_DECREASING BIT(4) +/* the curve is reflected across origin for negative inputs */ +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) +/* the same curve (red) is used for blue and green channels as well */ +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) + +struct drm_color_lut_range { + /* DRM_MODE_LUT_* */ + __u32 flags; + /* number of points on the curve */ + __u16 count; + /* input/output bits per component */ + __u8 input_bpc, output_bpc; + /* input start/end values */ + __s32 start, end; + /* output min/max values */ + __s32 min, max; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 From patchwork Fri Apr 12 10:20:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E84717E0 for ; Fri, 12 Apr 2019 09:55:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A20C28E29 for ; Fri, 12 Apr 2019 09:55:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E02028E2B; Fri, 12 Apr 2019 09:55:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3D28328E29 for ; Fri, 12 Apr 2019 09:55:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A13B089760; Fri, 12 Apr 2019 09:55:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12CF189760; Fri, 12 Apr 2019 09:55:16 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350685" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:11 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:50:58 +0530 Message-Id: <1555064463-18479-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v3 2/7] drm/i915: Define color lut range structure X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä This defines the color lut ranges for 10bit and multi segmented gamma range for ICL. v2: Defined and advertise the gamma modes supported on various platforms as suggested by Ville. Signed-off-by: Ville Syrjälä Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 566 ++++++++++++++++++++++++++++++++++++- 1 file changed, 562 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index ca341a9..c433215 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -383,6 +383,20 @@ static u32 ilk_lut_10(const struct drm_color_lut *color) drm_color_lut_extract(color->blue, 10); } +static bool i9xx_has_10bit_lut(struct drm_i915_private *dev_priv) +{ + /* + * Bspec: + " "NOTE: The 8-bit (non-10-bit) mode is the only + * mode supported by BrookDale-G and Springdale-G." + * and + * "NOTE: The 8-bit (non-10-bit) mode is the only + * mode supported by Alviso and Grantsdale." + */ + return !IS_I845G(dev_priv) && !IS_I865G(dev_priv) && + !IS_I915G(dev_priv) && !IS_I915GM(dev_priv); +} + /* Loads the legacy palette/gamma unit for the CRTC. */ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob) @@ -1221,10 +1235,420 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) return 0; } +enum { + I9XX_LUT_SIZE_8BIT = 256, + I9XX_LUT_SIZE_10BIT = 129, + + ILK_LUT_SIZE_10BIT = 1024, + ILK_LUT_SIZE_12BIT = 513, + + IVB_LUT_SIZE_SPLIT = 512, + + CHV_LUT_SIZE_CGM_DEGAMMA = 65, + CHV_LUT_SIZE_CGM_GAMMA = 257, +}; + +#define I9XX_GAMMA_8 \ + { \ + .flags = DRM_MODE_LUT_GAMMA, \ + .count = 256, \ + .input_bpc = 8, .output_bpc = 8, \ + .start = 0, .end = (1 << 8) - 1, \ + .min = 0, .max = (1 << 8) - 1, \ + } + +static const struct drm_color_lut_range i9xx_gamma_8[] = { + I9XX_GAMMA_8, +}; + +static const struct drm_color_lut_range i9xx_gamma_10_slope[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 129, + .input_bpc = 10, .output_bpc = 10, + .start = 0, .end = 1 << 10, + .min = 0, .max = (1 << 10) - 1, + }, +}; + +#define I965_GAMMA_10 \ + { \ + .flags = (DRM_MODE_LUT_GAMMA | \ + DRM_MODE_LUT_INTERPOLATE | \ + DRM_MODE_LUT_NON_DECREASING), \ + .count = 128, \ + .input_bpc = 10, .output_bpc = 16, \ + .start = 0, .end = (1 << 10) - (1 << 10) / 128, \ + .min = 0, .max = (1 << 16) - 1, \ + }, \ + /* PIPEGCMAX */ \ + { \ + .flags = (DRM_MODE_LUT_GAMMA | \ + DRM_MODE_LUT_INTERPOLATE | \ + DRM_MODE_LUT_REUSE_LAST | \ + DRM_MODE_LUT_NON_DECREASING), \ + .count = 1, \ + .input_bpc = 10, .output_bpc = 16, \ + .start = (1 << 10) - (1 << 10) / 128, .end = 1 << 10, \ + .min = 0, .max = 1 << 16, \ + } + +static const struct drm_color_lut_range i965_gamma_10[] = { + I965_GAMMA_10, +}; + +#define CHV_CGM_DEGAMMA \ + { \ + .flags = (DRM_MODE_LUT_DEGAMMA | \ + DRM_MODE_LUT_INTERPOLATE | \ + DRM_MODE_LUT_NON_DECREASING), \ + .count = 65, \ + .input_bpc = 10, .output_bpc = 14, \ + .start = 0, .end = 1 << 10, \ + .min = 0, .max = (1 << 14) - 1, \ + } +#define CHV_CGM_GAMMA \ + { \ + .flags = (DRM_MODE_LUT_GAMMA | \ + DRM_MODE_LUT_INTERPOLATE | \ + DRM_MODE_LUT_NON_DECREASING), \ + .count = 257, \ + .input_bpc = 14, .output_bpc = 10, \ + .start = 0, .end = 1 << 14, \ + .min = 0, .max = (1 << 10) - 1, \ + } + +static const struct drm_color_lut_range chv_cgm_degamma[] = { + CHV_CGM_DEGAMMA, +}; + +static const struct drm_color_lut_range chv_cgm_gamma[] = { + CHV_CGM_GAMMA, +}; + +static const struct drm_color_lut_range chv_cgm_degamma_i9xx_gamma_8[] = { + CHV_CGM_DEGAMMA, + I9XX_GAMMA_8, +}; + +static const struct drm_color_lut_range chv_cgm_degamma_i965_gamma_10[] = { + CHV_CGM_DEGAMMA, + I965_GAMMA_10, +}; + +static const struct drm_color_lut_range chv_cgm_degamma_cgm_degamma[] = { + CHV_CGM_DEGAMMA, + CHV_CGM_GAMMA, +}; + +static const struct drm_color_lut_range ilk_gamma_degamma_8[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA), + .count = 256, + .input_bpc = 8, .output_bpc = 8, + .start = 0, .end = (1 << 8) - 1, + .min = 0, .max = (1 << 8) - 1, + }, +}; + +static const struct drm_color_lut_range ilk_gamma_degamma_10[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA), + .count = 1024, + .input_bpc = 10, .output_bpc = 10, + .start = 0, .end = (1 << 10) - 1, + .min = 0, .max = (1 << 10) - 1, + }, +}; + +static const struct drm_color_lut_range ilk_gamma_degamma_12p4[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 512, + .input_bpc = 12, .output_bpc = 16, + .start = 0, .end = (1 << 12) - (1 << 12) / 512, + .min = 0, .max = (1 << 16) - 1, + }, + /* PIPEGCMAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 10, .output_bpc = 16, + .start = (1 << 12) - (1 << 12) / 512, .end = 1 << 12, + .min = 0, .max = 1 << 16, + }, +}; + +static const struct drm_color_lut_range ivb_gamma_degamma_10[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE), + .count = 1024, + .input_bpc = 10, .output_bpc = 10, + .start = 0, .end = (1 << 10) - 1, + .min = 0, .max = (1 << 10) - 1, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 10, .output_bpc = 16, + .start = 1 << 10, .end = 3 << 10, + .min = 0, .max = (8 << 16) - 1, + } +}; + +static const struct drm_color_lut_range glk_gamma_10[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE), + .count = 1024, + .input_bpc = 10, .output_bpc = 10, + .start = 0, .end = (1 << 10) - 1, + .min = 0, .max = (1 << 10) - 1, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 10, .output_bpc = 16, + .start = 1 << 10, .end = 3 << 10, + .min = 0, .max = (8 << 16) - 1, + }, + /* PAL_EXT2_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 10, .output_bpc = 16, + .start = 3 << 12, .end = 7 << 12, + .min = 0, .max = (8 << 16) - 1, + }, +}; + +/* FIXME input bpc? */ +static const struct drm_color_lut_range glk_gamma_12p4[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 512, + .input_bpc = 16, .output_bpc = 16, + .start = 0, .end = (1 << 16) - (1 << 16) / 512, + .min = 0, .max = (1 << 16) - 1, + }, + /* PAL_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = (1 << 16) - (1 << 16) / 512, .end = 1 << 16, + .min = 0, .max = 1 << 16, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = 1 << 16, .end = 3 << 16, + .min = 0, .max = (8 << 16) - 1, + }, + /* PAL_EXT2_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = 3 << 16, .end = 7 << 16, + .min = 0, .max = (8 << 16) - 1, + }, +}; + +static const struct drm_color_lut_range ivb_split_gamma[] = { + { + .flags = (DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE), + .count = 512, + .input_bpc = 9, .output_bpc = 10, + .start = 0, .end = (1 << 9) - 1, + .min = 0, .max = (1 << 10) - 1, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = (DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 10, .output_bpc = 16, + .start = 1 << 9, .end = 3 << 9, + .min = 0, .max = (8 << 16) - 1, + }, + { + .flags = DRM_MODE_LUT_GAMMA, + .count = 512, + .input_bpc = 9, .output_bpc = 10, + .start = 0, .end = (1 << 9) - 1, + .min = 0, .max = (1 << 10) - 1, + }, +}; + +/* FIXME input bpc? */ +static const struct drm_color_lut_range ivb_gamma_degamma_12p4[] = { + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 512, + .input_bpc = 12, .output_bpc = 16, + .start = 0, .end = (1 << 12) - (1 << 12) / 512, + .min = 0, .max = (1 << 16) - 1, + }, + /* PAL_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 12, .output_bpc = 16, + .start = (1 << 12) - (1 << 12) / 512, .end = 1 << 12, + .min = 0, .max = 1 << 16, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 12, .output_bpc = 16, + .start = 1 << 12, .end = 3 << 12, + .min = 0, .max = (8 << 16) - 1, + }, +}; + + /* FIXME input bpc? */ +static const struct drm_color_lut_range icl_multi_seg_gamma[] = { + /* segment 1 aka. super fine segment */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 9, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) / (128 * 256), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 2 aka. fine segment */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 257, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) / 128, + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 3 aka. coarse segment */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 257, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) - (1 << 24) / 256, + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 3 aka. coarse segment / PAL_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 24) - (1 << 24) / 256, .end = 1 << 24, + .min = 0, .max = 1 << 16, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 1 << 24, .end = 3 << 24, + .min = 0, .max = (8 << 16) - 1, + }, + /* PAL_EXT2_GC_MAX */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 3 << 24, .end = 7 << 24, + .min = 0, .max = (8 << 16) - 1, + }, +}; + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; + int degamma_lut_size, gamma_lut_size; drm_mode_crtc_set_gamma_size(&crtc->base, 256); @@ -1233,25 +1657,159 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_check = chv_color_check; dev_priv->display.color_commit = i9xx_color_commit; dev_priv->display.load_luts = cherryview_load_luts; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma", + i9xx_gamma_8, + sizeof(i9xx_gamma_8)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma", + i965_gamma_10, + sizeof(i965_gamma_10)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "CGM gamma", + chv_cgm_gamma, + sizeof(chv_cgm_gamma)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "CGM degamma", + chv_cgm_degamma, + sizeof(chv_cgm_degamma)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "CGM degamma with 8bit gamma", + chv_cgm_degamma_i9xx_gamma_8, + sizeof(chv_cgm_degamma)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "CGM degamma with 10bit interpolated gamma", + chv_cgm_degamma_i965_gamma_10, + sizeof(chv_cgm_degamma)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "CGM degamma with CGM gamma", + chv_cgm_degamma_cgm_degamma, + sizeof(chv_cgm_degamma)); } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv->display.color_check = i9xx_color_check; dev_priv->display.color_commit = i9xx_color_commit; dev_priv->display.load_luts = i965_load_luts; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma", + i9xx_gamma_8, + sizeof(i9xx_gamma_8)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma", + i965_gamma_10, + sizeof(i965_gamma_10)); } else { dev_priv->display.color_check = i9xx_color_check; dev_priv->display.color_commit = i9xx_color_commit; dev_priv->display.load_luts = i9xx_load_luts; + + degamma_lut_size = 0; + gamma_lut_size = 0; + has_ctm = false; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma", + i9xx_gamma_8, + sizeof(i9xx_gamma_8)); + + if (i9xx_has_10bit_lut(dev_priv)) { + /* 10bit interpolated gamma */ + gamma_lut_size = I9XX_LUT_SIZE_10BIT; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma", + i9xx_gamma_10_slope, + sizeof(i9xx_gamma_10_slope)); + } } } else { - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_GEN(dev_priv) >= 11) { dev_priv->display.color_check = icl_color_check; - else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + /* don't advertize the >= 1.0 entries */ + degamma_lut_size = 0; + gamma_lut_size = ILK_LUT_SIZE_10BIT; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma", + i9xx_gamma_8, + sizeof(i9xx_gamma_8)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "10bit gamma", + glk_gamma_10, + sizeof(glk_gamma_10)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma", + glk_gamma_12p4, + sizeof(glk_gamma_12p4)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "multi-segmented gamma", + icl_multi_seg_gamma, + sizeof(icl_multi_seg_gamma)); + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { dev_priv->display.color_check = glk_color_check; - else if (INTEL_GEN(dev_priv) >= 7) + /* don't advertize the >= 1.0 entries */ + degamma_lut_size = 0; + gamma_lut_size = ILK_LUT_SIZE_10BIT; + has_ctm = true; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma", + i9xx_gamma_8, + sizeof(i9xx_gamma_8)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "10bit gamma", + glk_gamma_10, + sizeof(glk_gamma_10)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma", + glk_gamma_12p4, + sizeof(glk_gamma_12p4)); + } else if (INTEL_GEN(dev_priv) >= 7) { dev_priv->display.color_check = ivb_color_check; - else + + /* don't advertize the >= 1.0 entries */ + degamma_lut_size = IVB_LUT_SIZE_SPLIT; + gamma_lut_size = IVB_LUT_SIZE_SPLIT; + has_ctm = true; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma or degamma", + ilk_gamma_degamma_8, + sizeof(ilk_gamma_degamma_8)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "split gamma", + ivb_split_gamma, + sizeof(ivb_split_gamma)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "10bit gamma or degamma", + ivb_gamma_degamma_10, + sizeof(ivb_gamma_degamma_10)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma or degamma", + ivb_gamma_degamma_12p4, + sizeof(ivb_gamma_degamma_12p4)); + } else { dev_priv->display.color_check = ilk_color_check; + degamma_lut_size = 0; + gamma_lut_size = ILK_LUT_SIZE_10BIT; + has_ctm = true; + + drm_color_add_gamma_mode_range(&dev_priv->drm, + "8bit gamma or degamma", + ilk_gamma_degamma_8, + sizeof(ilk_gamma_degamma_8)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "10bit gamma or degamma", + ilk_gamma_degamma_10, + sizeof(ilk_gamma_degamma_10)); + drm_color_add_gamma_mode_range(&dev_priv->drm, + "interpolated gamma or degamma", + ilk_gamma_degamma_12p4, + sizeof(ilk_gamma_degamma_12p4)); + } + if (INTEL_GEN(dev_priv) >= 9) dev_priv->display.color_commit = skl_color_commit; else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) From patchwork Fri Apr 12 10:20:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D71091390 for ; Fri, 12 Apr 2019 09:55:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA88428E29 for ; Fri, 12 Apr 2019 09:55:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AEF2428E2B; Fri, 12 Apr 2019 09:55:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6C97528E29 for ; Fri, 12 Apr 2019 09:55:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C974289872; Fri, 12 Apr 2019 09:55:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id E794789864; Fri, 12 Apr 2019 09:55:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350701" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:16 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:50:59 +0530 Message-Id: <1555064463-18479-4-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v3 3/7] drm/i915/icl: Add register definitions for Multi Segmented gamma X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add macros to define multi segmented gamma registers Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9c206e8..5554b0c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7196,6 +7196,7 @@ enum { #define GAMMA_MODE_MODE_10BIT (1 << 0) #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) +#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* DMC/CSR */ #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) @@ -10136,6 +10137,22 @@ enum skl_power_gate { #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) +/* Add registers for Gen11 Multi Segmented Gamma Mode */ +#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 +#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 +#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15) +#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0) + +#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C +#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C + +#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ + _PAL_PREC_MULTI_SEG_INDEX_A, \ + _PAL_PREC_MULTI_SEG_INDEX_B) +#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ + _PAL_PREC_MULTI_SEG_DATA_A, \ + _PAL_PREC_MULTI_SEG_DATA_B) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) From patchwork Fri Apr 12 10:21:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DE3F17E0 for ; Fri, 12 Apr 2019 09:55:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 564B628E29 for ; Fri, 12 Apr 2019 09:55:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A72C28E2B; Fri, 12 Apr 2019 09:55:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B6C7428E29 for ; Fri, 12 Apr 2019 09:55:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CA988987A; Fri, 12 Apr 2019 09:55:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD13289875; Fri, 12 Apr 2019 09:55:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350722" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:19 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:51:00 +0530 Message-Id: <1555064463-18479-5-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v3 4/7] drm/i915/icl: Add support for multi segmented gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 introduced a new gamma mode i.e, multi segmented gamma mode. Added support for the same. v2: Aligned to just 1 property interface as suggested by Ville. Fixed Ville's review comments. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 166 ++++++++++++++++++++++++++++++++++++- include/drm/drm_crtc.h | 3 + 2 files changed, 165 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index c433215..d4ce1ed 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -58,6 +58,12 @@ #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) +#define LEGACY_PALETTE_MODE_8BIT BIT(0) +#define PRECISION_PALETTE_MODE_10BIT BIT(1) +#define INTERPOLATED_GAMMA_MODE_12BIT BIT(2) +#define MULTI_SEGMENTED_GAMMA_MODE_12BIT BIT(3) +#define SPLIT_GAMMA_MODE_12BIT BIT(4) + static const u16 ilk_csc_off_zero[3] = {}; static const u16 ilk_csc_coeff_identity[9] = { @@ -93,6 +99,22 @@ 0x0800, 0x0100, 0x0800, }; +/* ilk+ "12.4" interpolated format (high 10 bits) */ +static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) +{ + return (color->red >> 6) << 20 | + (color->green >> 6) << 10 | + (color->blue >> 6); +} + +/* ilk+ "12.4" interpolated format (low 6 bits) */ +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) +{ + return (color->red & 0x3f) << 24 | + (color->green & 0x3f) << 14 | + (color->blue & 0x3f); +} + static bool lut_is_legacy(const struct drm_property_blob *lut) { return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; @@ -781,6 +803,118 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) } } +static void icl_program_coarse_segment_lut(const struct intel_crtc_state + *crtc_state, + struct drm_color_lut *gamma_lut, + u32 offset) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_color_lut *lut = gamma_lut; + enum pipe pipe = crtc->pipe; + u32 i, lut_size, word; + + WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK); + + I915_WRITE(PREC_PAL_INDEX(pipe), + (offset ? PAL_PREC_SPLIT_MODE : 0) | + PAL_PREC_AUTO_INCREMENT | + offset); + + if (lut && crtc_state->base.gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) { + lut_size = 9 + 514; + for (i = 9; i < lut_size; i++) { + /* For Even Index */ + word = ilk_lut_12p4_udw(&lut[i]); + + I915_WRITE(PREC_PAL_DATA(pipe), word); + + /* For ODD index */ + word = ilk_lut_12p4_ldw(&lut[i]); + + I915_WRITE(PREC_PAL_DATA(pipe), word); + } + } + + /* + * Program the max register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 1.0 + */ + I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16)); + I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16)); + I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16)); + + /* + * Program the max register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 1.0 to 3.0 + */ + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16)); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16)); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16)); + + /* + * Program the gc max 2 register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 3.0 to 7.0 + */ + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16)); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16)); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16)); + } +} + +static void icl_program_fine_segment_lut(const struct intel_crtc_state + *crtc_state, + struct drm_color_lut *gamma_lut, + u32 offset) +{ + struct drm_crtc *crtc = crtc_state->base.crtc; + struct drm_device *dev = crtc_state->base.crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + u32 i, word, lut_size = 9; + + WARN_ON(offset & ~PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK); + + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), + (PAL_PREC_AUTO_INCREMENT | offset)); + + if (gamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *)gamma_lut; + + for (i = 0; i < lut_size; i++) { + /* For Even Index */ + word = ilk_lut_12p4_udw(&lut[i]); + + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word); + + /* For ODD index */ + word = ilk_lut_12p4_ldw(&lut[i]); + + I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word); + } + } +} + +static void icl_load_gamma_multi_segmented_lut(const struct intel_crtc_state + *crtc_state, u32 offset) +{ + const struct drm_property_blob *gamma_lut_blob = + crtc_state->base.gamma_lut; + struct drm_color_lut *gamma_lut = NULL; + + if (gamma_lut_blob) + gamma_lut = gamma_lut_blob->data; + + icl_program_fine_segment_lut(crtc_state, gamma_lut, 0); + icl_program_coarse_segment_lut(crtc_state, gamma_lut, 0); +} + static void icl_load_luts(const struct intel_crtc_state *crtc_state) { const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; @@ -792,6 +926,9 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == GAMMA_MODE_MODE_8BIT) { i9xx_load_luts(crtc_state); + } else if (crtc_state->base.gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) { + icl_load_gamma_multi_segmented_lut(crtc_state, 0); } else { bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_10_max(crtc); @@ -1186,10 +1323,28 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) return 0; } -static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) +static u32 icl_gamma_mode(struct intel_crtc_state *crtc_state) { + struct drm_device *dev = crtc_state->base.crtc->dev; + struct drm_mode_config *config = &dev->mode_config; + struct drm_property *property = config->gamma_mode_property; + struct drm_property_enum *prop_enum; + u32 index = 0; u32 gamma_mode = 0; + list_for_each_entry(prop_enum, &property->enum_list, head) { + if (prop_enum->value == crtc_state->base.gamma_mode) { + if (!strcmp(prop_enum->name, + "multi-segmented gamma")) { + crtc_state->base.gamma_mode_type = + MULTI_SEGMENTED_GAMMA_MODE_12BIT; + DRM_INFO("multi-segment enabled\n"); + } + break; + } + index++; + } + if (crtc_state->base.degamma_lut) gamma_mode |= PRE_CSC_GAMMA_ENABLE; @@ -1200,6 +1355,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) if (!crtc_state->base.gamma_lut || crtc_state_is_legacy_gamma(crtc_state)) gamma_mode |= GAMMA_MODE_MODE_8BIT; + else if (crtc_state->base.gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) + gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; else gamma_mode |= GAMMA_MODE_MODE_10BIT; @@ -1755,7 +1913,7 @@ void intel_color_init(struct intel_crtc *crtc) drm_color_add_gamma_mode_range(&dev_priv->drm, "8bit gamma", - i9xx_gamma_8, + i9xx_gamma_8, sizeof(i9xx_gamma_8)); drm_color_add_gamma_mode_range(&dev_priv->drm, "10bit gamma", @@ -1798,8 +1956,8 @@ void intel_color_init(struct intel_crtc *crtc) drm_color_add_gamma_mode_range(&dev_priv->drm, "8bit gamma or degamma", - ilk_gamma_degamma_8, - sizeof(ilk_gamma_degamma_8)); + ilk_gamma_degamma_8, + sizeof(ilk_gamma_degamma_8)); drm_color_add_gamma_mode_range(&dev_priv->drm, "10bit gamma or degamma", ilk_gamma_degamma_10, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f2e60bd..f789359 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -255,6 +255,9 @@ struct drm_crtc_state { */ u32 gamma_mode; + /* Gamma mode type programmed on the pipe */ + u32 gamma_mode_type; + /** * @degamma_lut: * From patchwork Fri Apr 12 10:21:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897787 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0DC9B1390 for ; Fri, 12 Apr 2019 09:55:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E212728E29 for ; Fri, 12 Apr 2019 09:55:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D69A828E2B; Fri, 12 Apr 2019 09:55:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 97DB328E29 for ; Fri, 12 Apr 2019 09:55:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02A49897C3; Fri, 12 Apr 2019 09:55:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1C58897C3; Fri, 12 Apr 2019 09:55:27 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350739" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:23 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:51:01 +0530 Message-Id: <1555064463-18479-6-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v3 5/7] drm/i915: Attach gamma mode property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Attach the gamma mode property to allow userspace set the gamma mode and provide the luts for the same. v2: Enabled just 1 property interface for gamma_mode, as suggested by Ville. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 3 +++ drivers/gpu/drm/i915/intel_display.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index d4ce1ed..edf5ff8 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -1884,6 +1884,9 @@ void intel_color_init(struct intel_crtc *crtc) } else { if (INTEL_GEN(dev_priv) >= 11) { dev_priv->display.color_check = icl_color_check; + + drm_crtc_attach_gamma_mode_property(&crtc->base); + /* don't advertize the >= 1.0 entries */ degamma_lut_size = 0; gamma_lut_size = ILK_LUT_SIZE_10BIT; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f29a348..3e47935 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15680,6 +15680,9 @@ int intel_modeset_init(struct drm_device *dev) INTEL_INFO(dev_priv)->num_pipes, INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); + if (INTEL_GEN(dev_priv) >= 11) + drm_color_create_gamma_mode_property(&dev_priv->drm, 4); + for_each_pipe(dev_priv, pipe) { ret = intel_crtc_init(dev_priv, pipe); if (ret) { From patchwork Fri Apr 12 10:21:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897793 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8A5DE1390 for ; Fri, 12 Apr 2019 09:55:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F5EE28E29 for ; Fri, 12 Apr 2019 09:55:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 639A528E2B; Fri, 12 Apr 2019 09:55:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A173428E29 for ; Fri, 12 Apr 2019 09:55:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A14EE898BC; Fri, 12 Apr 2019 09:55:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id A035E89875; Fri, 12 Apr 2019 09:55:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350750" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:27 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:51:02 +0530 Message-Id: <1555064463-18479-7-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v3 6/7] drm: Add Client Cap for advance gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Introduced a client cap for advance cap mode capability. Userspace should set this to get to be able to use the new gamma_mode property. If this is not set, driver will work in legacy mode. Suggested-by: Ville Syrjälä Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_uapi.c | 3 +++ drivers/gpu/drm/drm_ioctl.c | 5 +++++ include/drm/drm_atomic.h | 1 + include/drm/drm_crtc.h | 7 +++++++ include/drm/drm_file.h | 8 ++++++++ include/uapi/drm/drm.h | 2 ++ 6 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index d85e0c9..590c87a 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -974,6 +974,8 @@ int drm_atomic_set_property(struct drm_atomic_state *state, break; } + crtc_state->advance_gamma_mode_active = + state->advance_gamma_mode_active; ret = drm_atomic_crtc_set_property(crtc, crtc_state, prop, prop_value); break; @@ -1297,6 +1299,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); state->acquire_ctx = &ctx; state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET); + state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active; retry: copied_objs = 0; diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index d337f16..e593a4c 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -348,6 +348,11 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_ return -EINVAL; file_priv->writeback_connectors = req->value; break; + case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES: + if (req->value > 1) + return -EINVAL; + file_priv->advance_gamma_mode_active = req->value; + break; default: return -EINVAL; } diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 824a5ed..02c1a68 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -338,6 +338,7 @@ struct drm_atomic_state { * states. */ bool duplicated : 1; + bool advance_gamma_mode_active : 1; struct __drm_planes_state *planes; struct __drm_crtcs_state *crtcs; int num_connector; diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f789359..f11dc25 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -170,6 +170,11 @@ struct drm_crtc_state { bool color_mgmt_changed : 1; /** + * This is to indicate advance gamma mode support + */ + bool advance_gamma_mode_active : 1; + + /** * @no_vblank: * * Reflects the ability of a CRTC to send VBLANK events. This state @@ -952,6 +957,8 @@ struct drm_crtc { */ bool enabled; + bool advance_gamma_mode_active : 1; + /** * @mode: * diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index 6710b61..b5aa24e 100644 --- a/include/drm/drm_file.h +++ b/include/drm/drm_file.h @@ -201,6 +201,14 @@ struct drm_file { bool writeback_connectors; /** + * This is to enable advance gamma modes using + * gamma_mode property + * + * True if client understands advance gamma + */ + bool advance_gamma_mode_active : 1; + + /** * @is_master: * * This client is the creator of @master. Protected by struct diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 236b01a..abef966 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -696,6 +696,8 @@ struct drm_get_cap { */ #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6 + /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; From patchwork Fri Apr 12 10:21:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10897797 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D347117E0 for ; Fri, 12 Apr 2019 09:55:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B627F28E29 for ; Fri, 12 Apr 2019 09:55:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AA31528E2B; Fri, 12 Apr 2019 09:55:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 72FDE28E29 for ; Fri, 12 Apr 2019 09:55:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24919898D9; Fri, 12 Apr 2019 09:55:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9735F898C7; Fri, 12 Apr 2019 09:55:35 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 02:55:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,340,1549958400"; d="scan'208";a="315350763" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.121]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2019 02:55:31 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 12 Apr 2019 15:51:03 +0530 Message-Id: <1555064463-18479-8-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> References: <1555064463-18479-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v3 7/7] drm/i915: Enable advance gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, sam@ravnborg.org, seanpaul@chromium.org, ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Enable advance gamma modes based on client caps. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index edf5ff8..36604c16 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -926,8 +926,9 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == GAMMA_MODE_MODE_8BIT) { i9xx_load_luts(crtc_state); - } else if (crtc_state->base.gamma_mode_type == - MULTI_SEGMENTED_GAMMA_MODE_12BIT) { + } else if ((crtc_state->base.gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT) && + crtc_state->base.advance_gamma_mode_active) { icl_load_gamma_multi_segmented_lut(crtc_state, 0); } else { bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); @@ -1352,12 +1353,13 @@ static u32 icl_gamma_mode(struct intel_crtc_state *crtc_state) !crtc_state->c8_planes) gamma_mode |= POST_CSC_GAMMA_ENABLE; - if (!crtc_state->base.gamma_lut || - crtc_state_is_legacy_gamma(crtc_state)) - gamma_mode |= GAMMA_MODE_MODE_8BIT; - else if (crtc_state->base.gamma_mode_type == - MULTI_SEGMENTED_GAMMA_MODE_12BIT) + if (crtc_state->base.gamma_mode_type == + MULTI_SEGMENTED_GAMMA_MODE_12BIT && + crtc_state->base.advance_gamma_mode_active) gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; + else if (!crtc_state->base.gamma_lut || + crtc_state_is_legacy_gamma(crtc_state)) + gamma_mode |= GAMMA_MODE_MODE_8BIT; else gamma_mode |= GAMMA_MODE_MODE_10BIT;