From patchwork Sat Apr 13 15:38:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 10899481 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8E07186E for ; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C92E328BAA for ; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD84628CEA; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3B19D28BB4 for ; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tG2Dn7zXxdar5abBYQ6YeWZuPX4viBY/d/aQ6pgpZ7A=; b=mSFuxCc+H9osH/ 83N/Gkeh6sN0tkbLnzAFCkYCcKanYcRZde8jXgNnuwoYIolL7KIjAj3vi7tj2kTq1ymjkP4n0xBhC VAn9jJyflqsBz9Y4Zr+GRLJfhv6sm6HpESgk/LUlf2FyydatU2gcMlWyg69PVG/4QyYT75yOMq1pl x/JCsdam5pIyI38a+hou3cWVO87EwKOzVqK9AgliRgtWGITK8CkqtYphE/unTsbv09D5hQolzERhK WEfSwwqFMz6bjCytaEgPooCAc0H3yReXkA2uIWRlGpEA2wi9ghluskAHoeZ4TvgsbO0Eu3fZdODOS UQW8Q36+HUCBHNK9/CxA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFKk0-00007F-T3; Sat, 13 Apr 2019 15:38:52 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFKjy-0008VV-A0 for linux-riscv@lists.infradead.org; Sat, 13 Apr 2019 15:38:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1555170017; x=1586706017; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=4tHpfIdvi6qydRvKMDWyV6PYnG4LFA/c15iKLM1Fzss=; b=ZrYJdbtRVpNMg0saEnJ5metQMBBJ/LPmf8FEIo1sEPzy0x0vGEVIT5xs 9n1CJ7S/AP4jvLSn+T8jntp1aGWO17JU/rT77pbrFxPCRb7J+vMQS8xLX LtwQjB3Rx041O3dmRuH8Y5Xlg1lf+FX7nptsCx2Q32MHXwPbzzQmW46Pf tVBjlrdD6MPYs4N4thAiE6D+WNnvNsy4bpl+m1gE9tgvlt380Cgg++Uyn a2YeOA35jgQ8i/BXQloD7gffSfP3qwYsRC73sXqj+eLJwLSFHOJDiJOFV uqxGTu0YsFoIS09kyXP54dKn6Sh8hvSiHwx30rqXgP4d60tqJUq1fAxam w==; X-IronPort-AV: E=Sophos;i="5.60,345,1549900800"; d="scan'208";a="204828661" Received: from mail-bl2nam02lp2055.outbound.protection.outlook.com (HELO NAM02-BL2-obe.outbound.protection.outlook.com) ([104.47.38.55]) by ob1.hgst.iphmx.com with ESMTP; 13 Apr 2019 23:39:58 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector1-wdc-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4tHpfIdvi6qydRvKMDWyV6PYnG4LFA/c15iKLM1Fzss=; b=KovqMYxRCcWtxpXiAJ91DTTg4QaYjSXPiPf6ygQviRjDgR5amP09182JGU6HFKslrPmqRLuCsEWHPK2moo2XwQeOHbqGl+lyfnYgbYH9GNcmDlFaI1D+RyNcqxPZm3Iu2ny+3bTklU5+5Qxashc2I+iV2D2iEqYHYfNxnYIN+ks= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5501.namprd04.prod.outlook.com (20.178.245.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.17; Sat, 13 Apr 2019 15:38:35 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::ad2f:3a0f:2de1:6fb2]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::ad2f:3a0f:2de1:6fb2%5]) with mapi id 15.20.1792.018; Sat, 13 Apr 2019 15:38:35 +0000 From: Anup Patel To: Palmer Dabbelt , Albert Ou Subject: [PATCH v2 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Thread-Topic: [PATCH v2 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Thread-Index: AQHU8g7103phegeQY0uauk1U9R6nkg== Date: Sat, 13 Apr 2019 15:38:35 +0000 Message-ID: <20190413153807.116227-2-anup.patel@wdc.com> References: <20190413153807.116227-1-anup.patel@wdc.com> In-Reply-To: <20190413153807.116227-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR0101CA0032.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::18) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.17.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d856da29-0045-4588-4d39-08d6c0261766 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB5501; x-ms-traffictypediagnostic: MN2PR04MB5501: wdcipoutbound: EOP-TRUE x-microsoft-antispam-prvs: x-forefront-prvs: 00064751B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(39860400002)(376002)(396003)(136003)(346002)(366004)(199004)(189003)(2906002)(71190400001)(71200400001)(97736004)(50226002)(1076003)(186003)(68736007)(102836004)(8936002)(6486002)(86362001)(110136005)(54906003)(316002)(9456002)(78486014)(55236004)(4326008)(81166006)(81156014)(6506007)(386003)(5660300002)(26005)(8676002)(36756003)(105586002)(44832011)(106356001)(14444005)(256004)(76176011)(3846002)(14454004)(478600001)(72206003)(6116002)(52116002)(6512007)(25786009)(99286004)(53936002)(11346002)(446003)(486006)(2171002)(66066001)(7736002)(6436002)(476003)(305945005)(2616005); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5501; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +cApNlaprpSNpdpfy/jj43atMEcryZ3KbCk8sjdOF3f1lS76Obsn1IxHOLNN3SwmLrWMRBs/Ud2A+9HV91YQ2tTwP46D2+EH/jMWbDOUf+W1BmQuQp5sWszdGKv0BHDxit2n02e4x5LtmTuSplub9mK5bdIOemUBTVtu/4KPQUfSdtg0EFfCbsRTZTThmDoQn2fIMPKjOJm50c6fQkaPnNjRWU4fmQip2XRuqZnlWjLft2HKEwycoZMogrkQIo2jsy9IFaU5PL0vQ7ilLQzz9VTlYENLZPc1tQ/nsmmio81oo2UaWYvjagfoFTGlaVJN6waOWKL3l05HBgj75ujyi0lI6qyeRxy7su+9hw+GoNUXhWqqRXI08jxU56935NpFVTefpGegWPXCjVX6Oz/sfTOI5/D8y4sqUKrCFO37Xf0= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d856da29-0045-4588-4d39-08d6c0261766 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Apr 2019 15:38:35.6556 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5501 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190413_083850_453060_9DFE34E4 X-CRM114-Status: GOOD ( 16.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Paul Walmsley , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP It's better to have all RISC-V spec related defines in one place so this patch adds separate asm/encoding.h for such defines which can be included in assembly as well as C code. Signed-off-by: Anup Patel --- arch/riscv/include/asm/csr.h | 52 +------------------------- arch/riscv/include/asm/encoding.h | 62 +++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 51 deletions(-) create mode 100644 arch/riscv/include/asm/encoding.h diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 28a0d1cb374c..8cf698e39463 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -14,57 +14,7 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H -#include - -/* Status register flags */ -#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ -#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ -#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ -#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ - -#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ -#define SR_FS_OFF _AC(0x00000000, UL) -#define SR_FS_INITIAL _AC(0x00002000, UL) -#define SR_FS_CLEAN _AC(0x00004000, UL) -#define SR_FS_DIRTY _AC(0x00006000, UL) - -#define SR_XS _AC(0x00018000, UL) /* Extension Status */ -#define SR_XS_OFF _AC(0x00000000, UL) -#define SR_XS_INITIAL _AC(0x00008000, UL) -#define SR_XS_CLEAN _AC(0x00010000, UL) -#define SR_XS_DIRTY _AC(0x00018000, UL) - -#ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ -#else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ -#endif - -/* SATP flags */ -#if __riscv_xlen == 32 -#define SATP_PPN _AC(0x003FFFFF, UL) -#define SATP_MODE_32 _AC(0x80000000, UL) -#define SATP_MODE SATP_MODE_32 -#else -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE SATP_MODE_39 -#endif - -/* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ - -#define EXC_INST_MISALIGNED 0 -#define EXC_INST_ACCESS 1 -#define EXC_BREAKPOINT 3 -#define EXC_LOAD_ACCESS 5 -#define EXC_STORE_ACCESS 7 -#define EXC_SYSCALL 8 -#define EXC_INST_PAGE_FAULT 12 -#define EXC_LOAD_PAGE_FAULT 13 -#define EXC_STORE_PAGE_FAULT 15 +#include #ifndef __ASSEMBLY__ diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h new file mode 100644 index 000000000000..29699705dc36 --- /dev/null +++ b/arch/riscv/include/asm/encoding.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Regents of the University of California + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_ENCODING_H +#define _ASM_RISCV_ENCODING_H + +#include + +/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) + +#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif + +/* SATP flags */ +#ifndef CONFIG_64BIT +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#endif + +/* Interrupt Enable and Interrupt Pending flags */ +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ +#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ + +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 + +#endif /* _ASM_RISCV_ENCODING_H */ From patchwork Sat Apr 13 15:38:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 10899479 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E31717E0 for ; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1023928BAA for ; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 037F728CEA; Sat, 13 Apr 2019 15:38:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91E9328BAA for ; Sat, 13 Apr 2019 15:38:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=elHQEvkEYV6iuHwv/uiwbSwQKFXf8sVt3N5IMv+abHI=; b=C1hPtxBPKYtnDA P+IYEjENQ0zh344LY/xX/mFrcTM8PL5bysAdMVZ3aXSg6IVeOIpt5eG6TJzPpg2fnrZeap/FG/mrg Ap5loLPcZBUZOLGHq5tOqgMQwBh7tIwNvzTxFkzDYIF5VFBg+QLPfIfBdL4atVrvKcJXcNdZx4mCd XNTc2T8jvAIKJFbhD9NysN5SiIuxT2ycRg2HDNXjU1PhcfdXC6kx7eh5sGWG1AjqVn5ajVl0IuLXZ 9EZbw7aWmERu37cOJQmDnrLXKR/aDY7b6U/tkk+Y1lBjoa5PzUuSkf0NyOLvuzfiM+SswaSJPOqBI l5RWLAWMbjcvP3YhEGlQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFKk1-00008N-Ro; Sat, 13 Apr 2019 15:38:53 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFKjy-0008Vx-Or for linux-riscv@lists.infradead.org; Sat, 13 Apr 2019 15:38:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1555170018; x=1586706018; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=T9yFNNImO8CfkqoFA0/qVcPa2wZJQfUTQnvM/Z+JMQs=; b=l8asCIdFXAVxHH+joUx/BKxo6+mFEYbFKM2KbezUs/bP7uxunjLL7ycD r2TlS1W6B8IYFm18yCvhvip52EXut4O/HQnSSRZDhysNMEKI0rbMhzNUC KKKpv0InMqqMRxJLW3geYp9bm3cqzupi8x1DeObBvA23Am8Jx4SFW4jgW efXFPvCJOQIUNJdMgoZdoWxIr4g7aA00Czuh/pRqH38R904AcTDhKVRYc HIUwD/YHa7WR8LNjDKEcVbdNhhRmVGWisSa7dq3GwFZ2DvriQTaohiJe4 Jfnk/ENTHW7uBe5eyrTR7Rz37HxcfU1VsF8LQndpgvitvAKDbYOUZksxF w==; X-IronPort-AV: E=Sophos;i="5.60,345,1549900800"; d="scan'208";a="204828673" Received: from mail-bl2nam02lp2052.outbound.protection.outlook.com (HELO NAM02-BL2-obe.outbound.protection.outlook.com) ([104.47.38.52]) by ob1.hgst.iphmx.com with ESMTP; 13 Apr 2019 23:40:05 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector1-wdc-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=T9yFNNImO8CfkqoFA0/qVcPa2wZJQfUTQnvM/Z+JMQs=; b=T+DacslAw7B0kZIzp5yro9u40stmtM5k+LUbRS3hdFtEunxp0NR9naTKKh4gTFIJ8NB3C9rzx93uZnj6/Qr8KfTbdaka0jSVkWu9lADvJii6YOXwfJZZP02Jb3F+Fl+oA6QTrwM/SJerMyR0W6m5qQ0eJxier9IwYcFxU1MY9a4= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5501.namprd04.prod.outlook.com (20.178.245.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.17; Sat, 13 Apr 2019 15:38:40 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::ad2f:3a0f:2de1:6fb2]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::ad2f:3a0f:2de1:6fb2%5]) with mapi id 15.20.1792.018; Sat, 13 Apr 2019 15:38:40 +0000 From: Anup Patel To: Palmer Dabbelt , Albert Ou Subject: [PATCH v2 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/encoding.h Thread-Topic: [PATCH v2 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/encoding.h Thread-Index: AQHU8g739Jygn8R9+UOEL40FVTFlWw== Date: Sat, 13 Apr 2019 15:38:39 +0000 Message-ID: <20190413153807.116227-3-anup.patel@wdc.com> References: <20190413153807.116227-1-anup.patel@wdc.com> In-Reply-To: <20190413153807.116227-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR0101CA0032.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::18) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.17.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 73cf40a5-6a82-4f21-fceb-08d6c02619f5 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB5501; x-ms-traffictypediagnostic: MN2PR04MB5501: wdcipoutbound: EOP-TRUE x-microsoft-antispam-prvs: x-forefront-prvs: 00064751B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(39860400002)(376002)(396003)(136003)(346002)(366004)(199004)(189003)(2906002)(71190400001)(71200400001)(97736004)(50226002)(1076003)(186003)(68736007)(102836004)(8936002)(6486002)(86362001)(110136005)(54906003)(316002)(9456002)(78486014)(55236004)(4326008)(81166006)(81156014)(6506007)(386003)(5660300002)(26005)(8676002)(36756003)(105586002)(44832011)(106356001)(14444005)(256004)(76176011)(3846002)(14454004)(478600001)(72206003)(6116002)(52116002)(6512007)(25786009)(99286004)(53936002)(11346002)(446003)(486006)(2171002)(66066001)(7736002)(6436002)(476003)(305945005)(2616005); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5501; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +VEvovHbr6wOc2u9D0yD1PKGkzDldeGFnMbK9RZwZBOay4vx0/3eB6+KlO2lwJdUhztWs3esS+nON9kmWGfVfTF7AEbmOndQKBYfgXOVbGDZy3fksWKd06YNOOWST7UCxRdvuhcIXgVLLbV/5j1QIaVthQbBlotOy1uGj0/Q++4scfQQnm634JPe57YWcThdYZvwNxzRXc6yciQC1/RQ4XilETbd/ulIkZSQZRD1WiSWayrdJZAhbI7gYCfIPjn++W/lrNQQJ6N8M1m953gpsbxFa25vsoev+soSyMKkxBqFDT6O2s/xXolp4klWgXJtVfISd6AYRpOm52Mu868OYbaVZbI5NuY9eocvnMU9wxhHgIijpRehA0Uvvgrzxd91bsjnYeNle+ISsYgROOk88cdjz6s5k3/7g/UNIFa2ZgI= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 73cf40a5-6a82-4f21-fceb-08d6c02619f5 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Apr 2019 15:38:39.9968 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5501 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190413_083850_929033_067E0FDA X-CRM114-Status: GOOD ( 15.32 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Paul Walmsley , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds SCAUSE interrupt flag and SCAUSE interrupt cause related defines to asm/encoding.h. We also use these defines in arch/riscv/kernel/irq.c and express SIE/SIP flag in-terms of interrupt causes. Signed-off-by: Anup Patel --- arch/riscv/include/asm/encoding.h | 25 +++++++++++++++++++++---- arch/riscv/kernel/irq.c | 9 +++++---- 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 29699705dc36..4f187854fd8b 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -44,10 +44,22 @@ #define SATP_MODE SATP_MODE_39 #endif -/* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ +/* SCAUSE */ +#ifdef CONFIG_64BIT +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) +#else +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) +#endif + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_M_EXT 11 #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 @@ -59,4 +71,9 @@ #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ +#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) +#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) +#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) + #endif /* _ASM_RISCV_ENCODING_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 48e6b7db83a1..22b8183ae8d4 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -9,14 +9,15 @@ #include #include #include +#include #include /* * Possible interrupt causes: */ -#define INTERRUPT_CAUSE_SOFTWARE 1 -#define INTERRUPT_CAUSE_TIMER 5 -#define INTERRUPT_CAUSE_EXTERNAL 9 +#define INTERRUPT_CAUSE_SOFTWARE IRQ_S_SOFT +#define INTERRUPT_CAUSE_TIMER IRQ_S_TIMER +#define INTERRUPT_CAUSE_EXTERNAL IRQ_S_EXT /* * The high order bit of the trap cause register is always set for @@ -24,7 +25,7 @@ * quickly. The INTERRUPT_CAUSE_* macros don't contain that bit, so we * need to mask it off. */ -#define INTERRUPT_CAUSE_FLAG (1UL << (__riscv_xlen - 1)) +#define INTERRUPT_CAUSE_FLAG SCAUSE_IRQ_FLAG int arch_show_interrupts(struct seq_file *p, int prec) { From patchwork Sat Apr 13 15:38:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 10899483 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 306281669 for ; Sat, 13 Apr 2019 15:39:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F6C628BAA for ; Sat, 13 Apr 2019 15:39:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0330F28CEA; Sat, 13 Apr 2019 15:38:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2E09D28BAA for ; Sat, 13 Apr 2019 15:38:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Itds4L5izBzmlsv0qzjqRkm8uAGRH/hnqBgZ34gWD+g=; b=W/V3UjpOQY6FMa YjoTmELc8Bp9jD9N0kp1qoOCjEqvEfrHz3p2GYD26DD47ij5UjY58x1LRlpXGptY7ptJtXTOqF45S 1AfUNzLiJFlbA2ksAYBLiuU8OIm7ZYl+of6nPPEaIYKWhsxOEnKf6bX1ccA7yornxLoVkCl+44zM1 msvoNNOpv3Xz33wZEk9bz448GmjxsSZvOYmyXBPwIPgh+LMIBUTYMPUtnrmtkYRvDABJpPJk87LvO Kndf1YMC6301Mk682q0qhAVzVkK0ZwlfgDntk+kEJchN4QqWF87GZh0IP/ZK1nWMJ9/QR9JAL2Gmr LCX6HUaRLkt9HcqFTMWA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFKk4-0000Bi-2N; Sat, 13 Apr 2019 15:38:56 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hFKjz-0008VV-Uq for linux-riscv@lists.infradead.org; Sat, 13 Apr 2019 15:38:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1555170020; x=1586706020; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=gLQaYrZDbmZxISGuDP2UpELMy5uEAPTKXvFE6eaNs7o=; b=TjxKIerPjn90zR8NKXXlwCSMdWKJfXG8qJjRhT5rBipDRZABylm39Yml oIEzXyGKqZEdHH7ZKN9b+Zi9AGhlvGDZsHQENEhNgNBRK3NS4bV6kWrlz ds339LYgzFBqw1Pc2o4kbZTM1RKfyXfOCQBEvxqCZYPHjoT2nEBZZJ+0+ 3aWllYmr2cxbgxqMAkKPr4cK5fv3dKvulP1vE/1/nVJ9wNXv4vhXjb+eZ P2OyZTw6xLyUs+9/T59JE142SGoK4jE0QxWr4TtBryrw/NvrbiIADQqen 96HtFkjKBflJhSz07q8hUUXtXabJRobRqg18QfVxFkHkS+kcocdzV17xB g==; X-IronPort-AV: E=Sophos;i="5.60,345,1549900800"; d="scan'208";a="204828675" Received: from mail-bl2nam02lp2055.outbound.protection.outlook.com (HELO NAM02-BL2-obe.outbound.protection.outlook.com) ([104.47.38.55]) by ob1.hgst.iphmx.com with ESMTP; 13 Apr 2019 23:40:11 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector1-wdc-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gLQaYrZDbmZxISGuDP2UpELMy5uEAPTKXvFE6eaNs7o=; b=boRjrTZmbRlzbsPaLG4QyUhiI4bnozgsKY8swxzi5L4s4gWjcf8j5cM+gzfJOY/uOFgJDqeImrR3sUHj/7krsgV7pisi29MlIjdaYPbMcrlycu1m02fS2+fa52gXzlheW6GWkuaYZd3RqXSCTaq+yrVa9QnWes01oqxp6qg4Zjg= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5501.namprd04.prod.outlook.com (20.178.245.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.17; Sat, 13 Apr 2019 15:38:44 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::ad2f:3a0f:2de1:6fb2]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::ad2f:3a0f:2de1:6fb2%5]) with mapi id 15.20.1792.018; Sat, 13 Apr 2019 15:38:44 +0000 From: Anup Patel To: Palmer Dabbelt , Albert Ou Subject: [PATCH v2 3/3] RISC-V: Access CSRs using CSR numbers Thread-Topic: [PATCH v2 3/3] RISC-V: Access CSRs using CSR numbers Thread-Index: AQHU8g76UV2mHqgJqEKGaOYNUpxpNQ== Date: Sat, 13 Apr 2019 15:38:44 +0000 Message-ID: <20190413153807.116227-4-anup.patel@wdc.com> References: <20190413153807.116227-1-anup.patel@wdc.com> In-Reply-To: <20190413153807.116227-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR0101CA0032.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::18) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.17.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: aeb05068-8e37-4d5b-5137-08d6c0261c63 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB5501; x-ms-traffictypediagnostic: MN2PR04MB5501: wdcipoutbound: EOP-TRUE x-microsoft-antispam-prvs: x-forefront-prvs: 00064751B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(39860400002)(376002)(396003)(136003)(346002)(366004)(199004)(189003)(2906002)(71190400001)(71200400001)(97736004)(50226002)(1076003)(186003)(68736007)(102836004)(8936002)(6486002)(86362001)(110136005)(54906003)(316002)(9456002)(78486014)(55236004)(4326008)(30864003)(81166006)(81156014)(6506007)(386003)(5660300002)(26005)(8676002)(36756003)(105586002)(44832011)(106356001)(14444005)(256004)(76176011)(3846002)(14454004)(478600001)(72206003)(6116002)(52116002)(6512007)(25786009)(99286004)(53936002)(11346002)(446003)(486006)(2171002)(66066001)(7736002)(6436002)(476003)(305945005)(2616005); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5501; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: VoGCM/RhGT5y+FbUq8/rBorn11P19OS5kEwYHTPYr4LWrV1CrXxrGtU2wAfL/XBDPk/OE5LQqfjq6Lzs7S/fpPs1gRMjcGv4ez7MDVEAx8YVt9rMUdj1zMXp+1jQ3NY4/rzQXn2ABAN8X0vIIJzeY80rvNVK//F0tzI9FXqh5bY2yasxtFfWzmLtI5LkWR9sh+U4tBEtLiqU4KqVSkyoDlzatBzThcTL1VRZnNo1HmiUbVU/tuXddMMIPWaWb0vZTxi0e/Z+TRjtnnzo9BfGKwdqFemNRopdn+X/zw9c/r0wBikWEivVVThe7r202EBpdFA8vxfjRkJpMt4Q04T8g8cufsnLEvOb2f7iPwYcDMFi6/66AXWf92D/ZIxTmL4/Z6/DNfVmm0HnUyoMLq5aUZUjMySkxERuU5owLcjjOgQ= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: aeb05068-8e37-4d5b-5137-08d6c0261c63 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Apr 2019 15:38:44.0447 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5501 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190413_083852_111378_D4D1E031 X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Paul Walmsley , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. Signed-off-by: Anup Patel --- arch/riscv/include/asm/csr.h | 15 ++++++++------- arch/riscv/include/asm/encoding.h | 16 ++++++++++++++++ arch/riscv/include/asm/irqflags.h | 10 +++++----- arch/riscv/include/asm/mmu_context.h | 7 +------ arch/riscv/kernel/entry.S | 22 +++++++++++----------- arch/riscv/kernel/head.S | 12 ++++++------ arch/riscv/kernel/perf_event.c | 4 ++-- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/traps.c | 6 +++--- arch/riscv/mm/fault.c | 6 +----- 10 files changed, 54 insertions(+), 46 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 8cf698e39463..6bf5652d3565 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -14,6 +14,7 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H +#include #include #ifndef __ASSEMBLY__ @@ -21,7 +22,7 @@ #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -30,7 +31,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -39,7 +40,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -47,7 +48,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -56,7 +57,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -64,7 +65,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -73,7 +74,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 4f187854fd8b..717b823ac110 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -76,4 +76,20 @@ #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 + #endif /* _ASM_RISCV_ENCODING_H */ diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 07a3c6d5706f..1a69b3bcd371 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -21,25 +21,25 @@ /* read interrupt enabled status */ static inline unsigned long arch_local_save_flags(void) { - return csr_read(sstatus); + return csr_read(CSR_SSTATUS); } /* unconditionally enable interrupts */ static inline void arch_local_irq_enable(void) { - csr_set(sstatus, SR_SIE); + csr_set(CSR_SSTATUS, SR_SIE); } /* unconditionally disable interrupts */ static inline void arch_local_irq_disable(void) { - csr_clear(sstatus, SR_SIE); + csr_clear(CSR_SSTATUS, SR_SIE); } /* get status and disable interrupts */ static inline unsigned long arch_local_irq_save(void) { - return csr_read_clear(sstatus, SR_SIE); + return csr_read_clear(CSR_SSTATUS, SR_SIE); } /* test flags */ @@ -57,7 +57,7 @@ static inline int arch_irqs_disabled(void) /* set interrupt enabled status */ static inline void arch_local_irq_restore(unsigned long flags) { - csr_set(sstatus, flags & SR_SIE); + csr_set(CSR_SSTATUS, flags & SR_SIE); } #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index 336d60ec5698..98c76c821367 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -83,12 +83,7 @@ static inline void switch_mm(struct mm_struct *prev, cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_set_cpu(cpu, mm_cpumask(next)); - /* - * Use the old spbtr name instead of using the current satp - * name to support binutils 2.29 which doesn't know about the - * privileged ISA 1.10 yet. - */ - csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); + csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); flush_icache_deferred(next); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index fd9b57c8b4ce..1c1ecc238cfa 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -37,11 +37,11 @@ * the kernel thread pointer. If we came from the kernel, sscratch * will contain 0, and we should continue on the current TP. */ - csrrw tp, sscratch, tp + csrrw tp, CSR_SSCRATCH, tp bnez tp, _save_context _restore_kernel_tpsp: - csrr tp, sscratch + csrr tp, CSR_SSCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) _save_context: REG_S sp, TASK_TI_USER_SP(tp) @@ -87,11 +87,11 @@ _save_context: li t0, SR_SUM | SR_FS REG_L s0, TASK_TI_USER_SP(tp) - csrrc s1, sstatus, t0 - csrr s2, sepc - csrr s3, sbadaddr - csrr s4, scause - csrr s5, sscratch + csrrc s1, CSR_SSTATUS, t0 + csrr s2, CSR_SEPC + csrr s3, CSR_STVAL + csrr s4, CSR_SCAUSE + csrr s5, CSR_SSCRATCH REG_S s0, PT_SP(sp) REG_S s1, PT_SSTATUS(sp) REG_S s2, PT_SEPC(sp) @@ -107,8 +107,8 @@ _save_context: .macro RESTORE_ALL REG_L a0, PT_SSTATUS(sp) REG_L a2, PT_SEPC(sp) - csrw sstatus, a0 - csrw sepc, a2 + csrw CSR_SSTATUS, a0 + csrw CSR_SEPC, a2 REG_L x1, PT_RA(sp) REG_L x3, PT_GP(sp) @@ -155,7 +155,7 @@ ENTRY(handle_exception) * Set sscratch register to 0, so that if a recursive exception * occurs, the exception vector knows it came from the kernel */ - csrw sscratch, x0 + csrw CSR_SSCRATCH, x0 /* Load the global pointer */ .option push @@ -248,7 +248,7 @@ resume_userspace: * Save TP into sscratch, so we can find the kernel data structures * again. */ - csrw sscratch, tp + csrw CSR_SSCRATCH, tp restore_all: RESTORE_ALL diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index fe884cd69abd..041492636b45 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -23,7 +23,7 @@ __INIT ENTRY(_start) /* Mask all interrupts */ - csrw sie, zero + csrw CSR_SIE, zero /* Load the global pointer */ .option push @@ -89,7 +89,7 @@ relocate: /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Compute satp for kernel page tables, but don't load it yet */ la a2, swapper_pg_dir @@ -105,12 +105,12 @@ relocate: srl a0, a0, PAGE_SHIFT or a0, a0, a1 sfence.vma - csrw sptbr, a0 + csrw CSR_SATP, a0 .align 2 1: /* Set trap vector to spin forever to help debug */ la a0, .Lsecondary_park - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Reload the global pointer */ .option push @@ -119,7 +119,7 @@ relocate: .option pop /* Switch to kernel page tables */ - csrw sptbr, a2 + csrw CSR_SATP, a2 ret @@ -130,7 +130,7 @@ relocate: /* Set trap vector to spin forever to help debug */ la a3, .Lsecondary_park - csrw stvec, a3 + csrw CSR_STVEC, a3 slli a3, a0, LGREG la a1, __cpu_up_stack_pointer diff --git a/arch/riscv/kernel/perf_event.c b/arch/riscv/kernel/perf_event.c index 667ee70defea..91626d9ae5f2 100644 --- a/arch/riscv/kernel/perf_event.c +++ b/arch/riscv/kernel/perf_event.c @@ -185,10 +185,10 @@ static inline u64 read_counter(int idx) switch (idx) { case RISCV_PMU_CYCLE: - val = csr_read(cycle); + val = csr_read(CSR_CYCLE); break; case RISCV_PMU_INSTRET: - val = csr_read(instret); + val = csr_read(CSR_INSTRET); break; default: WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 0c41d07ec281..f244c63d29e4 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,7 +89,7 @@ void riscv_software_interrupt(void) unsigned long *stats = ipi_data[smp_processor_id()].stats; /* Clear pending IPI */ - csr_clear(sip, SIE_SSIE); + csr_clear(CSR_SIP, SIE_SSIE); while (true) { unsigned long ops; diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 24a9333dda2c..1b407a9db3fc 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -159,9 +159,9 @@ void __init trap_init(void) * Set sup0 scratch register to 0, indicating to exception vector * that we are presently executing in the kernel */ - csr_write(sscratch, 0); + csr_write(CSR_SSCRATCH, 0); /* Set the exception vector address */ - csr_write(stvec, &handle_exception); + csr_write(CSR_STVEC, &handle_exception); /* Enable all interrupts */ - csr_write(sie, -1); + csr_write(CSR_SIE, -1); } diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 88401d5125bc..26293bc053a8 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -239,13 +239,9 @@ asmlinkage void do_page_fault(struct pt_regs *regs) * Do _not_ use "tsk->active_mm->pgd" here. * We might be inside an interrupt in the middle * of a task switch. - * - * Note: Use the old spbtr name instead of using the current - * satp name to support binutils 2.29 which doesn't know about - * the privileged ISA 1.10 yet. */ index = pgd_index(addr); - pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index; + pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index; pgd_k = init_mm.pgd + index; if (!pgd_present(*pgd_k))