From patchwork Tue Apr 16 14:15:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10903203 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84FC6139A for ; Tue, 16 Apr 2019 14:15:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F73728644 for ; Tue, 16 Apr 2019 14:15:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DCBF28A54; Tue, 16 Apr 2019 14:15:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA54C28644 for ; Tue, 16 Apr 2019 14:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729432AbfDPOPo (ORCPT ); Tue, 16 Apr 2019 10:15:44 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13474 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728149AbfDPOPo (ORCPT ); Tue, 16 Apr 2019 10:15:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Apr 2019 07:15:48 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Apr 2019 07:15:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Apr 2019 07:15:43 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 14:15:43 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 14:15:42 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 16 Apr 2019 14:15:42 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 16 Apr 2019 07:15:42 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , Subject: [PATCH V2 1/2] PCI: dwc: Add API support to de-initialize host Date: Tue, 16 Apr 2019 19:45:15 +0530 Message-ID: <20190416141516.23908-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190416141516.23908-1-vidyas@nvidia.com> References: <20190416141516.23908-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555424148; bh=pUiFP+Z9LUBBzgUJW1rnX/SXb+8V4muvYp1eB4jsEtg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=fg1RGE9xoQ2oe4tMXsgFMnsgzyPXVR5wLv+Am8ACyHGg5oHawHPGuvSdwBCdJlcwS R/vEU7L+GDw3iuGN9JFr2OuTGOJCojuErdElzXuUieoECL3NsBTbg52WY2z4tjk/Jv 2KNBzSNtkFSbyRwViKk89RTFk36Fbn2uqDc0h/jF6UfnN/nWZHQQqr0SfwlfOmFKNt jeA7t677o04utHVXdx0v5/ZddJWSdAw7LBOp6e7y/CfOu4wzr2i+ItnX9uUZytdNlW 9itqJQ1U49yb79hClgI3tpQflopKrCSoJXautbi62JUSQLbz/Q4rdOyz4vA4uEwKjq WBLiTd7BmNRtg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an API to group all the tasks to be done to de-initialize host which can then be called by any DesignWare core based driver implementations while adding .remove() support in their respective drivers. Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel --- v2: * s/Designware/DesignWare drivers/pci/controller/dwc/pcie-designware-host.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e4169e738a5..d7881490282d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -516,6 +516,13 @@ int dw_pcie_host_init(struct pcie_port *pp) return ret; } +void dw_pcie_host_deinit(struct pcie_port *pp) +{ + pci_stop_root_bus(pp->root_bus); + pci_remove_root_bus(pp->root_bus); + dw_pcie_free_msi(pp); +} + static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val, bool write) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index adff0c713665..ea8d1caf11c5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -343,6 +343,7 @@ void dw_pcie_msi_init(struct pcie_port *pp); void dw_pcie_free_msi(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) @@ -367,6 +368,10 @@ static inline int dw_pcie_host_init(struct pcie_port *pp) return 0; } +static inline void dw_pcie_host_deinit(struct pcie_port *pp) +{ +} + static inline int dw_pcie_allocate_domains(struct pcie_port *pp) { return 0; From patchwork Tue Apr 16 14:15:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10903205 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 379BE139A for ; Tue, 16 Apr 2019 14:15:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21E6C28A57 for ; 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Tue, 16 Apr 2019 07:15:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 16 Apr 2019 07:15:47 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 16 Apr 2019 07:15:47 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 14:15:47 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 16 Apr 2019 14:15:47 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 16 Apr 2019 07:15:47 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , Subject: [PATCH V2 2/2] PCI: dwc: Export APIs to support .remove() implementation Date: Tue, 16 Apr 2019 19:45:16 +0530 Message-ID: <20190416141516.23908-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190416141516.23908-1-vidyas@nvidia.com> References: <20190416141516.23908-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555424153; bh=FklILXYubYDMOwPRavR4AFJsqhNEpF0c8+8KX8MTQG0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=WH++pXQYwOOaEKWxskJQxCfRJKClo6Z9FjEj7yTOO139/J92L7Qtr/Wx6iP8vjmLb L6lAlysoUE7vDMry6JqfWQcJhv8/dVPkmZFB4HDePtJOX0iPzcx9JxIqZqUBJyaGF6 5s27ng7q68Uerj9H2Bv7+Xw906fInNF3DduNkfWozg4NXBoGo/mPHQqOumn/81kLpz +ZNk3Co2nLklvWFnmnySMfUBqMVzyMChYGjM8nHAIuPl/VpF+O+suxKkhKtn1r7XOh 7uXWdN/u61EWWgk87+8WB4X9TvxS6uRdEA1F5FXZNKSPO1lTvyf5RLRtToXGsJ7ct9 JuoIYwRl3jefg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Export all configuration space access APIs and also other APIs to support host controller drivers of DesignWare core based implementations while adding support for .remove() hook to build their respective drivers as modules Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel --- v2: * s/Designware/DesignWare .../pci/controller/dwc/pcie-designware-host.c | 4 ++ drivers/pci/controller/dwc/pcie-designware.c | 38 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 35 +++-------------- 3 files changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d7881490282d..2a5332e5ccfa 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -333,6 +333,7 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, upper_32_bits(msi_target)); } +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); int dw_pcie_host_init(struct pcie_port *pp) { @@ -515,6 +516,7 @@ int dw_pcie_host_init(struct pcie_port *pp) dw_pcie_free_msi(pp); return ret; } +EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { @@ -522,6 +524,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp) pci_remove_root_bus(pp->root_bus); dw_pcie_free_msi(pp); } +EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val, @@ -731,3 +734,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); } +EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 31f6331ca46f..f98e2f284ae1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -40,6 +40,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_SUCCESSFUL; } +EXPORT_SYMBOL_GPL(dw_pcie_read); int dw_pcie_write(void __iomem *addr, int size, u32 val) { @@ -57,6 +58,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } +EXPORT_SYMBOL_GPL(dw_pcie_write); u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) @@ -89,6 +91,42 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "Write DBI address failed\n"); } +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) +{ + __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val); +} +EXPORT_SYMBOL_GPL(dw_pcie_writel_dbi); + +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) +{ + return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4); +} +EXPORT_SYMBOL_GPL(dw_pcie_readl_dbi); + +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) +{ + __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val); +} +EXPORT_SYMBOL_GPL(dw_pcie_writew_dbi); + +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) +{ + return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2); +} +EXPORT_SYMBOL_GPL(dw_pcie_readw_dbi); + +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) +{ + __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val); +} +EXPORT_SYMBOL_GPL(dw_pcie_writeb_dbi); + +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) +{ + return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1); +} +EXPORT_SYMBOL_GPL(dw_pcie_readb_dbi); + static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ea8d1caf11c5..86df36701a37 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -265,35 +265,12 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type); void dw_pcie_setup(struct dw_pcie *pci); -static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) -{ - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val); -} - -static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) -{ - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4); -} - -static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) -{ - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val); -} - -static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) -{ - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2); -} - -static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) -{ - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val); -} - -static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) -{ - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1); -} +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val); +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg); +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val); +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg); +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val); +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg); static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) {